SN74HCS16507PWR [TI]
SN74HCS16507 8-Bit Parallel-Load Shift Registers with Open-Drain Outputs;
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SN74HCS16507
SCLS829 – AUGUST 2020
SN74HCS16507 8-Bit Parallel-Load Shift Registers with Open-Drain Outputs
1 Features
3 Description
•
•
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
The SN74HCS16507 is a parallel- or serial-in, serial-
out 8-bit shift register with open-drain outputs and
Schmitt-trigger inputs.
•
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
7.8-mA output drive at 6 V
Extended ambient temperature range: –40°C to
+125°C, TA
Device Information
PART NUMBER
SN74HCS16507PW
SN74HCS16507D
PACKAGE(1)
TSSOP (16)
SOIC (16)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
9.90 mm × 3.90 mm
•
•
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Increase the Number of Inputs on a Microcontroller
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Benefits of Schmitt-trigger inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS16507
SCLS829 – AUGUST 2020
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Characteristics ................................................5
6.7 Switching Characteristics............................................6
6.8 Operating Characteristics........................................... 7
6.9 Typical Characteristics................................................8
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................13
9.1 Reference................................................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................16
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Receiving Notification of Documentation Updates..17
12.3 Support Resources................................................. 17
12.4 Trademarks.............................................................17
12.5 Electrostatic Discharge Caution..............................17
12.6 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
DATE
REVISION
NOTES
August 2020
*
Initial Release
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5 Pin Configuration and Functions
SH/LD
CLK
E
VCC
1
2
3
4
5
6
16
CLK INH
15
14
D
C
B
A
F
13
12
11
10
9
G
H
QH
SER
QH
7
8
GND
D or PW Package 16-Pin SOIC or TSSOP Top View
Table 5-1. Pin Functions
PIN
I/O
DESCRIPTION
SOIC or TSSOP
NO.
NAME
1
SH/LD
I
I
Enable shifting when input is high, load data when input is low
Clock, rising edge triggered
Parallel input E
2
CLK
3
E
F
I
4
I
Parallel input F
5
G
I
Parallel input G
6
H
I
Parallel input H
7
Q H
GND
QH
SER
A
O
—
O
I
Inverted serial output, open drain
Ground
8
9
Serial output, open drain
Serial input
10
11
12
13
14
15
16
I
Parallel input A
B
I
Parallel input B
C
I
Parallel input C
D
I
Parallel input D
CLK INH
VCC
I
Clock inhibit input
—
Positive supply
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
VCC
IIK
Supply voltage
–0.5
Input clamp current(2)
VI < –0.5 V or VI > VCC + 0.5 V
VI < –0.5 V or VI > VCC + 0.5 V
VO = 0 to VCC
±20
±20
35
mA
mA
mA
mA
°C
IOK
IO
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
Storage temperature
±70
150
150
TJ
Tstg
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/
JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
5
0
VCC
VCC
125
V
VO
TA
Output voltage
Ambient temperature
0
V
–40
°C
6.4 Thermal Information
SN74HCS16507
PW (TSSOP)
THERMAL METRIC(1)
D (SOIC)
16 PINS
122.2
80.9
UNIT
16 PINS
141.2
78.8
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
85.8
80.6
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
27.7
40.4
ΨJB
85.5
80.3
RθJC(bot)
N/A
N/A
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
TYP
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
3.15
4.2
V
V
V
V
2 V
1.0
VT-
Negative switching threshold
Hysteresis (VT+ - VT-)(1)
Low-level output voltage
4.5 V
6 V
2.2
3.0
2 V
1.0
ΔVT
4.5 V
6 V
1.4
1.6
IOL = 20 µA
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
2 V to 6 V
4.5 V
6 V
0.002
0.18
0.22
±100
0.1
0.1
VOL
0.30
0.33
II
Input leakage current
Supply current
VI = VCC or 0
6 V
±1000 nA
ICC
Ci
VI = VCC or 0, IO = 0
6 V
2
5
µA
pF
Input capacitance
2 V to 6 V
(1) Guaranteed by design.
6.6 Timing Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement
Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
–40°C to 125°C
UNIT
MAX
49
MIN
MAX
2 V
43
120
150
fclock
Clock frequency
Pulse duration
4.5 V
6 V
130
170
MHz
2 V
6
6
6
7
6
6
7
7
SH/LD low
4.5 V
6 V
7
tw
ns
2 V
11
7
CLK high or low
4.5 V
6 V
7
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CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement
Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
–40°C to 125°C
UNIT
MAX
MIN
21
7
MAX
2 V
13
5
4
8
4
4
6
4
4
6
4
4
9
4
4
0
0
0
5
4
3
0
0
0
SH/LD high before
CLK↑
4.5 V
6 V
6
2 V
14
6
SER before CLK↑
4.5 V
6 V
6
2 V
9
tsu
CLK INH low before
CLK↑
Setup time
4.5 V
6 V
5
ns
5
2 V
9
CLK INH high
before CLK↑
4.5 V
6 V
5
5
2 V
17
6
Data before SH/LD↑ 4.5 V
6 V
6
2 V
0
Ser data after CLK↑ 4.5 V
0
6 V
0
2 V
6
th
PAR data after
4.5 V
Hold time
5
ns
SH/LD↑
6 V
4
2 V
0
SH/LD high after
4.5 V
0
CLK↑
6 V
0
6.7 Switching Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement
Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
TYP
–40°C to 125°C
MIN TYP MAX
UNIT
MIN
49
MAX
2 V
43
120
150
fmax
Max switching frequency
4.5 V
6 V
130
170
MHz
2 V
39
19
17
32
16
14
30
15
14
65
24
19
45
18
16
48
18
16
SH/LD
QH or Q H 4.5 V
6 V
2 V
tpd
Propagation delay
CLK
H
QH or Q H 4.5 V
ns
6 V
2 V
QH or Q H 4.5 V
6 V
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CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement
Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
TYP
–40°C to 125°C
MIN TYP MAX
UNIT
MIN
MAX
2 V
9
5
4
17
8
tt
Transition-time
Any output 4.5 V
6 V
ns
7
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Power dissipation capacitance
per gate
Cpd
No load
2 V to 6 V
20
pF
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6.9 Typical Characteristics
TA = 25°C
46
44
42
40
38
36
34
32
30
28
26
0.2
0.18
0.16
0.14
0.12
0.1
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 2.5 V
VCC = 3.3 V
0.08
0.06
0.04
0.02
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
0.5
1
1.5
2
2.5
3
3.5
VI œ Input Voltage (V)
Figure 6-1. Output driver resistance in LOW state. Figure 6-2. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
0.65
VCC = 4.5 V
0.6
0.55
VCC = 5 V
0.5
VCC = 6 V
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
Figure 6-3. Supply current across input voltage, 4.5-, 5-, and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
tw
VCC
Test
Point
VCC
0 V
S1
Input
50%
50%
RL
From Output
Under Test
Figure 7-2. Voltage Waveforms, Pulse Duration
(1)
CL
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Open-Drain Outputs
VCC
VCC
Clock
Input
Input
Output
Output
50%
50%
50%
0 V
VOH
VOL
VOH
VOL
0 V
(1)
(2)
tPLZ
tPZL
tsu
th
VCC
Data
Input
50%
50%
50%
10% VCC
0 V
(2)
(1)
tPZL
tPLZ
Figure 7-3. Voltage Waveforms, Setup and Hold
Times
50%
10%
(1) The greater between tPLZ and tPZL is the same as tpd
.
Figure 7-4. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
The SN74HCS16507 is a parallel- or serial-in, serial-out 8-bit shift register with Schmitt-trigger inputs and open-
drain outputs.
This device has two modes of operation: load data, and shift data.
When the shift or load (SH/LD) input is held in the low state, the internal registers are loaded with data from the
eight lettered inputs (A-H). This operation is asynchronous. In this state, the output (Q) will have the same state
as the input H, while the inverted output (Q) will have the opposite state.
When the shift or load (SH/LD) input is held in the high state, the internal registers hold their current state until a
clock pulse is received. On the rising edge of the clock (CLK) input, data from the serial input will be loaded into
the first register, and the data in the internal registers will be shifted by one place. The last register will lose its
value. The output (Q) will always be in the same state as the last register, and the inverted output (Q) will have
the opposite state. The clock inhibit (CLK INH) input can be held high to prevent clock pulses from being
detected. CLK and CLK INH are interchangable inputs.
8.2 Functional Block Diagram
Figure 8-1. Logic Diagram (Positive Logic) for SN74HCS16507
A
H
B
C
D
E
F
G
SH/LD
5 Additional
Shift Register
Stages
S
D
R
Q
S
D
R
Q
S
D
R
Q
Q
QH
QH
SER
CLK INH
CLK
8.3 Feature Description
8.3.1 Open-Drain CMOS Outputs
This device includes open-drain CMOS outputs. Open-drain outputs can only drive the output low. When in the
high logical state, open-drain outputs will be in a high-impedance state. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to
overcurrent. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all
times.
When placed into the high-impedance state, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to
the node, then this is known as a floating node and the voltage is unknown. A pull-up resistor can be connected
to the output to provide a known voltage at the output while it is in the high-impedance state. The value of the
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resistor will depend on multiple factors, including parasitic capacitance and power consumption limitations.
Typically, a 10 kΩ resistor can be used to meet these requirements.
Unused open-drain CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip-
flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.3.4 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
+IIK
+IOK
Input
Output
Logic
GND
-IIK
-IOK
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
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8.4 Device Functional Modes
The Operating Mode Table and the Output Function Table list the functional modes of the SN74HCS16507.
Table 8-1. Operating Mode Table
INPUTS(1)
FUNCTION
SH/LD
CLK
X
CLK INH
L
X
X
H
↑
Parallel load
No change
No change
Shift(2)
H
H
H
H
H
X
L
↑
L
Shift(2)
(1) H = High Voltage Level, L = Low Voltage Level, X = Don't Care,
↑ = Low to High transition
(2) Shift : Content of each internal register shifts towards serial
output QH. Data at SER is shifted into the first register.
Table 8-2. Output Function Table
INTERNAL REGISTERS(1) (2)
OUTPUTS(2)
A — G
H
L
Q
L
Q
Z
L
X
X
H
Z
(1) Internal registers refer to the shift registers inside the device.
These values are set by either loading data from the parallel
inputs, or by clocking data in from the serial input.
(2) H = High Voltage Level, L = Low Voltage Level, X = Don't Care,
Z = High Impedance
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes. Customers should validate and test their design
implementation to confirm system functionality.
9.1 Reference
The SN74HCS16507 is a parallel-input shift register, which can be used to reduce the number of required inputs
on a system controller very significantly in some applications. Parallel data is loaded into the shift register, then
the stored data can be loaded into a serial input of the system controller by clocking the shift register.
Multiple shift registers can be cascaded to provide more data inputs while still only using a single serial input to
the system controller. This process is primarily limited by the required data input rate and timing characteristics
of the selected shift register, as defined in the Timing Charactestics and Switching Charactestics tables.
An example block diagram is shown for using a single shift register in the Typical application block diagram
below.
9.2 Typical Application
DATA[7:0]
A B C D E F G H
VCC
SH/LD
Data Loading Gates
10 kꢀ
QH
SER
8-Bit Shift Register
Peripheral
System
Controller
QH
CLK
Control
Logic
CLK INH
Figure 9-1. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the maximum static supply current, ICC
,
listed in Electrical Characteristics and any transient current required for switching.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS16507 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS16507 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to
exceed 50 pF.
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The SN74HCS16507 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOL. When outputting in the high state, the output
voltage in the equation is defined as the difference between the measured output voltage and the supply voltage
at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS16507, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS16507 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics.
Open-drain outputs can be connected together directly to produce a wired-AND configuration or for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC
.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS16507 to the receiving device(s).
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3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
DATA[7:0]
SH/LD
CLK
0x00
0x11
0x00
QH
Figure 9-2. Application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1 ꢀF
16
SH/LD
1
VCC
CLK
E
2
3
4
5
6
7
8
15
14
13
12
11
10
9
CLK INH
D
C
B
A
F
G
Avoid 90°
corners for
signal lines
H
QH
Unused output
left floating
Unused input
tied to VCC
SER
QH
GND
Figure 11-1. Example layout for the SN74HCS16507 in the PW package.
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report (SCLA007)
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74HCS16507DR
PREVIEW
ACTIVE
SOIC
D
16
16
2500
2000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
SN74HCS16507PWR
TSSOP
PW
Green (RoHS
& no Sb/Br)
NIPDAU | SN
Level-1-260C-UNLIM
H16507
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
12-Sep-2020
OTHER QUALIFIED VERSIONS OF SN74HCS16507 :
Automotive: SN74HCS16507-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2020
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS16507PWR
SN74HCS16507PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
330.0
330.0
16.4
12.4
6.8
6.9
5.4
5.6
1.6
1.6
8.0
8.0
16.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Sep-2020
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCS16507PWR
SN74HCS16507PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
366.0
367.0
364.0
367.0
50.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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