SN74HCS21QDRQ1 [TI]
具有施密特触发输入的汽车类双路 4 输入与门 | D | 14 | -40 to 125;
| 型号： | SN74HCS21QDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有施密特触发输入的汽车类双路 4 输入与门 | D | 14 | -40 to 125 |
| 文件： | 总21页 (文件大小：679K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Support &
Community
Product
Folder
Order
Now
Tools &
Software
Technical
Documents
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
具有施密特触发输入的 SN74HCS21-Q1 汽车类双路 4 输入与门
1 特性
2 应用
1
•
符合面向汽车 应用的 AEC-Q100 标准：
•
•
将电源正常信号进行结合
使能数字信号
–
–
–
器件温度等级 1：–40°C 至 +125°C，TA
器件 HBM ESD 分类等级 2
3 说明
器件 CDM ESD 分类等级 C6
此器件包含两个具有施密特触发输入的独立 4 输入与
门。每个逻辑门以正逻辑执行布尔函数 Y = A ● B ● C
● D。
•
•
•
宽工作电压范围：2V 至 6V
施密特触发输入可实现慢速或高噪声输入信号
低功耗
–
–
I
CC 典型值为 100nA
器件信息(1)
输入泄漏电流典型值为 ±100nA
器件型号
SN74HCS21QPWRQ1 TSSOP (14)
SN74HCS21QDRQ1 SOIC (14)
封装
封装尺寸（标称值）
5.00mm × 4.40mm
8.70mm × 3.90mm
•
电压为 5V 时，输出驱动为 ±7.8mA
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
施密特触发输入的优势
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS761
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
www.ti.com.cn
目录
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 5
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 器件和文档支持 ..................................................... 13
12.1 文档支持................................................................ 13
12.2 相关链接................................................................ 13
12.3 社区资源................................................................ 13
12.4 商标....................................................................... 13
12.5 静电放电警告......................................................... 13
12.6 Glossary................................................................ 13
13 机械、封装和可订购信息....................................... 13
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2020 年 2 月
*
初始发行版。
2
Copyright © 2020, Texas Instruments Incorporated
SN74HCS21-Q1
www.ti.com.cn
ZHCSKY5 –FEBRUARY 2020
5 Pin Configuration and Functions
D or PW Package
14-Pin SOIC or TSSOP
Top View
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
VCC
2D
2C
NC
2B
2A
2Y
NC
1C
1D
1Y
8
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
1A
NO.
1
Input
Input
—
Channel 1, Input A
1B
2
Channel 1, Input B
Not internally connected
Channel 1, Input C
Channel 1, Input D
Channel 1, Output Y
Ground
NC
1C
3, 11
4
Input
Input
Output
—
1D
5
1Y
6
GND
2Y
7
8
Output
Input
Input
Input
Input
—
Channel 2, Output Y
Channel 2, Input A
Channel 2, Input B
Channel 2, Input C
Channel 2, Input D
Positive Supply
2A
9
2B
10
12
13
14
2C
2D
VCC
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
IIK
IOK
IO
Supply voltage
–0.5
7
V
VI < –0.5 or VI > VCC
0.5
+
Input clamp current(2)
±20
±20
mA
mA
VO < –0.5 or VO > VCC
0.5
+
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
VO = 0 to VCC
±35
±50
150
150
mA
mA
°C
TJ
Tstg
Storage temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Do not exceed the absolute
maximum voltage supply rating.
(3) Guaranteed by design.
Copyright © 2020, Texas Instruments Incorporated
3
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
www.ti.com.cn
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±4000
±1500
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C6
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
Δt/Δv
TA
Input transition rise and fall rate
Ambient temperature
Unlimited
125
ns/V
°C
–40
6.4 Thermal Information
SN74HCS21-Q1
PW (TSSOP)
THERMAL METRIC
D (SOIC)
14 PINS
133.6
89.0
UNIT
14 PINS
151.7
79.4
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
94.7
89.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.2
45.5
ΨJB
94.1
89.1
RθJC(bot)
N/A
N/A
6.5 Electrical Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
TYP
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
1.7
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
V
V
V
V
V
2.1
2 V
0.3
VT-
Negative switching threshold
4.5 V
6 V
0.9
1.2
2 V
0.2
ΔVT Hysteresis (VT+ - VT-
)
4.5 V
6 V
0.4
0.6
IOH = -20 µA
VI = VIH or VIL IOH = -6 mA
IOH = -7.8 mA
2 V to 6 V
4.5 V
6 V
VCC – 0.1
4
VCC – 0.002
4.3
VOH High-level output voltage
5.4
5.75
IOL = 20 µA
2 V to 6 V
4.5 V
6 V
0.002
0.18
0.1
0.30
0.33
VOL
Low-level output voltage
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
0.22
II
Input leakage current
Supply current
VI = VCC or 0
6 V
±100
0.1
±1000 nA
ICC
Ci
VI = VCC or 0, IO = 0
6 V
2
5
µA
pF
Input capacitance
2 V to 6 V
4
Copyright © 2020, Texas Instruments Incorporated
SN74HCS21-Q1
www.ti.com.cn
ZHCSKY5 –FEBRUARY 2020
Electrical Characteristics (continued)
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Power dissipation capacitance
per gate
Cpd
No load
2 V to 6 V
10
pF
6.6 Switching Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). See the
Parameter Measurement Information.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2 V
MIN
TYP
22
9
MAX UNIT
52
tpd
Propagation delay
A or B
Y
Y
4.5 V
6 V
22
16
17
8
ns
ns
8
2 V
9
tt
Transition-time
4.5 V
6 V
5
4
7
6.7 Typical Characteristics
TA = 25°C
46
44
42
40
38
36
34
32
30
28
26
70
65
60
55
50
45
40
35
30
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Source Current (mA)
图 1. Output driver resistance in Low state
图 2. Output driver resistance in High state
0.2
0.18
0.16
0.14
0.12
0.1
0.65
VCC = 2 V
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0.6
0.55
0.5
VCC = 2.5 V
VCC = 3.3 V
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
VI œ Input Voltage (V)
图 3. Typical supply current versus input voltage across
图 4. Typical supply current versus input voltage across
common supply values (2 V to 3.3 V)
common supply values (4.5 V to 6 V)
版权 © 2020, Texas Instruments Incorporated
5
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
www.ti.com.cn
7 Parameter Measurement Information
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
•
The outputs are measured one at a time, with one input transition per measurement.
Test
90%
Point
VCC
0 V
VOH
VOL
90%
Input
10%
tf(1)
10%
tr(1)
From Output
Under Test
(1)
90%
10%
CL
90%
Output
10%
tf(1)
tr(1)
CL= 50 pF and includes probe and jig capacitance.
图 5. Load Circuit
图 6. Voltage Waveforms
Transition Times
VCC
Input
50%
50%
0 V
VOH
VOL
VOH
VOL
(1)
(1)
tPLH
tPHL
Output
50%
50%
(1)
(1)
tPHL
tPLH
Output
50%
50%
The maximum between tPLH and TPHL is used for tpd
.
图 7. Voltage Waveforms
Propagation Delays
6
版权 © 2020, Texas Instruments Incorporated
SN74HCS21-Q1
www.ti.com.cn
ZHCSKY5 –FEBRUARY 2020
8 Detailed Description
8.1 Overview
This device contains two independent 4-input AND Gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A ● B ● C ● D in positive logic.
8.2 Functional Block Diagram
One of Two Channels
xA
xB
xY
xC
xD
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in 图 8.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
版权 © 2020, Texas Instruments Incorporated
7
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
www.ti.com.cn
Feature Description (接下页)
VCC
Logic
GND
Device
+IIK
+IOK
Input
Output
-IIK
-IOK
图 8. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
表 1. Function Table
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
C
H
X
X
L
D
H
X
X
X
L
H
L
L
L
L
X
X
X
X
X
X
8
版权 © 2020, Texas Instruments Incorporated
SN74HCS21-Q1
www.ti.com.cn
ZHCSKY5 –FEBRUARY 2020
9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In this application, one channel of the SN74HCS21-Q1 is used as shown in 图 9. The additional channel can be
used individually or the inputs can be grounded and the channel left unused.
The SN74HCS21-Q1 is used to drive the RESET pin of the system controller. When any of the inputs to the
gates become LOW, the controller will be disabled. The controller will only operate when all inputs are HIGH,
indicating normal operation.
9.2 Typical Application
Over Current
Power Supply
Detection
Motor Controller
OC
PG
RESET
ON/OFF
CASE
Case Tamper
On/Off Switch
Switch
图 9. Typical application block diagram
9.2.1 Design Requirements
•
•
•
All signals in the system operate at 5 V
All inputs must be HIGH for normal operation
Any input switching to LOW will force the output LOW
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HCS21-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device
can only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not
to exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
The SN74HCS21-Q1 can drive a load with a total capacitance less than or equal to 50 pF connected to a high-
impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
版权 © 2020, Texas Instruments Incorporated
9
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
www.ti.com.cn
Typical Application (接下页)
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS21-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS21-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics. The plots in and provide a
typical relationship between output voltage and current for this device.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS21-
Q1 to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
10
版权 © 2020, Texas Instruments Incorporated
SN74HCS21-Q1
www.ti.com.cn
ZHCSKY5 –FEBRUARY 2020
Typical Application (接下页)
9.2.3 Application Curves
OC
PG
ON/OFF
OT
RESET
图 10. Application timing diagram
版权 © 2020, Texas Instruments Incorporated
11
SN74HCS21-Q1
ZHCSKY5 –FEBRUARY 2020
www.ti.com.cn
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in 图
11.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to
the device
0.1 ꢀF
1A
1B
14
1
2
3
4
5
6
7
VCC
13
12
11
10
9
2D
2C
NC
2B
2A
2Y
Unused inputs
tied to VCC
NC
1C
1D
1Y
Avoid 90°
corners for
signal lines
GND
8
图 11. Example layout for the SN74HCS21-Q1
12
版权 © 2020, Texas Instruments Incorporated
SN74HCS21-Q1
www.ti.com.cn
ZHCSKY5 –FEBRUARY 2020
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
《借助全新的 HCS 逻辑系列降低噪声和功耗》
《CMOS 功耗与 CPD 计算》
《使用逻辑器件进行设计》
12.2 相关链接
下表列出了快速访问链接。类别包括技术文档、支持与社区资源、工具和软件，以及申请样片或购买产品的快速链
接。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
版权 © 2020, Texas Instruments Incorporated
13
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74HCS21QDRQ1
SN74HCS21QPWRQ1
ACTIVE
ACTIVE
SOIC
D
14
14
2500 RoHS & Green
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
HC21Q1
HCS21Q1
TSSOP
PW
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
UL1042
UL1042 - Uk砤d zr體nowa縪nego mieszacza iloczynowegoWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZXFV201
QUAD VIDEO AMPLIFIERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
ZXFV201N14
IC-SM-VIDEO AMPWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
ZXFV201N14TA
QUAD VIDEO AMPLIFIERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
ZXFV201N14TC
QUAD VIDEO AMPLIFIERWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZXFV302N16
IC-SM-4:1 MUX SWITCHWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ETC
ZXFV4089
VIDEO AMPLIFIER WITH DC RESTORATIONWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
ZETEX
©2020 ICPDF网 联系我们和版权申明