SN74HCS21 [TI]
具有施密特触发器输入的双路 4 输入与门;
| 型号： | SN74HCS21 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有施密特触发器输入的双路 4 输入与门 触发器 |
| 文件： | 总22页 (文件大小：546K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74HCS21
SCLS793A –MARCH 2020–REVISED JUNE 2020
SN74HCS21 Dual 4-Input AND Gates with Schmitt-Trigger Inputs
1 Features
3 Description
This device contains two independent 4-input AND
gates with Schmitt-trigger inputs. Each gate performs
the Boolean function Y = A ● B ● C ● D in positive
logic.
1
•
•
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
•
Low power consumption
Device Information(1)
–
–
Typical ICC of 100 nA
PART NUMBER
SN74HCS21PWR
SN74HCS21DR
PACKAGE
TSSOP (14)
SOIC (14)
BODY SIZE (NOM)
5.00 mm × 4.40 mm
8.70 mm × 3.90 mm
Typical input leakage current of ±100 nA
•
•
±7.8-mA output drive at 5 V
Extended ambient temperature range: –40°C to
+125°C, TA
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
•
Combining power good signals
Enable digital signals
Benefits of Schmitt-trigger Inputs
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCS21
SCLS793A –MARCH 2020–REVISED JUNE 2020
www.ti.com
Table of Contents
8.3 Feature Description................................................... 7
8.4 Device Functional Modes.......................................... 8
Application and Implementation .......................... 9
9.1 Application Information.............................................. 9
9.2 Typical Application .................................................... 9
1
2
3
4
5
6
Features.................................................................. 1
Applications ........................................................... 1
Description ............................................................. 1
Revision History..................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 3
6.1 Absolute Maximum Ratings ...................................... 3
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 4
6.6 Switching Characteristics.......................................... 5
6.7 Typical Characteristics.............................................. 5
Parameter Measurement Information .................. 6
Detailed Description .............................................. 7
8.1 Overview ................................................................... 7
8.2 Functional Block Diagram ......................................... 7
9
10 Power Supply Recommendations ..................... 12
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1 Documentation Support ........................................ 13
12.2 Related Links ........................................................ 13
12.3 Community Resources.......................................... 13
12.4 Trademarks........................................................... 13
12.5 Electrostatic Discharge Caution............................ 13
12.6 Glossary................................................................ 13
7
8
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (March 2020) to Revision A
Page
•
•
Added D package to data sheet ............................................................................................................................................ 1
Added D Package to Thermal Information Table ................................................................................................................... 4
2
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SCLS793A –MARCH 2020–REVISED JUNE 2020
5 Pin Configuration and Functions
D or PW Package
14-Pin SOIC or TSSOP
Top View
1
2
3
4
5
6
7
14
13
12
11
10
9
1A
1B
VCC
2D
2C
NC
2B
2A
2Y
NC
1C
1D
1Y
8
GND
Pin Functions
PIN
I/O
DESCRIPTION
NAME
1A
NO.
1
Input
Input
—
Channel 1, Input A
1B
2
Channel 1, Input B
Not internally connected
Channel 1, Input C
Channel 1, Input D
Channel 1, Output Y
Ground
NC
1C
3, 11
4
Input
Input
Output
—
1D
5
1Y
6
GND
2Y
7
8
Output
Input
Input
Input
Input
—
Channel 2, Output Y
Channel 2, Input A
Channel 2, Input B
Channel 2, Input C
Channel 2, Input D
Positive Supply
2A
9
2B
10
12
13
14
2C
2D
VCC
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
VCC
IIK
IOK
IO
Supply voltage
–0.5
7
V
VI < –0.5 or VI > VCC
0.5
+
Input clamp current(2)
±20
±20
mA
mA
VO < –0.5 or VO > VCC
0.5
+
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
VO = 0 to VCC
±35
±70
150
150
mA
mA
°C
TJ
Tstg
Storage temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Do not exceed the absolute
maximum voltage supply rating.
(3) Guaranteed by design.
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6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC
JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
Δt/Δv
TA
Input transition rise and fall rate
Ambient temperature
Unlimited
125
ns/V
°C
–40
6.4 Thermal Information
SN74HCS21
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
151.7
79.4
D (SOIC)
14 PINS
133.6
89.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
94.7
89.5
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.2
45.5
ΨJB
94.1
89.1
RθJC(bot)
N/A
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
TYP
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
1.7
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
V
V
V
V
V
2.1
2 V
0.3
VT-
Negative switching threshold
4.5 V
6 V
0.9
1.2
2 V
0.2
ΔVT Hysteresis (VT+ - VT-
)
4.5 V
6 V
0.4
0.6
IOH = -20 µA
VI = VIH or VIL IOH = -6 mA
IOH = -7.8 mA
2 V to 6 V
4.5 V
6 V
VCC – 0.1
4
VCC – 0.002
4.3
VOH High-level output voltage
5.4
5.75
IOL = 20 µA
2 V to 6 V
4.5 V
6 V
0.002
0.18
0.1
0.30
0.33
VOL
Low-level output voltage
Input leakage current
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
0.22
II
VI = VCC or 0
6 V
±100
±1000 nA
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Electrical Characteristics (continued)
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted).
PARAMETER
Supply current
TEST CONDITIONS
VI = VCC or 0, IO = 0
VCC
MIN
TYP
MAX UNIT
ICC
Ci
6 V
0.1
2
5
µA
pF
Input capacitance
2 V to 6 V
Power dissipation capacitance
per gate
Cpd
No load
2 V to 6 V
10
pF
6.6 Switching Characteristics
over operating free-air temperature range; typical ratings measured at TA = 25°C (unless otherwise noted). See the
Parameter Measurement Information.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2 V
MIN
TYP
22
9
MAX UNIT
52
tpd
Propagation delay
A or B
Y
Y
4.5 V
6 V
22
16
17
8
ns
ns
8
2 V
9
tt
Transition-time
4.5 V
6 V
5
4
7
6.7 Typical Characteristics
TA = 25°C
46
44
42
40
38
36
34
32
30
28
26
70
65
60
55
50
45
40
35
30
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Source Current (mA)
Figure 1. Output driver resistance in Low state
Figure 2. Output driver resistance in High state
0.2
0.18
0.16
0.14
0.12
0.1
0.65
VCC = 2 V
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0.6
0.55
0.5
VCC = 2.5 V
VCC = 3.3 V
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
VI œ Input Voltage (V)
Figure 3. Typical supply current versus input voltage across
common supply values (2 V to 3.3 V)
Figure 4. Typical supply current versus input voltage across
common supply values (4.5 V to 6 V)
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7 Parameter Measurement Information
•
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
•
The outputs are measured one at a time, with one input transition per measurement.
Test
90%
Point
VCC
0 V
VOH
VOL
90%
Input
10%
tf(1)
10%
tr(1)
From Output
Under Test
(1)
90%
10%
CL
90%
Output
10%
tf(1)
tr(1)
CL= 50 pF and includes probe and jig capacitance.
Figure 5. Load Circuit
Figure 6. Voltage Waveforms
Transition Times
VCC
0 V
VOH
VOL
VOH
VOL
Input
50%
50%
(1)
(1)
tPLH
tPHL
Output
50%
50%
(1)
(1)
tPHL
tPLH
Output
50%
50%
The maximum between tPLH and TPHL is used for tpd
.
Figure 7. Voltage Waveforms
Propagation Delays
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8 Detailed Description
8.1 Overview
This device contains two independent 4-input AND gates with Schmitt-trigger inputs. Each gate performs the
Boolean function Y = A ● B ● C ● D in positive logic.
8.2 Functional Block Diagram
One of Two Channels
xA
xB
xY
xC
xD
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined in the Absolute Maximum Ratings must be followed at all times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
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Feature Description (continued)
VCC
Logic
GND
Device
+IIK
+IOK
Input
Output
-IIK
-IOK
Figure 8. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Table 1. Function Table
INPUTS
OUTPUT
Y
A
H
L
B
H
X
L
C
H
X
X
L
D
H
X
X
X
L
H
L
L
L
L
X
X
X
X
X
X
8
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
In this application, one channel of the SN74HCS21 is used as shown in Figure 9. The additional channel can be
used individually or the inputs can be grounded and the channel left unused.
The SN74HCS21 is used to drive the RESET pin of the system controller. When any of the inputs to the gates
become LOW, the controller will be disabled. The controller will only operate when all inputs are HIGH, indicating
normal operation.
9.2 Typical Application
Over Current
Power Supply
Detection
Motor Controller
OC
PG
RESET
ON/OFF
CASE
Case Tamper
On/Off Switch
Switch
Figure 9. Typical application block diagram
9.2.1 Design Requirements
•
•
•
All signals in the system operate at 5 V
All inputs must be HIGH for normal operation
Any input switching to LOW will force the output LOW
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The supply must be capable of sourcing current equal to the total current to be sourced by all outputs of the
SN74HCS21 plus the maximum supply current, ICC, listed in the Electrical Characteristics. The logic device can
only source or sink as much current as it is provided at the supply and ground pins, respectively. Be sure not to
exceed the maximum total current through GND or VCC listed in the Absolute Maximum Ratings.
The SN74HCS21 can drive a load with a total capacitance less than or equal to 50 pF connected to a high-
impedance CMOS input while still meeting all of the datasheet specifications. Larger capacitive loads can be
applied, however it is not recommended to exceed 70 pF.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
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Typical Application (continued)
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings,
is an additional limitation to prevent damage to the device. Do not violate any values
listed in the Absolute Maximum Ratings. These limits are provided to prevent damage
to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS21, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ resistor
value is often used due to these factors.
The SN74HCS21 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. Similarly, the
ground voltage is used to produce the output LOW voltage. Sinking current into the output will increase the
output voltage as specified by the VOL specification in the Electrical Characteristics. The plots in and provide a
typical relationship between output voltage and current for this device.
Unused outputs can be left floating.
Refer to Feature Description for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout.
2. Ensure the capacitive load at the output is ≤ 70 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the SN74HCS21
to the receiving device.
3. Ensure the resistive load at the output is larger than (VCC / 25 mA) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation
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Typical Application (continued)
9.2.3 Application Curves
OC
PG
ON/OFF
OT
RESET
Figure 10. Application timing diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
Figure 11.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to
the device
0.1 ꢀF
1A
1B
14
1
2
3
4
5
6
7
VCC
13
12
11
10
9
2D
2C
NC
2B
2A
2Y
Unused inputs
tied to VCC
NC
1C
1D
1Y
Avoid 90°
corners for
signal lines
GND
8
Figure 11. Example layout for the SN74HCS21
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12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
Reduce Noise and Save Power with the New HCS Logic Family
CMOS Power Consumption and CPD Calculation
Designing with Logic
12.2 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
12.3 Community Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74HCS21DR
ACTIVE
ACTIVE
SOIC
D
14
14
2500 RoHS & Green
2000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
HCS21
HCS21
SN74HCS21PWR
TSSOP
PW
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
OTHER QUALIFIED VERSIONS OF SN74HCS21 :
Automotive: SN74HCS21-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS21DR
SN74HCS21DR
SN74HCS21PWR
SN74HCS21PWR
SOIC
SOIC
D
D
14
14
14
14
2500
2500
2000
2000
330.0
330.0
330.0
330.0
16.4
16.4
12.4
12.4
6.5
6.6
9.0
9.3
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
TSSOP
TSSOP
PW
PW
6.85
6.9
5.45
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCS21DR
SN74HCS21DR
SN74HCS21PWR
SN74HCS21PWR
SOIC
SOIC
D
D
14
14
14
14
2500
2500
2000
2000
356.0
366.0
366.0
356.0
356.0
364.0
364.0
356.0
35.0
50.0
50.0
35.0
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022, Texas Instruments Incorporated
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