SN74HCS541-Q1 [TI]
具有三态输出和施密特触发输入的汽车类八路缓冲器和线路驱动器;
| 型号： | SN74HCS541-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出和施密特触发输入的汽车类八路缓冲器和线路驱动器 驱动 驱动器 |
| 文件： | 总28页 (文件大小：1933K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74HCS541-Q1
ZHCSPC4A –NOVEMBER 2021 –REVISED FEBRUARY 2022
具有施密特触发输入、三态输出和直通引脚排列的SN74HCS541-Q1 汽车类八
路缓冲器和线路驱动器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
SN74HCS541-Q1 包含三态输出和施密特触发输入的
八路缓冲器。低电平有效输出能够使引脚（OE1、
OE2）控制所有八个通道，并配置为必须为低电平以使
输出有效。
– 器件温度等级1：
–40°C 至+125°C，TA
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C6
• 采用具有可润湿侧翼的QFN (WRKS) 封装
• 宽工作电压范围：2V 至6V
• 施密特触发输入可耐受慢速或高噪声输入信号
• 低功耗
器件信息
封装(1)
器件型号
封装尺寸（标称值）
6.50mm × 4.40mm
4.50mm x 2.50mm
SN74HCS541PW-Q1
TSSOP (20)
SN74HCS541WRKS-Q1 VQFN (20)
– ICC 典型值为100nA
– 输入泄漏电流典型值为±100nA
• 电压为6V 时，输出驱动为±7.8mA
(1) 如需了解所有可用封装，请见数据表末尾的可订购产品附录。
2 应用
• 启用或禁用数字信号
• 消除慢速或高噪声输入信号
• 在控制器复位期间保持信号
• 对开关进行去抖
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
施密特触发输入的优势
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS859
SN74HCS541-Q1
ZHCSPC4A –NOVEMBER 2021 –REVISED FEBRUARY 2022
www.ti.com.cn
Table of Contents
8.3 Feature Description.....................................................8
8.4 Device Functional Modes..........................................10
9 Application and Implementation.................................. 11
9.1 Application Information..............................................11
9.2 Typical Application.................................................... 11
10 Power Supply Recommendations..............................14
11 Layout...........................................................................14
11.1 Layout Guidelines................................................... 14
11.2 Layout Example...................................................... 14
12 Device and Documentation Support..........................15
12.1 Documentation Support.......................................... 15
12.2 接收文档更新通知................................................... 15
12.3 支持资源..................................................................15
12.4 Trademarks.............................................................15
12.5 Electrostatic Discharge Caution..............................15
12.6 术语表..................................................................... 15
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics............................................5
6.7 Operating Characteristics........................................... 5
6.8 Typical Characteristics................................................6
7 Parameter Measurement Information............................7
8 Detailed Description........................................................8
8.1 Overview.....................................................................8
8.2 Functional Block Diagram...........................................8
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (November 2021) to Revision A (February 2022)
Page
• 将数据表从“预告信息”更改为“量产数据”....................................................................................................1
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5 Pin Configuration and Functions
OE1 VCC
OE1
1
20
VCC
1
20
A1
A2
A3
A4
A5
A6
A7
A8
2
3
4
5
6
7
8
9
19
18
OE2
Y1
A1
A2
2
3
19
18
OE2
Y1
A3
A4
A5
A6
4
5
6
7
17 Y2
17
16
Y2
Y3
Y4
16
15
Y3
Y4
15
14
PAD
Y5
14 Y5
13
12
11
A7
A8
8
9
Y6
Y7
Y6
Y7
13
12
GND
10
Y8
10 11
GND
Y8
PW package
20-Pin TSSOP
Top View
WRKS Package
20-Pin VQFN
Top View
Pin Functions
PIN
I/O
DESCRIPTION
NAME
OE1
A1
NO.
1
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output enable input 1, active low
Input for channel 1
Input for channel 2
Input for channel 3
Input for channel 4
Input for channel 5
Input for channel 6
Input for channel 7
Input for channel 8
Ground
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
GND
Y8
10
11
12
13
14
15
16
17
18
19
20
—
Output
Output
Output
Output
Output
Output
Output
Output
Input
Output for channel 8
Output for channel 7
Output for channel 6
Output for channel 5
Output for channel 4
Output for channel 3
Output for channel 2
Output for channel 1
Output enable input 2, active low
Postive supply
Y7
Y6
Y5
Y4
Y3
Y2
Y1
OE2
VCC
—
—
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
or supply.
Thermal Pad(1)
(1) WRKS package only.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX UNIT
VCC
IIK
Supply voltage
7
±20
±20
±35
±70
150
150
V
–0.5
Input clamp current(2)
VI < -0.5 V or VI > VCC + 0.5 V
VO < -0.5 V or VO > VCC + 0.5 V
VO = 0 to VCC
mA
mA
mA
mA
°C
IOK
IO
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
Storage temperature
ICC
TJ
Tstg
°C
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±4000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC Q100-011
CDM ESD Classification Level C4B
±1000
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
5
0
VCC
VCC
125
V
VO
TA
Output voltage
Ambient temperature
0
V
°C
–40
6.4 Thermal Information
SN74HCS541-Q1
THERMAL METRIC(1)
PW (TSSOP)
20 PINS
151.7
79.4
WRKS (VQFN)
20 PINS
83.2
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
82.6
94.7
57.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.2
14.5
ΨJT
94.1
56.4
ΨJB
RθJC(bot)
N/A
40.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
TYP
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
3.15
4.2
1
V
V
V
V
V
2 V
VT-
Negative switching threshold
Hysteresis (VT+ - VT-)
4.5 V
6 V
2.2
3
2 V
1
4.5 V
6 V
1.4
1.6
ΔVT
VOH
VOL
IOH = -20 µA
2 V to 6 V
4.5 V
6 V
VCC –0.1 VCC –0.002
High-level output voltage
VI = VIH or VIL
IOH = -6 mA
IOH = -7.8 mA
4
4.3
5.75
5.4
IOL = 20 µA
2 V to 6 V
4.5 V
6 V
0.002
0.18
0.1
0.3
Low-level output voltage
Input leakage current
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
0.22
0.33
II
VI = VCC or 0
6 V
±100
±1000 nA
±2 µA
Off-state (high-impedance
state) output current
IOZ
VO = VCC or 0
6 V
±0.01
0.1
ICC
Ci
Supply current
VI = VCC or 0, IO = 0
6 V
2
5
µA
pF
Input capacitance
2 V to 6 V
6.6 Switching Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurment Information. CL = 50 pF.
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2 V
MIN
TYP
13
7
MAX UNIT
45
tpd
ten
tdis
tt
Propagation delay
A
Y
Y
Y
4.5 V
6 V
18
16
44
22
18
30
20
19
16
9
ns
ns
ns
ns
6
2 V
15
7
Enable time
Disable time
Transition-time
OE
OE
4.5 V
6 V
6
2 V
12
9
4.5 V
6 V
8
2 V
9
Any
4.5 V
6 V
5
4
8
6.7 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Cpd
Power dissipation capacitance per gate
No load
20
pF
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6.8 Typical Characteristics
TA = 25°C
46
70
65
60
55
50
45
40
35
30
VCC = 2 V
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
44
42
40
38
36
34
32
30
28
26
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Source Current (mA)
图6-1. Output Driver Resistance in LOW State
图6-2. Output Driver Resistance in HIGH State
0.2
0.65
VCC = 2 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
0.6
0.18
0.16
0.55
VCC = 5 V
0.5
VCC = 6 V
0.14
0.12
0.1
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
VI œ Input Voltage (V)
图6-3. Supply Current Across Input Voltage, 2-,
图6-4. Supply Current Across Input Voltage, 4.5-,
2.5-, and 3.3-V Supply
5-, and 6-V Supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
VCC
0 V
VOH
VOL
VOH
VOL
Test
Point
Input
Output
Output
50%
50%
S1
S2
RL
(1)
(1)
From Output
Under Test
tPLH
tPHL
(1)
CL
50%
50%
(1)
(1)
(1) CL includes probe and test-fixture capacitance.
tPHL
tPLH
图7-1. Load Circuit for 3-State Outputs
50%
50%
(1) The greater between tPLH and tPHL is the same as tpd
.
图7-2. Voltage Waveforms Propagation Delays
VCC
VCC
90%
10%
90%
Output
Control
50%
50%
Input
10%
tf(1)
0 V
0 V
VOH
VOL
tr(1)
(3)
(4)
tPZL
tPLZ
≈ VCC
90%
10%
90%
Output
Waveform 1
(1)
S1 at VLOAD
50%
Output
10%
10%
tf(1)
VOL
tr(1)
(3)
(4)
tPZH
tPHZ
(1) The greater between tr and tf is the same as tt.
VOH
Output
Waveform 2
S1 at GND(2)
图7-4. Voltage Waveforms, Input and Output
90%
50%
Transition Times
≈ 0 V
图7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
The SN74HCS541-Q1 contains eight buffers with 3-state outputs and Schmitt-trigger inputs. The active low
output enable pins (OE1, OE2) control all eight channels, and are configured such that both must be low for the
outputs to be active.
When the outputs are enabled, the outputs are actively driving low or high.
When the outputs are disabled, the outputs are set into the high-impedance state.
8.2 Functional Block Diagram
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving
high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar
currents. The drive capability of this device may create fast edges into light loads so routing and load conditions
should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger
currents than the device can sustain without being damaged. It is important for the output power of the device to
be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to
the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can
be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The
value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10 kΩresistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.3.2 CMOS Schmitt-Trigger Inputs
This device includes inputs with the Schmitt-trigger architecture. These inputs are high impedance and are
typically modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics table
from the input to ground. The worst case resistance is calculated with the maximum input voltage, given in the
Absolute Maximum Ratings table, and the maximum input leakage current, given in the Electrical Characteristics
table, using Ohm's law (R = V ÷ I).
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The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics
table, which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much
slower than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the
inputs with slow transitioning signals will increase dynamic current consumption of the device. For additional
information regarding Schmitt-trigger inputs, please see Understanding Schmitt Triggers.
8.3.3 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
+IIK
+IOK
Input
Output
Logic
GND
-IIK
-IOK
图8-1. Electrical Placement of Clamping Diodes for Each Input and Output
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8.3.4 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Standard Lead
We able Flank Lead
Pad
PCB
图8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering which makes QFN packages easier to inspect with
automatic optical inspection (AOI). A wettable flank can be dimpled or step-cut to provide additional surface area
for solder adhesion which assists in reliably creating a side fillet as shown in 图 8-2. Please see the mechanical
drawing for additional details.
8.4 Device Functional Modes
表8-1. Function Table
INPUTS(1)
OUTPUT(2)
OE1
L
OE2
L
A
L
Y
L
L
L
H
X
X
H
Z
Z
H
X
X
H
(1) L = input low, H = input high, X = don't care
(2) L = output low, H = output high, Z = high impedance
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74HCS541-Q1 can be used to drive signals over relatively long traces or transmission lines. In order to
reduce ringing caused by impedance mismatches between the driver, transmission line, and receiver, a series
damping resistor placed in series with the transmitter’s output can be used. The plot in the Application Curve
section shows the received signal with three separate resistor values. Just a small amount of resistance can
make a significant impact on signal integrity in this type of application.
9.2 Typical Application
Rd
1A1
1Y1
1A1
1Y1
System
Controller
Z0
Peripheral
L > 12 cm
Transmitter
Receiver
图9-1. Typical application block diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS541-Q1 plus the maximum static supply current, ICC, listed in Electrical Characteristics
and any transient current required for switching. The logic device can only source as much current as is provided
by the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the
Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS541-Q1 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS541-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to
exceed 50 pF.
The SN74HCS541-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
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CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS541-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS541-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit, however it will ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS541-Q1 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
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9.2.3 Application Curve
5
0 ꢀ
22 ꢀ
50 ꢀ
4
3.3
2
1
0
-1
-2
0
15
30
45
Time (ns)
60
75
90 100
图9-2. Simulated signal integrity at the reciever with different damping resistor (Rd) values
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
VCC
GND
F
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1
1OE
VCC
1
20
19
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
2
3
4
5
6
7
8
9
2OE
18
17
16
15
14
13
1Y1
2A4
1Y2
2A3
1Y3
2A2
Unused input
tied to GND
Unused output
left floating
GND
12
11
1Y4
10
Avoid 90°
corners for
signal lines
GND
2A1
图11-1. Example layout for the SN74HCS541-Q1 in the WRKS Package
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
• Texas Instruments, HCMOS Design Considerations application report (SCLA007)
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
• Texas Instruments, Designing With Logic application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74HCS541QPWRQ1
ACTIVE
ACTIVE
TSSOP
VQFN
PW
20
20
2000 RoHS & Green
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
HCS541Q
HCS541Q
Samples
Samples
SN74HCS541QWRKSRQ1
RKS
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2022
OTHER QUALIFIED VERSIONS OF SN74HCS541-Q1 :
Catalog : SN74HCS541
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS541QPWRQ1 TSSOP
SN74HCS541QWRKSRQ1 VQFN
PW
20
20
2000
3000
330.0
180.0
16.4
12.4
6.95
2.8
7.0
4.8
1.4
1.2
8.0
4.0
16.0
12.0
Q1
Q1
RKS
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
3-Jun-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCS541QPWRQ1
TSSOP
VQFN
PW
20
20
2000
3000
356.0
210.0
356.0
185.0
35.0
35.0
SN74HCS541QWRKSRQ1
RKS
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RKS 20
2.5 x 4.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226872/A
www.ti.com
PACKAGE OUTLINE
RKS0020B
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
4.6
4.4
(0.1) MIN
(0.13)
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.05
0.95
2X 0.5
(0.2) TYP
EXPOSED
THERMAL PAD
10
11
14X 0.5
9
12
A
A
2X
3.05
2.95
3.5
2
19
0.3
20X
1
20
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A B
0.45
0.35
20X
0.05
4226762/B 06/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RKS0020B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
2X (0.5)
1
20
20X (0.6)
2
19
20X (0.25)
(1.25)
(3)
SYMM
2X (3.5)
(4.3)
16X (0.5)
(R0.05) TYP
9
12
(
0.2) VIA
TYP
10
11
SYMM
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226762/B 06/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
www.ti.com
EXAMPLE STENCIL DESIGN
RKS0020B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.95)
2X (0.5)
1
20
20X (0.6)
2
19
20X (0.25)
2X (1.31)
16X (0.5)
SYMM
2X (3.5) (4.3)
(0.76)
METAL
TYP
9
12
(R0.05) TYP
10
11
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226762/B 06/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
PACKAGE OUTLINE
PW0020A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
18X 0.65
20
1
2X
5.85
6.6
6.4
NOTE 3
10
B
11
0.30
20X
4.5
4.3
NOTE 4
0.19
1.2 MAX
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220206/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
20X (1.5)
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
11
10
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220206/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0020A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
20X (1.5)
SYMM
(R0.05) TYP
20
1
20X (0.45)
SYMM
18X (0.65)
10
11
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220206/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
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