SN74HCS595QDYYRQ1 [TI]
SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State Output Registers;
| 型号： | SN74HCS595QDYYRQ1 |
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TEXAS INSTRUMENTS |
| 描述： | SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and 3-State Output Registers |
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SN74HCS595-Q1
SCLS785C – DECEMBER 2019 – REVISED MARCH 2021
SN74HCS595-Q1 Automotive 8-Bit Shift Register With Schmitt-Trigger Inputs and
3-State Output Registers
1 Features
3 Description
•
AEC-Q100 Qualified for automotive applications:
– Device temperature grade 1:
–40°C to +125°C, TA
– Device HBM ESD Classification Level 2
– Device CDM ESD Classifcation Level C6
Wide operating voltage range: 2 V to 6 V
Schmitt-trigger inputs allow for slow or noisy input
signals
Low power consumption
– Typical ICC of 100 nA
– Typical input leakage current of ±100 nA
±7.8-mA output drive at 6 V
The SN74HCS595-Q1 device contains an 8-bit, serial-
in, parallel-out shift register that feeds an 8-bit
D-type storage register. All inputs include Schmitt-
trigger architecture, eliminating any erroneous data
outputs due to slow-edged or noisy input signals. The
storage register has parallel 3-state outputs. Separate
clocks are provided for both the shift and storage
register. The shift register has a direct overriding clear
(SRCLR) input, serial (SER) input, and a serial output
(QH') for cascading. When the output-enable (OE)
input is high, the storage register outputs are in a
high-impedance state. Internal register data and serial
output (QH') are not impacted by the operation of the
OE input.
•
•
•
•
2 Applications
Device Information (1)
•
•
•
•
Output expansion
PART NUMBER
SN74HCS595PW-Q1
SN74HCS595D-Q1
PACKAGE
TSSOP (16) 5.00 mm x 4.40 mm
SOIC (16) 9.90 mm x 3.90 mm
BODY SIZE (NOM)
LED matrix control
7-segment display control
8-bit data storage
SN74HCS595BQB-Q1
SN74HCS595DYY-Q1(2)
WQFN (16) 3.60 mm x 2.60 mm
SOT-23-THN 4.20 mm × 2.00 mm
(16)
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
(2) Package is in Preview.
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Benefits of Schmitt-trigger inputs
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this document contains PRODUCTION
DATA.
SN74HCS595-Q1
SCLS785C – DECEMBER 2019 – REVISED MARCH 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
Pin Functions.................................................................... 3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings ....................................... 4
6.2 ESD Ratings .............................................................. 4
6.3 Recommended Operating Conditions ........................4
6.4 Thermal Information ...................................................5
6.5 Electrical Characteristics ............................................5
6.6 Timing Characteristics ................................................6
6.7 Switching Characteristics ...........................................6
6.8 Operating Characteristics .......................................... 7
6.9 Typical Characteristics................................................9
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................11
8.1 Functional Block Diagram......................................... 11
8.2 Feature Description...................................................11
8.3 Device Functional Modes..........................................12
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
10 Power Supply Recommendations..............................16
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 Receiving Notification of Documentation Updates..17
12.3 Support Resources................................................. 17
12.4 Trademarks.............................................................17
12.5 Electrostatic Discharge Caution..............................17
12.6 Glossary..................................................................17
13 Mechanical, Packaging, and Orderable
Information.................................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (August 2020) to Revision C (March 2021)
Page
•
•
•
Added DYY Package to Device Information Table............................................................................................. 1
Added DYY Package pinout diagram and information to Pin Configuration and Functions............................... 3
Added DYY Package to Thermal Information table............................................................................................5
Changes from Revision A (February 2020) to Revision B (August 2020)
Page
•
•
•
Updated the numbering format for tables, figures and cross-references throughout the document...................1
Added BQB package to orderable table............................................................................................................. 1
Added BQB Package to Thermal Information table............................................................................................5
Changes from Revision * (December 2019) to Revision A (February 2020)
Page
Added D package to orderable table.................................................................................................................. 1
Added D Package to Thermal Information table.................................................................................................5
•
•
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5 Pin Configuration and Functions
QB
1
VCC
16
QB
VCC
QA
1
2
3
4
5
6
16
QC
QD
QE
15
14
QC
QD
QE
QF
QG
QH
2
15 QA
SER
OE
3
4
5
6
7
SER
14
13
13
12
11
10
9
OE
PAD
QF
QG
RCLK
12
11
10
RCLK
SRCLK
SRCLK
SRCLR
QH
7
8
SRCLR
QH‘
GND
8
9
GND QH`
D, PW, or DYY Package
16-Pin SOIC, TSSOP, or SOT
Top View
BQB Package
16-Pin WQFN
Transparent Top View
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
QB
NO.
1
Output
Output
Output
Output
Output
Output
Output
—
QB output
QC output
QD output
QE output
QF output
QG output
QH output
Ground
QC
2
QD
3
QE
4
QF
5
QG
6
QH
7
GND
QH'
8
9
Output
Input
Serial output, can be used for cascading
Shift register clear, active low
Shift register clock, rising edge triggered
Output register clock, rising edge triggered
Output Enable, active low
Serial input
SRCLR
SRCLK
RCLK
OE
10
11
12
13
14
15
16
Input
Input
Input
SER
QA
Input
Output
—
QA output
VCC
Positive supply
The thermal pad can be connect to GND or left floating. Do not connect to any other signal
or supply.
Thermal Pad(1)
—
1. BQ package only.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
VCC
IIK
Supply voltage
–0.5
Input clamp current(2)
VI < –0.5 V or VI > VCC + 0.5 V
VI < –0.5 V or VI > VCC + 0.5 V
VO = 0 to VCC
±20
±20
±35
±70
150
150
mA
mA
mA
mA
°C
IOK
IO
Output clamp current(2)
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
Storage temperature
TJ
Tstg
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2
±4000
V(ESD)
Electrostatic discharge
V
Charged device model (CDM), per AEC
Q100-011 CDM ESD Classification Level C6
±1500
(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
Input voltage
5
0
VCC
VCC
125
V
VO
TA
Output voltage
Ambient temperature
0
V
–40
°C
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6.4 Thermal Information
SN74HCS595-Q1
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
D (SOIC)
BQB (WQFN)
16 PINS
DYY (SOT)
16 PINS
UNIT
16 PINS
Junction-to-ambient thermal
resistance
RθJA
141.2
78.8
85.8
27.7
85.5
N/A
122.2
108.4
77.3
74.4
12.6
74.5
54.3
186.2
109.1
111.0
18.0
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Junction-to-case (top) thermal
resistance
RθJC(top)
80.9
80.6
40.4
80.3
N/A
Junction-to-board thermal
resistance
RθJB
Junction-to-top characterization
parameter
ΨJT
Junction-to-board characterization
parameter
ΨJB
110.9
N/A
Junction-to-case (bottom) thermal
resistance
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
1.7
2.1
0.3
0.9
1.2
0.2
0.4
0.6
TYP
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
V
V
V
V
V
2 V
VT-
Negative switching threshold
Hysteresis (VT+ - VT-)(1)
4.5 V
6 V
2 V
ΔVT
VOH
VOL
4.5 V
6 V
IOH = -20 µA
VI = VIH or VIL IOH = -6 mA
IOH = -7.8 mA
2 V to 6 V
4.5 V
6 V
VCC – 0.1 VCC – 0.002
High-level output voltage
4.0
5.4
4.3
5.75
0.002
0.18
0.22
±0.1
IOL = 20 µA
2 V to 6 V
4.5 V
6 V
0.1
0.30
0.33
Low-level output voltage
Input leakage current
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
II
VI = VCC or 0
6 V
±1 µA
±5 µA
Off-state (high-impedance
state) output current
IOZ
VO = VCC or 0
6 V
±0.5
0.1
ICC
Ci
Supply current
VI = VCC or 0, IO = 0
6 V
2
5
µA
pF
Input capacitance
2 V to 6 V
(1) Guaranteed by design.
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6.6 Timing Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
VCC
25°C
MIN
–40°C to 125°C
UNIT
MAX
MIN
9
MAX
2 V
7
7
7
8
7
7
8
4
3
11
5
4
8
4
4
8
4
4
0
0
0
SRCLK or RCLK
high or low
4.5 V
6 V
7
7
tw
Pulse duration
ns
2 V
10
7
SRCLR low
4.5 V
6 V
7
2 V
13
5
SER before
SRCLK↑
4.5 V
6 V
4
2 V
18
7
SRCLK↑ before
RCLK↑
4.5 V
6 V
6
tsu
Setup time
ns
2 V
13
6
SRCLR low before
RCLK↑
4.5 V
6 V
5
2 V
13
6
SRCLR high
(inactive) before
SRCLK↑
4.5 V
6 V
5
2 V
0
th
Hold time
SER after SRCLK↑ 4.5 V
6 V
0
ns
0
6.7 Switching Characteristics
CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
TYP
–40°C to 125°C
MIN TYP MAX
UNIT
MIN
35
MAX
2 V
19
60
75
fmax
Max switching frequency
4.5 V
6 V
110
130
MHz
2 V
14
6
19
8
28
10
9
SRCLK
RCLK
SRCLR
OE
QH'
4.5 V
6 V
5
7
tpd
Propagation delay
ns
2 V
16
6
21
9
37
12
10
27
11
10
27
13
11
QA - QH
4.5 V
6 V
6
8
2 V
13
6
19
8
tPHL
Propagation delay
Enable time
QH'
4.5 V
6 V
ns
ns
6
8
2 V
12
6
18
9
ten
QA - QH
4.5 V
6 V
5
8
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CL = 50 pF; over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
Operating free-air temperature (TA)
PARAMETER
FROM
TO
VCC
25°C
TYP
–40°C to 125°C
MIN TYP MAX
UNIT
MIN
MAX
16
11
10
9
2 V
13
9
20
13
12
16
9
tdis
Disable time
OE
QA - QH
4.5 V
6 V
ns
8
2 V
tt
Transition-time
Any output 4.5 V
6 V
5
ns
4
8
6.8 Operating Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted).
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX UNIT
Power dissipation capacitance
per gate
Cpd
No load
2 V to 6 V
40
pF
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SRCLK
SER
RCLK
SRCLR
OE
Q
A
Q
B
Q
C
Q
D
Q
E
Q
F
Q
G
Q
H
Q
H’
NOTE:
implies that the output is in 3-State mode.
Figure 6-1. Timing Diagram
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6.9 Typical Characteristics
TA = 25°C
46
44
42
40
38
36
34
32
30
28
26
70
65
60
55
50
45
40
35
30
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Source Current (mA)
Figure 6-2. Output driver resistance in LOW state. Figure 6-3. Output driver resistance in HIGH state.
0.2
0.18
0.16
0.14
0.12
0.1
0.65
0.6
VCC = 2 V
VCC = 4.5 V
VCC = 5 V
VCC = 6 V
0.55
0.5
VCC = 2.5 V
VCC = 3.3 V
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
VI œ Input Voltage (V)
Figure 6-4. Supply current across input voltage, 2-,
2.5-, and 3.3-V supply
Figure 6-5. Supply current across input voltage,
4.5-, 5-, and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
Test
Point
Test
Point
S1
S2
RL
From Output
Under Test
From Output
Under Test
(1)
(1)
CL
CL
(1) CL includes probe and test-fixture capacitance.
(1) CL includes probe and test-fixture capacitance.
Figure 7-2. Load Circuit for Push-Pull Outputs
Figure 7-1. Load Circuit for 3-State Outputs
tw
VCC
Clock
Input
VCC
50%
Input
50%
50%
0 V
0 V
tsu
th
Figure 7-3. Voltage Waveforms, Pulse Duration
VCC
Data
Input
50%
50%
0 V
Figure 7-4. Voltage Waveforms, Setup and Hold
Times
VCC
VCC
Output
Control
Input
Output
Output
50%
50%
50%
50%
0 V
VOH
VOL
VOH
VOL
0 V
(1)
(1)
(3)
(4)
tPLH
tPHL
tPZL
tPLZ
≈ VCC
Output
Waveform 1
(1)
S1 at VLOAD
50%
50%
50%
10%
VOL
(1)
(1)
(3)
(4)
tPHL
tPLH
tPZH
tPHZ
VOH
Output
Waveform 2
S1 at GND(2)
90%
50%
50%
50%
≈ 0 V
(1) The greater between tPLH and tPHL is the same as tpd
.
Figure 7-6. Voltage Waveforms Propagation Delays
Figure 7-5. Voltage Waveforms Propagation Delays
VCC
90%
Input
90%
10%
0 V
10%
tr(1)
tf(1)
VOH
90%
90%
Output
10%
10%
VOL
tr(1)
tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 7-7. Voltage Waveforms, Input and Output Transition Times
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8 Detailed Description
8.1 Functional Block Diagram
13
OE
RCLK
12
10
11
14
SRCLR
SRCLK
SER
D
R
Q
Q
D
D
15
QA
Q
D
R
1
Q
QB
2
QC
3
QD
4
QE
5
QF
6
QG
D
R
Q
D
7
Q
QH
9
QH‘
Figure 8-1. Logic Diagram (Positive Logic) for the SN74HCS595-Q1
8.2 Feature Description
8.2.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-State outputs. The three states that these outputs can be in are driving
high, driving low, and high impedance. The term "balanced" indicates that the device can sink and source similar
currents. The drive capability of this device may create fast edges into light loads so routing and load conditions
should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving larger
currents than the device can sustain without being damaged. It is important for the output power of the device
to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected
to the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor
can be connected to the output to provide a known voltage at the output while it is in the high-impedance state.
The value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10 kΩ resistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.2.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term "balanced" indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
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of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.2.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.2.4 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Electrical
Placement of Clamping Diodes for Each Input and Output.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
+IIK
+IOK
Input
Output
Logic
GND
-IIK
-IOK
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.3 Device Functional Modes
Function Table lists the functional modes of the SN74HCS595-Q1.
Table 8-1. Function Table
INPUTS
FUNCTION
SER
X
SRCLK
SRCLR
RCLK
OE
H
X
X
X
↑
X
X
L
X
X
X
X
Outputs QA – QH are disabled
Outputs QA – QH are enabled.
Shift register is cleared.
X
L
X
X
L
H
X
First stage of the shift register goes low. Other stages store the data
of previous stage, respectively.
H
↑
H
X
X
First stage of the shift register goes high. Other stages store the data
of previous stage, respectively.
X
X
X
↑
H
H
↑
↑
X
X
Shift-register data is stored in the storage register.
Data in shift register is stored in the storage register, the data is then
shifted through.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74HCS595-Q1 is used to control seven-segment displays. Utilizing the serial output
and combining a few of the input signals, this implementation reduces the number of I/O pins required to
control the displays from sixteen to four. Unlike other I/O expanders, the SN74HCS595-Q1 does not need a
communication interface for control. It can be easily operated with simple GPIO pins.
The OE pin is used to easily disable the outputs when the displays need to be turned off or connected to a
PWM signal to control brightness. However, this pin can be tied low and the outputs of the SN74HCS595-Q1
can be controlled accordingly to turn off all the outputs reducing the I/O needed to three. There is no practical
limitation to how many SN74HCS595-Q1 devices can be cascaded. To add more, the serial output will need to
be connected to the following serial input and the clocks will need to be connected accordingly. With separate
control for the shift registers and output registers, the desired digit can be displayed while the data for the next
digit is loaded into the shift register.
At power-up, the initial state of the shift registers and output registers are unknown. To give them a defined state,
the shift register needs to be cleared and then clocked into the output register. An RC can be connected to the
SRCLR pin as shown in the Typical application block diagram to initialize the shift register to all zeros. With the
OE pin pulled up with a resistor, this process can be performed while the outputs are in a high impedance state
eliminating any erroneous data causing issues with the displays.
9.2 Typical Application
VCC
VCC
Seven Segment
R1
C1
QA
QB
QC
QD
QE
QF
QG
QH
g
a
SRCLR
f
f
b
c
a
SER
b
DP
c
g
SRCLK
RCLK
MCU
e
d
e
d
DP
OE
GND
QH‘
VCC
VCC
Seven Segment
R2
C2
QA
QB
QC
QD
QE
QF
QG
QH
g
a
SRCLR
f
f
b
c
a
SER
b
DP
c
g
SRCLK
RCLK
e
d
e
d
DP
OE
GND
QH‘
Figure 9-1. Typical application block diagram
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9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCS595-Q1 plus the maximum static supply current, ICC, listed in Electrical Characteristics
and any transient current required for switching. The logic device can only source as much current as is provided
by the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the
Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCS595-Q1 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCS595-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting
all of the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to
exceed 50 pF.
The SN74HCS595-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross Vt-(min) to be considered a logic LOW, and Vt+(max) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into the
SN74HCS595-Q1, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCS595-Q1 has no input signal transition rate requirements because it has Schmitt-trigger inputs.
Another benefit to having Schmitt-trigger inputs is the ability to reject noise. Noise with a large enough amplitude
can still cause issues. To know how much noise is too much, please refer to the ΔVT(min) in the Electrical
Characteristics. This hysteresis value will provide the peak-to-peak limit.
Unlike what happens with standard CMOS inputs, Schmitt-trigger inputs can be held at any valid value without
causing huge increases in power consumption. The typical additional current caused by holding an input at a
value other than VCC or ground is plotted in the Typical Characteristics.
Refer to the Feature Description section for additional information regarding the inputs for this device.
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9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCS595-Q1 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
SER
QA
QB
QC
QD
QE
QF
QG
SER
QA
QB
QC
QD
QE
QF
QG
QH
QH
QH‘
QH‘
SRCLK rising edge shifts data
in the serial registers only
RCLK rising edge shifts data
to the output registers
Figure 9-2. Simplified functional diagram showing clock operation
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GNDflood fill for
improvedsignal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placedclose to
Unused inputs tieto GNDor VCC
thedevice
0.1 ꢀF
QB
QC
16
15
14
13
12
11
10
9
VCC
1
2
3
4
5
6
7
8
QA
QD
SER
OE
QE
QF
RCLK
SRCLK
SRCLR
QH‘
QG
QH
Avoid 90°
corners for
signal lines
GND
Unused output
left floating
Figure 11-1. Example layout for the SN74HCS595-Q1.
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report (SCLA007)
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report (SDYA009)
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
3000
3000
(1)
(2)
(3)
(4/5)
(6)
PSN74HCS595QBQBRQ1
PSN74HCS595QDYYRQ1
ACTIVE
WQFN
BQB
16
16
Non-RoHS &
Non-Green
Call TI
Call TI
Call TI
-40 to 125
-40 to 125
ACTIVE SOT-23-THN
DYY
Non-RoHS &
Non-Green
Call TI
SN74HCS595QBQBRQ1
SN74HCS595QDRQ1
SN74HCS595QDYYRQ1
ACTIVE
ACTIVE
WQFN
SOIC
BQB
D
16
16
16
3000 RoHS & Green
NIPDAU
NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Call TI
-40 to 125
-40 to 125
-40 to 125
CS595Q
2500 RoHS & Green
HCS595Q
PREVIEW SOT-23-THN
ACTIVE TSSOP
DYY
3000
Non-RoHS &
Non-Green
SN74HCS595QPWRQ1
PW
16
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
HCS595Q
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Mar-2021
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74HCS595-Q1 :
Catalog : SN74HCS595
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCS595QBQBRQ1 WQFN
SN74HCS595QDRQ1 SOIC
SN74HCS595QPWRQ1 TSSOP
BQB
D
16
16
16
3000
2500
2000
180.0
330.0
330.0
12.4
16.4
12.4
2.8
6.5
6.9
3.8
10.3
5.6
1.2
2.1
1.6
4.0
8.0
8.0
12.0
16.0
12.0
Q1
Q1
Q1
PW
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
10-Mar-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCS595QBQBRQ1
SN74HCS595QDRQ1
SN74HCS595QPWRQ1
WQFN
SOIC
BQB
D
16
16
16
3000
2500
2000
210.0
853.0
853.0
185.0
449.0
449.0
35.0
35.0
35.0
TSSOP
PW
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
www.ti.com
EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
C
3.36
3.16
SEATING PLANE
PIN 1 INDEX
AREA
A
0.1 C
14X 0.5
16
1
4.3
4.1
NOTE 3
2X
3.5
8
9
0.31
16X
0.11
0.1
C A
B
1.1 MAX
2.1
1.9
B
0.2
0.08
TYP
SEE DETAIL A
0.25
GAUGE PLANE
0°- 8°
0.1
0.0
0.63
0.33
DETAIL A
TYP
4224642/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed
0.15 per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.50 per side.
www.ti.com
EXAMPLE BOARD LAYOUT
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
SOLDER MASK
OPENING
NON- SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4224642/A 11/2018
NOTES: (continued)
5. Publication IPC-7351 may have alternate designs.
6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
SOT-23-THIN - 1.1 mm max height
PLASTIC SMALL OUTLINE
DYY0016A
16X (1.05)
SYMM
16
1
16X (0.3)
SYMM
14X (0.5)
9
8
(R0.05) TYP
(3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 20X
4224642/A 11/2018
NOTES: (continued)
7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.
www.ti.com
GENERIC PACKAGE VIEW
BQB 16
2.5 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226161/A
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
PLASTIC QUAD FLAT PACK-NO LEAD
BQB0016A
A
2.6
2.4
B
3.6
3.4
PIN 1 INDEX AREA
C
0.8
0.7
SEATING PLANE
0.08 C
1.1
0.9
0.05
0.00
(0.2) TYP
2X 0.5
8
9
10X 0.5
7
10
SYMM
2X
2.5
2.1
1.9
15
2
0.30
0.18
16X
0.5
0.3
16
1
PIN 1 ID
(OPTIONAL)
SYMM
16X
0.1
C A B
0.05
C
4224640/A 11/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
BQB0016A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(1)
2X (0.5)
1
16
10X (0.5)
2
15
SYMM
2X
(2.5)
(2)
(3.3)
2X
(0.75)
10
7
16X (0.24)
16X (0.6)
(Ø0.2) VIA
TYP
9
8
SYMM
(R0.05) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
0.07 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
0.07 MIN
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
SOLDER MASK
OPENING
EXPOSED METAL
NON-SOLDER MASK
SOLDER MASK
DEFINED
DEFINED
(PREFERRED)
4224640/A 11/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
BQB0016A
PLASTIC QUAD FLAT PACK-NO LEAD
(2.3)
(0.95)
2X (0.5)
1
16
10X (0.5)
2
15
SYMM
2X
(2.5)
(1.79) (3.3)
10
7
16X (0.24)
16X (0.6)
EXPOSED METAL
9
8
SYMM
(R0.05) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4224640/A 11/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
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