SN74HCS72 [TI]
具有清零和预置端的施密特触发输入双路负边沿触发式 D 型触发器;
| 型号： | SN74HCS72 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有清零和预置端的施密特触发输入双路负边沿触发式 D 型触发器 触发器 |
| 文件： | 总22页 (文件大小：699K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SN74HCS72
ZHCSKT3 –FEBRUARY 2020
具有清零和预设功能且通过汽车认证的 SN74HCS72 施密特触发输入双路
D 型
负缘触发触发器
1 特性
3 说明
1
•
•
•
宽工作电压范围：2V 至 6V
该器件包含两个独立的 D 型负缘触发触发器。所有输
入均包括施密特触发，可实现慢速或高噪声输入信号。
将预设 (PRE) 输入设为低电平，会输出高电平。将清
零 (CLR) 输入设为低电平，会重新输出低电平。预设
和清零功能是异步的，并且不依赖于其他输入的电平。
当 PRE 和 CLR 处于非活动状态（高电平）时，数据
(D) 输入处满足设置时间要求的数据将传输到时钟
(CLK) 脉冲负向缘上的输出（Q，Q）处。经过保持时
间间隔后，可以更改数据 (D) 输入处的数据而不影响输
出（Q，Q）处的电平。
施密特触发输入可实现慢速或高噪声输入信号
低功耗
–
–
I
CC 典型值为 100nA
输入泄漏电流典型值为 ±100nA
•
•
电压为 5V 时，输出驱动为 ±7.8mA
工作环境温度范围：–40°C 至 +125°C，TA
2 应用
•
•
•
•
将瞬时开关转换为拨动开关
输入慢速边沿速率信号
器件信息(1)
可在高噪声环境中运行
器件型号
封装
封装尺寸（标称值）
启用具有唤醒模式的 CAN 控制器电源
SN74HCS72PWR
TSSOP (14) 5.00mm x 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
施密特触发输入的优势
Supports Slow Inputs
Low Power
Noise Rejection
Input Voltage
Waveforms
Time
Input Voltage
Time
Standard
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
Schmitt-trigger
CMOS Input
Response
Waveforms
Time
Time
Input Voltage
1
本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。 有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确
性和有效性。 在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS801
SN74HCS72
ZHCSKT3 –FEBRUARY 2020
www.ti.com.cn
目录
8.3 Feature Description................................................... 9
8.4 Device Functional Modes........................................ 10
Application and Implementation ........................ 11
9.1 Application Information .......................................... 11
9.2 Typical Application ................................................. 11
1
2
3
4
5
6
特性.......................................................................... 1
应用.......................................................................... 1
说明.......................................................................... 1
修订历史记录 ........................................................... 2
Pin Configuration and Functions......................... 3
Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Switching Characteristics.......................................... 5
6.7 Timing Characteristics............................................... 6
6.8 Typical Characteristics.............................................. 7
Parameter Measurement Information .................. 8
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
9
10 Power Supply Recommendations ..................... 13
11 Layout................................................................... 13
11.1 Layout Guidelines ................................................. 13
11.2 Layout Example .................................................... 13
12 器件和文档支持 ..................................................... 14
12.1 文档支持................................................................ 14
12.2 接收文档更新通知 ................................................. 14
12.3 社区资源................................................................ 14
12.4 商标....................................................................... 14
12.5 静电放电警告......................................................... 14
12.6 Glossary................................................................ 14
13 机械、封装和可订购信息....................................... 14
7
8
4 修订历史记录
注：之前版本的页码可能与当前版本有所不同。
日期
修订版本
说明
2020 年 2 月
*
初始发行版。
2
Copyright © 2020, Texas Instruments Incorporated
SN74HCS72
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ZHCSKT3 –FEBRUARY 2020
5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
1
2
3
4
5
6
7
14
VCC
1CLR
1D
2CLR
13
12
11
10
9
1CLK
1PRE
2D
2CLK
1Q
1Q
2PRE
2Q
GND
2Q
8
Pin Functions
PIN
TYPE
DESCRIPTION
NAME
1CLR
1D
NO.
1
Input
Input
Input
Input
Output
Output
—
Clear for channel 1, active low
Data for channel 1
2
1CLK
1PRE
1Q
3
Clock for channel 1, falling edge triggered
Preset for channel 1, active low
Output for channel 1
4
5
1Q
6
Inverted output for channel 1
Ground
GND
2Q
7
8
Output
Output
Input
Input
Input
Input
—
Inverted output for channel 2
Output for channel 2
2Q
9
2PRE
2CLK
2D
10
11
12
13
14
Preset for channel 2, active low
Clock for channel 2, falling edge triggered
Data for channel 2
2CLR
VCC
Clear for channel 2, active low
Positive supply
Copyright © 2020, Texas Instruments Incorporated
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ZHCSKT3 –FEBRUARY 2020
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
7
UNIT
V
VCC
IIK
Supply voltage
Input clamp current(2)
–0.5
VI < 0 or VI > VCC + 0.5 V
±20
mA
VO < 0 or VO > VCC + 0.5
V
IOK
IO
Output clamp current(2)
±20
mA
Continuous output current
Continuous current through VCC or GND
Junction temperature(3)
VO = 0 to VCC
±25
±50
150
150
mA
mA
°C
Tj
Tstg
Storage temperature
–65
°C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) Guaranteed by design
6.2 ESD Ratings
VALUE
UNIT
Human-body model (HBM), per
ANSI/ESDA/JEDEC JS-001(1)
±4000
V(ESD)
Electrostatic discharge
V
Charged-device model (CDM), per JEDEC
specification JESD22-C101(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2
NOM
MAX
6
UNIT
V
VCC
VI
Supply voltage
5
Input voltage
0
VCC
V
VO
Output voltage
0
VCC
V
Δt/Δv
TA
Input transition rise and fall rate
Ambient temperature
Unlimited
125
ns/V
°C
–40
6.4 Thermal Information
SN74HCS72
THERMAL METRIC
PW (TSSOP)
14 PINS
151.7
79.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
94.7
ΨJT
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
25.2
ΨJB
94.1
RθJC(bot)
N/A
4
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ZHCSKT3 –FEBRUARY 2020
6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
0.7
TYP
MAX UNIT
2 V
1.5
VT+
Positive switching threshold
4.5 V
6 V
1.7
3.15
4.2
1.0
2.2
3.0
1.0
1.4
1.6
V
V
V
V
V
2.1
2 V
0.3
VT-
Negative switching threshold
4.5 V
6 V
0.9
1.2
2 V
0.2
(1)
ΔVT Hysteresis (VT+ - VT-
)
4.5 V
6 V
0.4
0.6
IOH = -20 µA
VI = VIH or VIL IOH = -6 mA
IOH = -7.8 mA
2 V to 6 V
4.5 V
6 V
VCC – 0.1
4
VCC – 0.002
4.3
VOH High-level output voltage
5.4
5.75
IOL = 20 µA
2 V to 6 V
4.5 V
6 V
0.002
0.18
0.1
0.30
0.33
VOL
Low-level output voltage
VI = VIH or VIL IOL = 6 mA
IOL = 7.8 mA
0.22
II
Input leakage current
Supply current
VI = VCC or 0
6 V
±100
0.1
±1000 nA
ICC
Ci
VI = VCC or 0, IO = 0
6 V
2
5
µA
pF
Input capacitance
2 V to 6 V
Power dissipation capacitance
per gate
Cpd
No load
2 V to 6 V
10
pF
(1) Guaranteed by design.
6.6 Switching Characteristics
CL = 50 pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See
Parameter Measurement Information
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
2 V
MIN
20
TYP
31
95
105
19
8
MAX UNIT
fmax
tpd
tt
Max switching frequency
4.5 V
6 V
64
MHz
74
2 V
42
PRE or CLR
CLK
Q or Q
4.5 V
6 V
19
15
42
19
15
16
9
ns
ns
ns
7
Propagation delay
Transition-time(1)
2 V
19
8
Q or Q
Q or Q
4.5 V
6 V
7
2 V
9
4.5 V
6 V
5
4
8
(1) tt = tr or tf, whichever is larger
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6.7 Timing Characteristics
CL = 50 pF; over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See
Parameter Measurement Information.
PARAMETER
VCC
2 V
MIN
TYP
MAX
20
UNIT
fclock
Clock frequency
Pulse duration
4.5 V
6 V
64
MHz
74
2 V
8
7
7
5
PRE or CLR low
CLK high or low
Data
4.5 V
6 V
ns
ns
ns
ns
ns
7
5
tw
2 V
10
9
5
4.5 V
6 V
3
8
2
2 V
16
6
11
1
4.5 V
6 V
3
1
tsu
Setup time before CLK low
2 V
7
PRE or CLR inactive
Data after CLK ↓
4.5 V
6 V
0
0
2 V
5
th
Hold time
4.5 V
6 V
3
2
6
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6.8 Typical Characteristics
TA = 25°C
46
70
65
60
55
50
45
40
35
30
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
VCC = 2 V
VCC = 3.3 V
VCC = 4.5 V
VCC = 6 V
44
42
40
38
36
34
32
30
28
26
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Sink Current (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
Output Source Current (mA)
图 1. Output driver resistance in LOW state.
图 2. Output driver resistance in HIGH state.
0.2
0.65
VCC = 2 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 4.5 V
0.6
0.18
0.16
0.55
VCC = 5 V
0.5
VCC = 6 V
0.14
0.12
0.1
0.45
0.4
0.35
0.3
0.08
0.06
0.04
0.02
0
0.25
0.2
0.15
0.1
0.05
0
0
0.5
1
1.5
2
2.5
3
3.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
VI œ Input Voltage (V)
VI œ Input Voltage (V)
图 3. Supply current across input voltage, 2-, 2.5-,
图 4. Supply current across input voltage, 4.5-, 5-,
and 3.3-V supply
and 6-V supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
tw
Test
Point
VCC
VCC
0 V
Input
50%
50%
S1
S2
RL
From Output
Under Test
图 6. Voltage Waveforms, Pulse Duration
(1)
CL
CL includes probe and test-fixture capacitance.
图 5. Load Circuit
VCC
0 V
VCC
0 V
VCC
0 V
VOH
VOL
VOH
VOL
Clock
Input
50%
Input
50%
50%
(1)
(1)
tPLH
tPHL
tsu
th
Data
Input
50%
50%
Output
50%
50%
(1)
(1)
图 7. Voltage Waveforms, Setup and Hold Times
tPHL
tPLH
Output
50%
50%
Voltage Waveforms, Propagation Delay specifications tPLH and tPHL
are the same as tpd
.
图 8. Voltage Waveforms Propagation Delays
VCC
90%
Input
90%
10%
10%
tf
0 V
VOH
tr
90%
10%
90%
Output
10%
tf
VOL
tr
图 9. Voltage Waveforms, Input and Output Transition Times
8
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SN74HCS72
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ZHCSKT3 –FEBRUARY 2020
8 Detailed Description
8.1 Overview
图 10 describes the SN74HCS72. As the SN74HCS72 is a dual D-Type negative-edge-triggered flip-flop with
clear and preset, the diagram below describes one of the two device flip-flops.
8.2 Functional Block Diagram
CLK
PRE
C
C
C
C
Q
C
C
C
C
D
C
C
Q
CLR
图 10. Logic Diagram (Positive Logic) for one channel of SN74HCS72
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
A balanced output allows the device to sink and source similar currents. The drive capability of this device may
create fast edges into light loads so routing and load conditions should be considered to prevent ringing.
Additionally, the outputs of this device are capable of driving larger currents than the device can sustain without
being damaged. It is important for the output power of the device to be limited to avoid damage due to over-
current. The electrical and thermal limits defined the in the Absolute Maximum Ratings must be followed at all
times.
8.3.2 CMOS Schmitt-Trigger Inputs
Standard CMOS inputs are high impedance and are typically modeled as a resistor in parallel with the input
capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the maximum
input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the
Electrical Characteristics, using ohm's law (R = V ÷ I).
The Schmitt-trigger input architecture provides hysteresis as defined by ΔVT in the Electrical Characteristics,
which makes this device extremely tolerant to slow or noisy inputs. While the inputs can be driven much slower
than standard CMOS inputs, it is still recommended to properly terminate unused inputs. Driving the inputs slowly
will also increase dynamic current consumption of the device. For additional information regarding Schmitt-trigger
inputs, please see Understanding Schmitt Triggers.
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Feature Description (接下页)
8.3.3 Positive and Negative Clamping Diodes
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in 图 11.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can
cause damage to the device. The input negative-voltage and output voltage ratings
may be exceeded if the input and output clamp-current ratings are observed.
VCC
Device
+IIK
+IOK
Input
Output
Logic
GND
-IIK
-IOK
图 11. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
表 1 lists the functional modes of the SN74HCS72.
表 1. Function Table
INPUTS
OUTPUTS
PRE
L
CLR
H
CLK
X
D
X
X
X
H
L
Q
H
Q
L
H
L
X
L
H(1)
H
H(1)
L
L
X
H
H
↓
H
L
H
H
↓
L
H
H
H
L
X
X
Q0
Q0
Q0
Q0
H
H
H
(1) This configuration is nonstable; that is, it does not persist when PRE or CLR returns to its inactive
(high) level.
10
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9 Application and Implementation
注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
The SN74HCS72 is an ideal device for taking a CAN wake-up request and converting it to a power supply enable
due to its low power consumption and noise rejecting inputs, which eliminate false triggers. CAN communication
can occur when the vehicle ignition is off. Therefore, many circuits are designed to work in a standby or low
power mode. Because a CAN wake-up request causes the RX pin to pulse LOW, the SN74HCS72 will trigger off
the falling edge enabling the power for the CAN controller. Then the CAN controller powers on for the incoming
communication. When communications are finished, the controller sends a reset pulse to the SN74HCS72 and
CAN transceiver putting the circuit back into a standby mode.
9.2 Typical Application
VCC
CAN Controller
Power
EN
VCC
RX
VCC
PRE
CLK
CLR
D
Q
R1
C1
RX
nSTB
TX
Q
CAN Controller
GND
R2
I/O
TX
图 12. Power Enable Using CAN Wake-up Request
9.2.1 Design Requirements
The SN74HCS72 device allows flexibility by having complementary outputs for active-high or active-low enables.
The supply should be selected such that the device is always powered along with the CAN transceiver. The
same supply for both devices is recommended.
With the SN74HCS72, a power on reset circuit only requires a resistor (R) and capacitor (C) to create a delay.
The R and C values create a delay that is approximately 2.2×RC. In this application, it is desired to have the
output (Q) in the HIGH state at startup, so R1 and C1 are connected directly to the CLR pin, as shown in 图 12.
A second resistor is needed to limit the current into the CAN controller when it sets the circuit back into standby
mode. It is required for the R1 resistor to be at least ten times larger than R2 to avoid a divider circuit (R2 ≤
10R1).
The D input can be tied either to VCC or ground depending on the desired implementation. In this example, it is
tied to VCC to obtain a HIGH signal from Q when a wake-up request occurs.
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Typical Application (接下页)
9.2.1.1 Output Considerations
In general, the load needs to be considered in the design to determine if the device will have the capability to
drive it. For this application, we assume that the flip-flop output is transmitting over a relatively short trace (under
10 cm) to a CMOS input.
Primary load factors to consider:
•
Load Capacitance: approximately 15 pF
–
–
–
See the Switching Characteristics section for the capacitive loads tested with this device.
Increasing capacitance will proportionally increase output transition times.
Decreasing capacitance will proportionally decrease output transition times, and can produce ringing due
to very fast transition rates. A 25-Ω resistor can be added in series with the output if ringing needs to be
dampened.
•
•
Load Current: expected maximum of 10 µA
–
–
–
Leakage current into connected devices.
Parasitic current from other components.
Resistive load current.
Output Voltage: see Electrical Characteristics for output voltage ratings at a given current.
–
Output HIGH (VOH) and output LOW (VOL) voltage levels affect the input voltage, VIH and VIL, respectively,
to subsequent devices.
9.2.1.2 Input Considerations
The SN74HCS72 has Schmitt-trigger inputs. Schmitt-trigger inputs have no limitation on transition rate, however
the input voltage must be larger than VT+(max) to be guaranteed to be read as a logic high, and below VT-(min) to be
guaranteed to be read as a logic low, as defined in the Electrical Characteristics. Do not exceed the values
specified in the Absolute Maximum Ratings or the device could be damaged.
9.2.1.3 Timing Considerations
The SN74HCS72 is a clocked device. As such, it requires special timing considerations to ensure normal
operation.
Primary timing factors to consider:
•
Maximum clock frequency: the maximum operating clock frequency defined in Timing Characteristics is the
maximum frequency at which the device is guaranteed to function. This value refers specifically to the
triggering waveform, measuring from one trigger level to the next.
•
•
•
Pulse duration: ensure that the triggering event duration is larger than the minimum pulse duration, as defined
in the Timing Characteristics.
Setup time: ensure that the data has changed at least one setup time prior to the triggering event, as defined
in the Timing Characteristics.
Hold time: ensure that the data remains in the desired state at least one hold time after the triggering event,
as defined in the Timing Characteristics.
9.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
–
Input signals to Schmitt-trigger inputs, like those found on the HCS family of devices, can support
unlimited edge rates.
–
–
Input thresholds are listed in the Electrical Characteristics.
Inputs include positive clamp diodes. Input voltages can exceed the device's supply so long as the clamp
current ratings are observed from the Absolute Maximum Ratings. Do not exceed the absolute maximum
voltage rating of the device or it could be damaged.
2. Recommended Output Conditions:
–
–
Load currents should not exceed the value listed in the Absolute Maximum Ratings.
Series resistors on the output may be used if the user desires to slow the output edge signal or limit the
12
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Typical Application (接下页)
output current.
9.2.3 Application Curve
*Wake-up Pattern
RX
Q
I/O
图 13. Application timing diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings table. Each VCC terminal should have a bypass capacitor to prevent power
disturbance. For this device, a 0.1-μF capacitor is recommended. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminals as possible for best results.
11 Layout
11.1 Layout Guidelines
In many cases, functions or parts of functions of digital logic devices are unused. Some examples are when only
two inputs of a triple-input AND gate are used, or when only 3 of the 4 channels are used. Such input pins should
not be left completely unconnected because the unknown voltages result in undefined operational states.
Specified in 图 14 are rules that must be observed under all circumstances. All unused inputs of digital logic
devices must be connected to a high or low bias to prevent them from floating. The logic level that must be
applied to any particular unused input depends on the function of the device. Generally they are tied to GND or
VCC, whichever makes more sense or is more convenient. It is recommended to float outputs unless the part is a
transceiver. If the transceiver has an output enable pin, it disables the output section of the part when asserted.
This pin keeps the input section of the I/Os from being disabled and floated.
11.2 Layout Example
GND VCC
Recommend GNDflood fill for
improvedsignal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placedclose to
thedevice
0.1 ꢀF
Unused inputs
tied to VCC
1CLR
1D
14
1
2
3
4
5
6
7
VCC
13
12
11
10
9
2CLR
2D
1CLK
1PRE
1Q
2CLK
2PRE
2Q
1Q
Avoid 90°
corners for
signal lines
Unused output
left floating
GND
8
2Q
图 14. Layout Example
版权 © 2020, Texas Instruments Incorporated
13
SN74HCS72
ZHCSKT3 –FEBRUARY 2020
www.ti.com.cn
12 器件和文档支持
12.1 文档支持
12.1.1 相关文档
请参阅如下相关文档：
•
•
•
德州仪器 (TI)，《慢速或浮点 CMOS 输入的影响》应用报告
德州仪器 (TI)，《使用全新 HCS 逻辑系列降低噪声并节省电力》 应用报告
德州仪器 (TI)，《了解施密特触发》 应用报告
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com.cn 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 社区资源
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 商标
E2E is a trademark of Texas Instruments.
12.5 静电放电警告
这些装置包含有限的内置 ESD 保护。 存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损
伤。
12.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。
14
版权 © 2020, Texas Instruments Incorporated
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74HCS72DR
ACTIVE
ACTIVE
SOIC
D
14
14
2500 RoHS & Green
2000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
HCS72
HCS72
SN74HCS72PWR
TSSOP
PW
NIPDAU | SN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Dec-2020
Addendum-Page 2
重要声明和免责声明
TI 均以“原样”提供技术性及可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资
源，不保证其中不含任何瑕疵，且不做任何明示或暗示的担保，包括但不限于对适销性、适合某特定用途或不侵犯任何第三方知识产权的暗示
担保。
所述资源可供专业开发人员应用TI 产品进行设计使用。您将对以下行为独自承担全部责任：(1) 针对您的应用选择合适的TI 产品；(2) 设计、
验证并测试您的应用；(3) 确保您的应用满足相应标准以及任何其他安全、安保或其他要求。所述资源如有变更，恕不另行通知。TI 对您使用
所述资源的授权仅限于开发资源所涉及TI 产品的相关应用。除此之外不得复制或展示所述资源，也不提供其它TI或任何第三方的知识产权授权
许可。如因使用所述资源而产生任何索赔、赔偿、成本、损失及债务等，TI对此概不负责，并且您须赔偿由此对TI 及其代表造成的损害。
TI 所提供产品均受TI 的销售条款 (http://www.ti.com.cn/zh-cn/legal/termsofsale.html) 以及ti.com.cn上或随附TI产品提供的其他可适用条款的约
束。TI提供所述资源并不扩展或以其他方式更改TI 针对TI 产品所发布的可适用的担保范围或担保免责声明。IMPORTANT NOTICE
邮寄地址：上海市浦东新区世纪大道 1568 号中建大厦 32 楼，邮政编码：200122
Copyright © 2020 德州仪器半导体技术（上海）有限公司
相关型号：
UL1042
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