SN74HCT138N3 [TI]
3-LINE TO 8-LINE DECODERS DEMULTIPLEXERS; 3线路至8线路解码器多路解复用器
| 型号： | SN74HCT138N3 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-LINE TO 8-LINE DECODERS DEMULTIPLEXERS |
| 文件： | 总21页 (文件大小：1134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢈ ꢌꢍ ꢎꢁꢏ ꢆ ꢐ ꢉ ꢌꢍ ꢎꢁꢏ ꢑꢏ ꢅꢐꢑ ꢏꢒꢀꢓ ꢑꢏ ꢔꢕꢍꢆ ꢎꢖ ꢍꢏ ꢗꢏ ꢒ ꢀ
SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003
D
D
D
D
D
Operating Voltage Range of 4.5 V to 5.5 V
Outputs Can Drive Up To 10 LSTTL Loads
D
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
D
D
Low Power Consumption, 80-µA Max I
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
CC
Typical t = 17 ns
pd
4-mA Output Drive at 5 V
D
Incorporate Three Enable Inputs to Simplify
Cascading and/or Data Reception
SN54HCT138 . . . J OR W PACKAGE
SN74HCT138 . . . D, N, NS, OR PW PACKAGE
(TOP VIEW)
SN54HCT138 . . . FK PACKAGE
(TOP VIEW)
A
B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
3
2
1
20 19
18
Y0
Y1
Y2
Y1
Y2
NC
C
G2A
NC
4
5
6
7
8
C
17
16
G2A
G2B
G1
12 Y3
15 Y3
14
9 10 11 12 13
G2B
G1
11
10
9
Y4
Y5
Y6
Y4
Y7
GND
NC − No internal connection
description/ordering information
The ’HCT138 devices are designed for high-performance memory-decoding or data-routing applications
requiring very short propagation delay times. In high-performance memory systems, these decoders can
minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable
circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical
access time of the memory. This means that the effective system delay introduced by the decoders is negligible.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube of 25
Tube of 40
Reel of 2500
Reel of 250
Reel of 2000
Tube of 90
Reel of 2000
Reel of 250
Tube of 25
Tube of 150
Tube of 55
SN74HCT138N
SN74HCT138N
SN74HCT138D
SN74HCT138DR
SN74HCT138DT
SN74HCT138NSR
SN74HCT138PW
SN74HCT138PWR
SN74HCT138PWT
SNJ54HCT138J
SNJ54HCT138W
SNJ54HCT138FK
SOIC − D
SOP − NS
HCT138
HCT138
−40°C to 85°C
TSSOP − PW
HT138
CDIP − J
CFP − W
LCCC − FK
SNJ54HCT138J
SNJ54HCT138W
SNJ54HCT138FK
−55°C to 125°C
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2003, Texas Instruments Incorporated
ꢐ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢔꢎ ꢍꢌ ꢖꢒ ꢯ ꢌꢈꢉꢂ ꢈꢂꢊ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢀꢁꢋ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ
ꢈꢌ ꢍ ꢎ ꢁꢏ ꢆꢐ ꢉ ꢌꢍ ꢎ ꢁꢏ ꢑꢏ ꢅꢐ ꢑꢏ ꢒꢀ ꢓ ꢑꢏ ꢔꢕ ꢍꢆꢎ ꢖꢍ ꢏꢗꢏ ꢒꢀ
SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003
description/ordering information (continued)
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low (G) and one active-high (G) enable inputs reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
FUNCTION TABLE
INPUTS
OUTPUTS
ENABLE
SELECT
G1
X
G2A
H
X
X
L
G2B
X
H
X
L
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
L
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
H
H
L
L
H
H
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢈ ꢌꢍ ꢎꢁꢏ ꢆ ꢐ ꢉ ꢌꢍ ꢎꢁꢏ ꢑꢏ ꢅꢐꢑ ꢏꢒꢀꢓ ꢑꢏ ꢔꢕꢍꢆ ꢎꢖ ꢍꢏ ꢗꢏ ꢒ ꢀ
SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003
logic diagram (positive logic)
15
Y0
1
A
14
Y1
2
B
13
Y2
3
12
Y3
C
11
Y4
10
Y5
6
G1
9
Y6
4
G2A
7
Y7
5
G2B
Pin numbers shown are for the D, J, N, NS, PW, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢈ ꢉꢊ ꢀꢁꢋ ꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ
ꢈꢌ ꢍ ꢎ ꢁꢏ ꢆꢐ ꢉ ꢌꢍ ꢎ ꢁꢏ ꢑꢏ ꢅꢐ ꢑꢏ ꢒꢀ ꢓ ꢑꢏ ꢔꢕ ꢍꢆꢎ ꢖꢍ ꢏꢗꢏ ꢒꢀ
SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003
recommended operating conditions (see Note 3)
SN54HCT138
MIN NOM MAX
SN74HCT138
MIN NOM MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
∆t/∆v
Input transition rise/fall time
Operating free-air temperature
500
125
500
85
ns
°C
T
A
−55
−40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT138 SN74HCT138
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= −20 µA
= −4 mA
= 20 µA
= 4 mA
4.4 4.499
OH
OH
OL
OL
V
V = V or V
IH
4.5 V
4.5 V
OH
OL
I
IL
3.98
4.3
0.001
0.17
0.1
3.7
3.84
0.1
0.26
100
8
0.1
0.4
0.1
0.33
1000
80
V
V = V or V
V
I
IH
IL
I
I
V = V
I
or 0
5.5 V
5.5 V
1000
160
nA
I
CC
V = V
I
or 0,
I
O
= 0
µA
CC
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
10
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
.
CC
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
23
SN54HCT138 SN74HCT138
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
ns
CC
MIN
MAX
36
MIN
MAX
54
MIN
MAX
45
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
A, B, or C
Enable
Any Y
Any Y
Y
17
32
49
34
t
t
pd
22
33
50
42
18
30
45
38
12
15
22
19
ns
t
11
14
20
17
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
85
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢈ ꢌꢍ ꢎꢁꢏ ꢆ ꢐ ꢉ ꢌꢍ ꢎꢁꢏ ꢑꢏ ꢅꢐꢑ ꢏꢒꢀꢓ ꢑꢏ ꢔꢕꢍꢆ ꢎꢖ ꢍꢏ ꢗꢏ ꢒ ꢀ
SCLS171E − MARCH 1984 − REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
3 V
0 V
From Output
Under Test
Test
Point
Input
1.3 V
1.3 V
C
= 50 pF
L
t
t
PLH
PHL
90%
(see Note A)
V
V
OH
In-Phase
Output
90%
t
1.3 V
10%
1.3 V
10%
LOAD CIRCUIT
OL
t
r
f
f
t
t
PLH
PHL
90%
3 V
0 V
V
V
OH
2.7 V
2.7 V
Input
1.3 V
0.3 V
1.3 V
0.3 V
90%
t
Out-of-Phase
Output
1.3 V
10%
1.3 V
10%
OL
t
t
t
r
f
r
VOLTAGE WAVEFORM
INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
C includes probe and test-fixture capacitance.
L
O
r
f
C. The outputs are measured one at a time with one input transition per measurement.
D. and t are the same as t
t
.
PLH
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
85504012A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
85504012A
SNJ54HCT
138FK
8550401EA
8550401FA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
CDIP
CFP
J
W
J
16
16
16
16
1
1
1
1
TBD
TBD
TBD
TBD
TBD
A42
A42
A42
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
8550401EA
SNJ54HCT138J
8550401FA
SNJ54HCT138W
JM38510/65852BEA
M38510/65852BEA
CDIP
CDIP
JM38510/
65852BEA
J
JM38510/
65852BEA
SN54HCT138J
SN74HCT138D
ACTIVE
ACTIVE
CDIP
SOIC
J
16
16
1
A42
N / A for Pkg Type
-55 to 125
-40 to 85
SN54HCT138J
D
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HCT138
SN74HCT138DE4
SN74HCT138DG4
SN74HCT138DR
SN74HCT138DRE4
SN74HCT138DRG4
SN74HCT138DT
SN74HCT138DTE4
SN74HCT138DTG4
SN74HCT138N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
OBSOLETE
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
D
D
D
D
D
D
D
D
N
N
16
16
16
16
16
16
16
16
16
16
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
HCT138
HCT138
HCT138
HCT138
HCT138
HCT138
HCT138
HCT138
SN74HCT138N
Green (RoHS
& no Sb/Br)
2500
2500
2500
250
250
250
25
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Pb-Free
(RoHS)
SN74HCT138N3
TBD
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74HCT138NE4
SN74HCT138NSR
SN74HCT138NSRE4
SN74HCT138NSRG4
SN74HCT138PW
ACTIVE
PDIP
SO
N
16
16
16
16
16
16
16
25
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
SN74HCT138N
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
NS
NS
NS
PW
PW
PW
2000
2000
2000
90
Green (RoHS
& no Sb/Br)
HCT138
HCT138
HCT138
HT138
SO
Green (RoHS
& no Sb/Br)
SO
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
Green (RoHS
& no Sb/Br)
SN74HCT138PWE4
SN74HCT138PWG4
90
Green (RoHS
& no Sb/Br)
HT138
90
Green (RoHS
& no Sb/Br)
HT138
SN74HCT138PWLE
SN74HCT138PWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
2000
250
250
250
1
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
HT138
HT138
HT138
HT138
HT138
HT138
SN74HCT138PWRE4
SN74HCT138PWRG4
SN74HCT138PWT
SN74HCT138PWTE4
SN74HCT138PWTG4
SNJ54HCT138FK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
LCCC
PW
PW
PW
PW
PW
FK
16
16
16
16
16
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-55 to 125
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TBD
85504012A
SNJ54HCT
138FK
SNJ54HCT138J
SNJ54HCT138W
ACTIVE
CDIP
CFP
J
16
16
1
TBD
TBD
A42
N / A for Pkg Type
Call TI
-55 to 125
-55 to 125
8550401EA
SNJ54HCT138J
OBSOLETE
W
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54HCT138, SN74HCT138 :
Catalog: SN74HCT138
•
Military: SN54HCT138
•
NOTE: Qualified Version Definitions:
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
Catalog - TI's standard catalog product
•
•
Military - QML certified for Military and Defense Applications
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT138DR
SN74HCT138DRG4
SN74HCT138PWR
SN74HCT138PWT
SOIC
SOIC
D
D
16
16
16
16
2500
2500
2000
250
330.0
330.0
330.0
330.0
16.8
16.4
12.4
12.4
6.5
6.5
6.9
6.9
10.3
10.3
5.6
2.1
2.1
1.6
1.6
8.0
8.0
8.0
8.0
16.0
16.0
12.0
12.0
Q1
Q1
Q1
Q1
TSSOP
TSSOP
PW
PW
5.6
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Oct-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCT138DR
SN74HCT138DRG4
SN74HCT138PWR
SN74HCT138PWT
SOIC
SOIC
D
D
16
16
16
16
2500
2500
2000
250
364.0
333.2
367.0
367.0
364.0
345.9
367.0
367.0
27.0
28.6
35.0
35.0
TSSOP
TSSOP
PW
PW
Pack Materials-Page 2
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