SN74HCT165PWR [TI]
SN74HCT165 8-Bit Parallel-Load Shift Registers;
| 型号： | SN74HCT165PWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SN74HCT165 8-Bit Parallel-Load Shift Registers |
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| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74HCT165
SCLS881A – OCTOBER 2021 – REVISED DECEMBER 2021
SN74HCT165 8-Bit Parallel-Load Shift Registers
1 Features
3 Description
•
LSTTL input logic compatible
– VIL(max) = 0.8 V, VIH(min) = 2 V
CMOS input logic compatible
– II ≤ 1 µA at VOL, VOH
The SN74HCT165 is a parallel- or serial-in, serial-out
8-bit shift register. Parallel-in access to each stage is
provided by eight individual direct data (A-H) inputs
that are enabled by a low level at the shift/load
(SH/LD) input. The SN74HCT165 also features a
clock-inhibit (CLK INH) function and a complementary
serial (Q H) output.
•
•
•
•
•
•
4.5 V to 5.5 V operation
Supports fanout up to 10 LSTTL loads
Direct overriding load (data) inputs
Gated clock inputs
Extended ambient temperature range: –40°C to
+125°C, TA
Device Information
PART NUMBER
PACKAGE(1)
BODY SIZE (NOM)
SN74HCT165PW
TSSOP (16)
5.00 mm × 4.40 mm
2 Applications
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
•
Increase the number of inputs on a microcontroller
A
H
B
C
D
E
F
G
SH/LD
5 Additional
Shift Register
Stages
S
D
R
Q
S
D
R
Q
S
D
R
Q
Q
QH
QH
SER
CLK INH
CLK
Positive Logic Diagram
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
SN74HCT165
SCLS881A – OCTOBER 2021 – REVISED DECEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................4
6.5 Electrical Characteristics.............................................5
6.6 Timing Characteristics.................................................5
6.7 Switching Characteristics............................................6
6.8 Typical Characteristics................................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................15
11 Layout...........................................................................15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 Receiving Notification of Documentation Updates..16
12.3 Support Resources................................................. 16
12.4 Trademarks.............................................................16
12.5 Electrostatic Discharge Caution..............................16
12.6 Glossary..................................................................16
13 Mechanical, Packaging, and Orderable
Information.................................................................... 16
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (October 2021) to Revision A (December 2021)
Page
•
Updated the status of the data sheet from: Advanced Information to: Production Data ....................................1
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5 Pin Configuration and Functions
SH/LD
CLK
E
VCC
1
2
3
4
5
6
16
CLK INH
15
14
D
C
B
A
F
13
12
11
10
9
G
H
QH
SER
QH
7
8
GND
Figure 5-1. PW Package
16-Pin TSSOP
Top View
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1
SH/LD
I
I
Enable shifting when input is high, load data when input is low
Clock, rising edge triggered
Parallel input E
CLK
2
E
F
3
I
4
I
Parallel input F
G
5
I
Parallel input G
H
6
I
Parallel input H
Q H
GND
QH
SER
A
7
O
—
O
I
Inverted serial output
Ground
8
9
Serial output
10
11
12
13
14
15
16
Serial input
I
Parallel input A
B
I
Parallel input B
C
I
Parallel input C
D
I
Parallel input D
CLK INH
VCC
I
Clock inhibit input
Positive supply
—
(1) Signal Types: I = Input, O = Output, I/O = Input or Output.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–20
–20
–35
–70
MAX
7
UNIT
V
VCC
IIK
Supply voltage
Input clamp current(2)
Output clamp current(2)
Continuous output current
VI < 0 or VI > VCC + 0.5 V
VO < 0 or VO > VCC + 0.5 V
VO = 0 to VCC
20
mA
mA
mA
mA
°C
IOK
IO
20
35
ICC
TJ
Continuous output current through VCC or GND
Junction temperature
70
150
150
Tstg
Storage temperature
–65
°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
±4000
±1500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
V(ESD)
Electrostatic discharge
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
4.5
2
NOM
MAX
UNIT
VCC
VIH
VIL
Supply voltage
5
5.5
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 4.5 V to 5.5V
VCC = 4.5 V to 5.5V
0.8
VCC
VCC
500
125
V
VI
0
0
V
VO
Output voltage
V
Δt/Δv
TA
Input transition rise and fall rate VCC = 4.5 V to 5.5V
Ambient temperature
ns/V
°C
–40
6.4 Thermal Information
SN74HCT165
PW (TSSOP)
16 PINS
131.8
THERMAL METRIC(1)
UNIT
RθJA
RθJC(top)
RθJB
ΨJT
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
69.8
76.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
20.9
YJB
76.1
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6.4 Thermal Information (continued)
SN74HCT165
THERMAL METRIC(1)
PW (TSSOP)
16 PINS
N/A
UNIT
RθJC(bot)
Junction-to-case (bottom) thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
-40°C to 125°C
MIN TYP
UNI
T
PARAMETER
TEST CONDITIONS
MIN
MAX
MAX
IOH = -20 uA, VCC
= 4.5 V
4.4
4.4
V
V
V
V
VOH High-level output voltage
VI = VIH or VIL
IOH = -4 mA, VCC
= 4.5 V
3.98
3.84
IOL = 20 uA, VCC
4.5 V
=
0.1
0.1
VOL Low-level output voltage
VI = VIH or VIL
VI = VCC or 0
IOL = 4 mA, VCC
4.5 V
=
0.26
±100
±0.5
0.33
II
Input leakage current
VCC = 5.5 V
VCC = 5.5 V
±1000 nA
±5 µA
Off-State (High-Impedance VO = VCC or 0,
IOZ
State) Output Current
QA-QH
VI = VCC or 0, IO
0
=
ICC Supply current
VCC = 5.5 V
8
80 µA
VCC = 4.5V to
5.5V
VI = VCC - 2.1V
126.2
2.4
157.5 µA
2.9 mA
pF
Additional Quiescent Device
Current Per Input Pin
ΔICC
VI = 0.5 V or 2.4V VCC = 5.5V
VCC = 4.5V to
5.5V
VCC = 4.5V to
5.5V
Ci
Input capacitance
10
VCC = 4.5V to
5.5V
VCC = 4.5V to
5.5V
CO Output capacitance
20
50
pF
pF
Power dissipation
Cpd
No load
capacitance per gate
6.6 Timing Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
-40°C to 125°C
MIN
PARAMETER
CONDITION
VCC
UNIT
MAX
MIN
MAX
fclock
Clock frequency
4.5 V
31
25 MHz
4.5 V
5.5 V
4.5 V
5.5 V
20
20
18
18
25
25
23
23
SH/LD low
tw
Pulse duration
ns
CLK high or low
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UNIT
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6.6 Timing Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
-40°C to 125°C
PARAMETER
CONDITION
SH/LD high before CLK↑
SER before CLK↑
VCC
MIN
20
20
20
20
20
20
20
20
20
20
7
MAX
MIN
25
25
25
25
25
25
25
25
25
25
9
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
tsu
Setup time
CLK INH low before CLK↑
CLK INH high before CLK↑
Data before SH/LD↓
ns
Ser data after CLK↑ or CLK INH↑
PAR data after SH/LD↓
7
9
th
Hold time
ns
7
9
7
9
6.7 Switching Characteristics
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
-40°C to 125°C
UNI
T
PARAMETER
FROM (INPUT)
TO (OUTPUT)
VCC
MIN
MAX
MIN
TYP
MAX
fmax
4.5 V
31
25
MHz
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
40
40
40
40
35
35
12
14
60
60
60
60
53
53
15
17
SH/LD
QH or QH
QH or QH
QH or QH
tpd
Propagation delay CLK
ns
H
Any output
Any output
tt
Transition-time
ns
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6.8 Typical Characteristics
TA = 25°C
4.5
0.3
0.25
0.2
4.45
4.4
4.35
4.3
0.15
0.1
4.25
4.2
0.05
0
4.15
0
1
2
3
4
5
6
0
1
2
3
4
5
6
IOH Output High Current (mA)
IOL Output Low Current (mA)
Figure 6-1. Typical Output Voltage in the High State Figure 6-2. Typical Output Voltage in the Low State
(VOH (VOL
)
)
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tt < 6 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
tw
Test
Point
VCC
0 V
Input
50%
50%
From Output
Under Test
Figure 7-2. Voltage Waveforms, Pulse Duration
(1)
CL
(1) CL includes probe and test-fixture capacitance.
Figure 7-1. Load Circuit for Push-Pull Outputs
VCC
VCC
Clock
Input
50%
Input
Output
Output
50%
50%
0 V
0 V
VOH
VOL
VOH
VOL
(1)
(1)
tPLH
tPHL
tsu
th
VCC
Data
Input
50%
50%
50%
50%
0 V
(1)
(1)
Figure 7-3. Voltage Waveforms, Setup and Hold
Times
tPHL
tPLH
50%
50%
(1) The greater between tPLH and tPHL is the same as tpd
.
Figure 7-4. Voltage Waveforms Propagation Delays
VCC
90%
Input
90%
10%
0 V
10%
tr(1)
tf(1)
VOH
90%
90%
Output
10%
10%
VOL
tr(1)
tf(1)
(1) The greater between tr and tf is the same as tt.
Figure 7-5. Voltage Waveforms, Input and Output Transition Times
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8 Detailed Description
8.1 Overview
The SN74HCT165 is a parallel- or serial-in, serial-out 8-bit shift register.
This device has two modes of operation: load data, and shift data.
When the shift or load (SH/LD) input is held in the low state, the internal registers are loaded with data from the
eight lettered inputs (A-H). This operation is asynchronous. In this state, the output (Q) will have the same state
as the input H, while the inverted output (Q) will have the opposite state.
When the shift or load (SH/LD) input is held in the high state, the internal registers hold their current state until
a clock pulse is received. On the rising edge of the clock (CLK) input, data from the serial input will be loaded
into the first register, and the data in the internal registers will be shifted by one place. The last register will lose
its value. The output (Q) will always be in the same state as the last register, and the inverted output (Q) will
have the opposite state. The clock inhibit (CLK INH) input can be held high to prevent clock pulses from being
detected. CLK and CLK INH are interchangable inputs.
8.2 Functional Block Diagram
A
H
B
C
D
E
F
G
SH/LD
5 Additional
Shift Register
Stages
S
D
R
Q
S
D
R
Q
S
D
R
Q
Q
QH
QH
SER
CLK INH
CLK
Figure 8-1. Logic Diagram (Positive Logic) for SN74HCT165
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8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 TTL-Compatible CMOS Inputs
This device includes TTL-compatible CMOS inputs. These inputs are specifically designed to interface with TTL
logic devices by having a reduced input voltage threshold.
TTL-compatible CMOS inputs are high impedance and are typically modeled as a resistor in parallel with
the input capacitance given in the Electrical Characteristics. The worst case resistance is calculated with the
maximum input voltage, given in the Absolute Maximum Ratings, and the maximum input leakage current, given
in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
TTL-compatible CMOS inputs require that input signals transition between valid logic states quickly, as defined
by the input transition time or rate in the Recommended Operating Conditions table. Failing to meet this
specification will result in excessive power consumption and could cause oscillations. More details can be found
in the Implications of Slow or Floating CMOS Inputs application report.
Do not leave TTL-compatible CMOS inputs floating at any time during operation. Unused inputs must be
terminated at VCC or GND. If a system will not be actively driving an input at all times, a pull-up or pull-down
resistor can be added to provide a valid input voltage during these times. The resistor value will depend on
multiple factors; however, a 10-kΩ resistor is recommended and will typically meet all requirements.
8.3.3 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type
flip-flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.3.4 Clamp Diode Structure
The inputs and outputs to this device have both positive and negative clamping diodes as depicted in Figure 8-2.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage
to the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
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VCC
Logic
GND
Device
+IIK
+IOK
Input
Output
-IIK
-IOK
Figure 8-2. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
The Operating Mode Table and the Output Function Table list the functional modes of the SN74HCT165.
Table 8-1. Operating Mode Table
INPUTS(1)
FUNCTION
SH/LD
CLK
X
CLK INH
L
X
X
H
↑
Parallel load
No change
No change
Shift(2)
H
H
H
H
H
X
L
↑
L
Shift(2)
(1) H = High Voltage Level, L = Low Voltage Level, X = Do not care,
↑ = Low to High transition.
(2) Shift : Content of each internal register shifts towards serial
output QH. Data at SER is shifted into the first register.
Table 8-2. Output Function Table
INTERNAL REGISTERS(1) (2)
OUTPUTS(2)
A — G
H
L
Q
L
Q
H
L
X
X
H
H
(1) Internal registers refer to the shift registers inside the device.
These values are set by either loading data from the parallel
inputs, or by clocking data in from the serial input.
(2) H = High Voltage Level, L = Low Voltage Level, X = Do not care.
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9 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74HCT165 is a parallel-input shift register, which can be used to reduce the number of required inputs on
a system controller very significantly in some applications. Parallel data is loaded into the shift register, then the
stored data can be loaded into a serial input of the system controller by clocking the shift register.
Multiple shift registers can be cascaded to provide more data inputs while still only using a single serial input to
the system controller. This process is primarily limited by the required data input rate and timing characteristics
of the selected shift register, as defined in the Timing Charactestics and Switching Charactestics tables.
An example block diagram is shown for using a single shift register in the Typical Application Block Diagram
below.
9.2 Typical Application
DATA[7:0]
A B C D E F G H
SH/LD
Data Loading Gates
QH
SER
8-Bit Shift Register
Peripheral
System
Controller
QH
CLK
Control
Logic
CLK INH
Figure 9-1. Typical Application Block Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74HCT165 plus the maximum static supply current, ICC, listed in Electrical Characteristics and
any transient current required for switching. The logic device can only source as much current as is provided by
the positive supply source. Be sure not to exceed the maximum total current through VCC listed in the Absolute
Maximum Ratings.
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The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74HCT165 plus the maximum supply current, ICC, listed in Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current as can be sunk into its ground
connection. Be sure not to exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74HCT165 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all of
the datasheet specifications. Larger capacitive loads can be applied, however it is not recommended to exceed
50 pF.
The SN74HCT165 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage and
current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the high state, the
output voltage in the equation is defined as the difference between the measured output voltage and the supply
voltage at the VCC pin.
Total power consumption can be calculated using the information provided in the CMOS Power Consumption
and Cpd Calculation application report.
Thermal increase can be calculated using the information provided in the Thermal Characteristics of Standard
Linear and Logic (SLL) Packages and Devices application report.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. These can be directly terminated if the input is
completely unused, or they can be connected with a pull-up or pull-down resistor if the input is to be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is
used for a default state of LOW. The resistor size is limited by drive current of the controller, leakage current into
the SN74HCT165, as specified in the Electrical Characteristics, and the desired input transition rate. A 10-kΩ
resistor value is often used due to these factors.
The SN74HCT165 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined in
the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to Feature Description section for additional information regarding the outputs for this device.
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9.2.2 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤ 50 pF. This is not a hard limit, however it will ensure
optimal performance. This can be accomplished by providing short, appropriately sized traces from the
SN74HCT165 to the receiving device(s).
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in megaohms; much larger than the minimum calculated above.
4. Thermal issues are rarely a concern for logic gates, however the power consumption and thermal increase
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.3 Application Curve
DATA[7:0]
SH/LD
CLK
0x00
0x11
0x00
QH
Figure 9-2. Application Timing Diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in
given example layout image.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1 ꢀF
16
SH/LD
1
VCC
CLK
E
2
3
4
5
6
7
8
15
14
13
12
11
10
9
CLK INH
D
C
B
A
F
G
Avoid 90°
corners for
signal lines
H
QH
Unused output
left floating
Unused input
tied to VCC
SER
QH
GND
Figure 11-1. Example Layout for the SN74HCT165 in the PW Package
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
•
•
•
Texas Instruments, HCMOS Design Considerations application report
Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
Texas Instruments, Designing With Logic application report
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
12.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PSN74HCT165PWR
SN74HCT165PWR
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
16
16
2000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
2000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
HT165
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2021
OTHER QUALIFIED VERSIONS OF SN74HCT165 :
Automotive : SN74HCT165-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HCT165PWR
SN74HCT165PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
330.0
330.0
12.4
12.4
6.85
6.9
5.45
5.6
1.6
1.6
8.0
8.0
12.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74HCT165PWR
SN74HCT165PWR
TSSOP
TSSOP
PW
PW
16
16
2000
2000
366.0
853.0
364.0
449.0
50.0
35.0
Pack Materials-Page 2
PACKAGE OUTLINE
PW0016A
TSSOP - 1.2 mm max height
S
C
A
L
E
2
.
5
0
0
SMALL OUTLINE PACKAGE
SEATING
PLANE
C
6.6
6.2
TYP
A
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1
2X
5.1
4.9
4.55
NOTE 3
8
9
0.30
16X
4.5
4.3
NOTE 4
1.2 MAX
0.19
B
0.1
C A B
(0.15) TYP
SEE DETAIL A
0.25
GAGE PLANE
0.15
0.05
0.75
0.50
A
20
0 -8
DETAIL A
TYPICAL
4220204/A 02/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.
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EXAMPLE BOARD LAYOUT
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
SYMM
16X (1.5)
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 10X
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL
EXPOSED METAL
EXPOSED METAL
0.05 MAX
ALL AROUND
0.05 MIN
ALL AROUND
NON-SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
15.000
(PREFERRED)
SOLDER MASK DETAILS
4220204/A 02/2017
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
PW0016A
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE
16X (1.5)
SYMM
(R0.05) TYP
16
1
16X (0.45)
SYMM
14X (0.65)
8
9
(5.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE: 10X
4220204/A 02/2017
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
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