SN74HCT240PWR_技术文档

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SCLS174E − MARCH 1984 − REVISED AUGUST 2003

SN54HCT240 . . . J OR W PACKAGE

SN74HCT240 . . . DW, N, NS, OR PW PACKAGE

(TOP VIEW)

D

Operating Voltage Range of 4.5 V to 5.5 V

High-Current Outputs Drive Up To 15

LSTTL Loads

D

Low Power Consumption, 80-µA Max I

Typical t = 12 ns

pd

6-mA Output Drive at 5 V

1OE

1A1

2Y4

1A2

2Y3

1A3

2Y2

1A4

2Y1

1

2

3

4

5

6

7

8

9

20

V

CC

19 2OE

18 1Y1

17 2A4

16 1Y2

15 2A3

14 1Y3

13 2A2

12 1Y4

11 2A1

Low Input Current of 1 µA Max

Inputs Are TTL-Voltage Compatible

3-State Outputs Drive Bus Lines or Buffer

Memory Address Registers

description/ordering information

GND 10

These octal buffers and line drivers are designed

specifically to improve both the performance and

density of 3-state memory address drivers, clock

drivers, and bus-oriented receivers and

transmitters. The ’HCT240 devices are organized

as two 4-bit buffers/drivers with separate

output-enable (OE) inputs. When OE is low, the

device passes inverted data from the A inputs to

the Y outputs. When OE is high, the outputs are

in the high-impedance state.

SN54HCT240 . . . FK PACKAGE

(TOP VIEW)

3

2

1

20 19

18

1Y1

2A4

1Y2

2A3

1Y3

1A2

2Y3

1A3

2Y2

1A4

4

5

6

7

8

17

16

15

14

9 10 11 12 13

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

PDIP − N

Tube of 20

Tube of 25

Reel of 2000

Tube of 70

Reel of 2000

Reel of 250

Tube of 20

Tube of 85

Tube of 55

SN74HCT240N

SN74HCT240DW

SN74HCT240DWR

SN74HCT240NSR

SN74HCT240PW

SN74HCT240PWR

SN74HCT240PWT

SNJ54HCT240J

SOIC − DW

SOP − NS

HCT240

−40°C to 85°C

TSSOP − PW

HT240

CDIP − J

CFP − W

LCCC − FK

SNJ54HCT240J

SNJ54HCT240W

SNJ54HCT240FK

−55°C to 125°C

SNJ54HCT240FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2003, Texas Instruments Incorporated

ꢋ ꢛ ꢦ ꢞ ꢝꢩ ꢤꢣ ꢡꢢ ꢣꢝ ꢟꢦ ꢨꢚ ꢠꢛ ꢡ ꢡꢝ ꢰꢔ ꢍꢘ ꢙꢒ ꢐ ꢘꢗꢱꢂ ꢗꢂꢉ ꢠꢨꢨ ꢦꢠ ꢞ ꢠ ꢟꢥ ꢡꢥꢞ ꢢ ꢠ ꢞ ꢥ ꢡꢥ ꢢꢡꢥ ꢩ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢈꢉ ꢀꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ

ꢋꢅ ꢆꢌ ꢍ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢀ ꢌꢁ ꢓ ꢍꢔ ꢁ ꢑ ꢓꢒ ꢔ ꢕꢑ ꢒꢀ

ꢖꢔ ꢆ ꢄ ꢗ ꢘꢀꢆꢌꢆ ꢑ ꢋꢏꢆ ꢙꢏ ꢆꢀ

SCLS174E − MARCH 1984 − REVISED AUGUST 2003

FUNCTION TABLE

(each buffer/driver)

INPUTS

OUTPUT

Y

OE

A

H

L

H

Z

H

X

logic diagram (positive logic)

1

19

1OE

2OE

18

2

9

7

11

13

1Y1

1Y2

1Y3

1Y4

1A1

2Y1

2Y2

2A1

2A2

2A3

2A4

16

14

12

4

1A2

5

3

6

15

17

1A3

2Y3

2Y4

8

1A4

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

I

Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

IK

I

CC

Output clamp current, I

(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA

OK

O O CC

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA

Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W

JA

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SCLS174E − MARCH 1984 − REVISED AUGUST 2003

recommended operating conditions (see Note 3)

SN54HCT240

SN74HCT240

MIN NOM MAX

UNIT

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.5

2

5

5.5

V

CC

IH

IL

I

High-level input voltage

Low-level input voltage

Input voltage

V

= 4.5 V to 5.5 V

CC

0.8

V

CC

0

V

0

V

CC

Output voltage

V

O

CC

∆t/∆v

Input transition rise/fall time

Operating free-air temperature

500

125

500

85

ns

°C

T

A

−55

−40

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

T

= 25°C

SN54HCT240 SN74HCT240

A

PARAMETER

TEST CONDITIONS

V

UNIT

V

CC

MIN

TYP

MAX

MIN

4.4

MAX

MIN

4.4

MAX

I

= −20 µA

= −6 mA

= 20 µA

= 6 mA

4.4 4.499

OH

OL

V

V = V or V

IH

4.5 V

OH

OL

I

IL

3.98

4.3

0.001

0.17

0.1

3.7

3.84

0.1

0.26

100

0.5

8

0.1

0.4

0.1

0.33

1000

5

V

V = V or V

V

I

IH

IL

I

V = V

I

or 0

5.5 V

1000

10

nA

µA

I

CC

V

O

= V

or 0,

V = V or V

0.01

OZ

CC

I

IH

= 0

IL

V = V

CC

I

O

160

80

I

One input at 0.5 V or 2.4 V,

Other inputs at 0 or V

†

5.5 V

1.4

3

2.4

10

3

2.9

10

mA

pF

∆I

CC

4.5 V

to 5.5 V

C

10

i

†

This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V

.

CC

switching characteristics over recommended operating free-air temperature range, C = 50 pF

L

(unless otherwise noted) (see Figure 1)

T

A

= 25°C

TYP

13

SN54HCT240 SN74HCT240

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

V

UNIT

ns

CC

MIN

MAX

25

MIN

MAX

37

MIN

MAX

32

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

t

A

Y

pd

en

dis

t

12

23

33

29

21

35

53

44

ns

OE

19

32

48

40

19

35

53

44

ns

18

32

48

40

8

12

18

15

ns

7

11

16

14

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄ ꢅ ꢆ ꢇꢃ ꢈꢉ ꢀꢁꢊ ꢃ ꢄꢅ ꢆꢇ ꢃ ꢈ

ꢋꢅ ꢆꢌ ꢍ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢀ ꢌꢁ ꢓ ꢍꢔ ꢁ ꢑ ꢓꢒ ꢔ ꢕꢑ ꢒꢀ

ꢖꢔ ꢆ ꢄ ꢗ ꢘꢀꢆꢌꢆ ꢑ ꢋꢏꢆ ꢙꢏ ꢆꢀ

SCLS174E − MARCH 1984 − REVISED AUGUST 2003

switching characteristics over recommended operating free-air temperature range, C = 150 pF

L

(unless otherwise noted) (see Figure 1)

T

A

= 25°C

TYP

20

SN54HCT240 SN74HCT240

FROM

(INPUT)

TO

(OUTPUT)

PARAMETER

V

UNIT

ns

CC

MIN

MAX

42

MIN

MAX

63

MIN

MAX

53

4.5 V

5.5 V

4.5 V

5.5 V

4.5 V

5.5 V

t

pd

t

en

t

A

Y

19

38

56

48

25

52

79

65

ns

OE

22

47

71

59

17

42

63

53

ns

14

38

57

48

operating characteristics, T = 25°C

A

PARAMETER

TEST CONDITIONS

TYP

UNIT

C

Power dissipation capacitance

No load

40

pF

pd

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢄ

ꢅ

ꢆ

ꢇ

ꢃ

ꢈ

ꢀ

ꢖ ꢔꢆ ꢄ ꢗ ꢘꢀꢆꢌꢆ ꢑ ꢋ ꢏꢆ ꢙꢏ ꢆ

SCLS174E − MARCH 1984 − REVISED AUGUST 2003

PARAMETER MEASUREMENT INFORMATION

V

CC

PARAMETER

R

C

S1

S2

L

50 pF

or

150 pF

t

Open

Closed

Open

S1

S2

PZH

Test

Point

t

1 kΩ

en

R

t

L

PZL

PHZ

PLZ

From Output

Under Test

Open

Closed

Open

50 pF

C

dis

L

Closed

(see Note A)

50 pF

or

150 pF

t

or t

−−

Open

pd

t

LOAD CIRCUIT

Input

3 V

2.7 V

1.3 V

0.3 V

1.3 V

0.3 V

0 V

t

r

f

VOLTAGE WAVEFORM

INPUT RISE AND FALL TIMES

Output

Control

(Low-Level

Enabling)

3 V

0 V

3 V

0 V

Input

1.3 V

t

PLH

PHL

90%

t

PLZ

PZL

V

OH

≈V

CC

In-Phase

Output

Waveform 1

(See Note B)

90%

t

1.3 V

10%

1.3 V

10%

1.3 V

10%

OL

V

OL

OH

t

r

f

t

PHL

90%

PLH

PZH

PHZ

Out-of-

Phase

Output

V

OH

V

Output

Waveform 2

(See Note B)

90%

t

90%

1.3 V

10%

1.3 V

10%

1.3 V

≈0 V

OL

t

r

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS

VOLTAGE WAVEFORMS

PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES

NOTES: A.

C includes probe and test-fixture capacitance.

L

B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.

C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following

characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.

O

r

f

D. The outputs are measured one at a time with one input transition per measurement.

E.

F.

G.

t

and t

are the same as t

.

dis

PLZ

PZL

PLH

PHZ

PZH

PHL

are the same as t

.

en

are the same as t .

pd

Figure 1. Load Circuit and Voltage Waveforms

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

30-May-2005

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

LCCC

CDIP

SOIC

Drawing

85505012A

8550501RA

ACTIVE

FK

J

20

1

TBD

Call TI

Level-NC-NC-NC

JM38510/65753BRA

SN54HCT240J

SN74HCT240DW

J

1

J

1

DW

25

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SN74HCT240DWE4

SN74HCT240DWR

SN74HCT240DWRE4

SN74HCT240N

ACTIVE

SOIC

DW

N

20

25

2000

20

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

SOIC

Pb-Free

(RoHS)

CU NIPDAU Level-2-250C-1 YEAR/

Level-1-235C-UNLIM

PDIP

Pb-Free

(RoHS)

CU NIPDAU Level-NC-NC-NC

SN74HCT240NSR

SN74HCT240NSRE4

SN74HCT240PW

SO

NS

PW

2000

70

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

SO

Pb-Free

(RoHS)

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

TSSOP

Pb-Free

(RoHS)

CU NIPDAU Level-1-250C-UNLIM

SN74HCT240PWE4

SN74HCT240PWR

SN74HCT240PWRE4

SN74HCT240PWT

SN74HCT240PWTE4

70

Pb-Free

(RoHS)

2000

250

Pb-Free

(RoHS)

Pb-Free

(RoHS)

Pb-Free

(RoHS)

Pb-Free

(RoHS)

SNJ54HCT240FK

SNJ54HCT240J

ACTIVE

LCCC

CDIP

FK

J

20

1

TBD

Call TI

Level-NC-NC-NC

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan

-

The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS

&

no Sb/Br)

-

please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

30-May-2005

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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型号：	SN74HCT240PWR
厂家：	TEXAS INSTRUMENTS
描述：	OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS 八路缓冲器并用3态输出线路驱动器总线驱动器总线收发器逻辑集成电路光电二极管输出元件
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