SN74HCT574DW [TI]
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS; 八路边沿触发D型触发器具有三态输出
| 型号： | SN74HCT574DW |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS |
| 文件： | 总6页 (文件大小：118K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MAY 1997
SN54HCT574 . . . J OR W PACKAGE
SN74HCT574 . . . DW, N, OR PW PACKAGE
(TOP VIEW)
Inputs Are TTL-Voltage Compatible
High-Current 3-State Noninverting Outputs
Drive Bus Lines Directly or up to 15 LSTTL
Loads
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
1Q
2Q
1
2
3
4
5
6
7
8
9
20
19
18
Bus-Structured Pinout
Package Options Include Plastic
Small-Outline (DW), Thin Shrink
Small-Outline (PW), and Ceramic Flat (W)
Packages, Ceramic Chip Carriers (FK), and
Standard Plastic (N) and Ceramic (J)
300-mil DIPs
17 3Q
16 4Q
15 5Q
14 6Q
13
7Q
12 8Q
description
GND 10
11 CLK
These octal edge-triggered D-type flip-flops
feature 3-state outputs designed specifically for
bus driving. They are particularly suitable for
implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
SN54HCT574 . . . FK PACKAGE
(TOP VIEW)
3
2
1
20 19
18
The eight flip-flops enter data on the low-to-high
transition of the clock (CLK) input.
2Q
3Q
4Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
A buffered output-enable (OE) input can be used
to place the eight outputs in either a normal logic
state (high or low logic levels) or the
high-impedance state. In the high-impedance
state, the outputs neither load nor drive the bus
lines significantly. The high-impedance state and
increased drive provide the capability to drive bus
lines without interface or pullup components.
15 5Q
14
9 10 11 12 13
6Q
OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
The SN54HCT574 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74HCT574 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MAY 1997
†
logic symbol
1
OE
EN
C1
11
CLK
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1
OE
11
CLK
C1
1D
19
1Q
2
1D
To Seven Other Channels
‡
absolute maximum ratings over operating free-air temperature range
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MAY 1997
recommended operating conditions
SN54HCT574
MIN NOM MAX
SN74HCT574
MIN NOM MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0
0.8
0
0.8
V
CC
0
V
V
0
V
V
V
CC
CC
Output voltage
0
0
V
O
CC
CC
t
Input transition (rise and fall) time
Operating free-air temperature
0
500
125
0
500
85
ns
°C
t
T
–55
–40
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT574 SN74HCT574
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –6 mA
= 20 µA
= 6 mA
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
OH
I
IL
IL
3.98
4.3
0.001
0.17
3.7
3.84
0.1
0.26
±100
±0.5
8
0.1
0.4
0.1
0.33
±1000
±5
V = V or V
V
OL
I
IH
I
I
I
V = V
I
or 0
5.5 V
5.5 V
5.5 V
±0.1
±1000
±10
nA
µA
µA
I
CC
V
O
= V or 0
CC
±0.01
OZ
CC
V = V
I
or 0,
I
O
= 0
160
80
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
5.5 V
1.4
3
2.4
10
3
2.9
mA
pF
∆I
CC
CC
4.5 V
to 5.5 V
C
10
10
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels rather than 0 V or V
CC
.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT574 SN74HCT574
A
V
UNIT
MHz
ns
CC
MIN
0
MAX
30
MIN
0
MAX
20
MIN
0
MAX
24
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
t
t
Clock frequency
clock
0
33
0
22
0
27
16
14
20
17
5
24
22
30
27
5
20
18
25
23
5
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
w
ns
su
h
ns
5
5
5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MAY 1997
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
36
SN54HCT574 SN74HCT574
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
MHz
ns
CC
MIN
30
MAX
MIN
20
MAX
MIN
24
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
t
t
t
max
pd
en
dis
t
33
40
22
27
30
36
32
30
27
30
27
12
11
54
48
45
41
45
41
18
16
45
41
38
34
38
34
15
14
CLK
OE
Any Q
Any Q
Any Q
Any Q
25
26
ns
23
23
ns
OE
22
10
ns
9
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
36
SN54HCT574 SN74HCT574
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
MHz
ns
CC
MIN
30
MAX
MIN
20
MAX
MIN
24
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
t
t
max
pd
en
t
33
40
22
27
40
53
47
47
39
42
38
80
71
71
94
63
57
66
60
59
78
53
48
CLK
OE
Any Q
Any Q
Any Q
35
34
ns
29
18
ns
16
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per flip-flop
TEST CONDITIONS
TYP
UNIT
C
No load
93
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT574, SN74HCT574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS177C – MARCH 1984 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
150 pF
t
t
Open
Closed
Closed
Open
PZH
S1
S2
Test
Point
t
t
1 kΩ
1 kΩ
en
R
PZL
L
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
dis
C
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
3 V
Reference
Input
1.3 V
3 V
0 V
High-Level
0 V
1.3 V
1.3 V
1.3 V
Pulse
t
t
h
su
3 V
0 V
t
Data
Input
w
2.7 V
2.7 V
1.3 V
0.3 V
1.3 V
0.3 V
3 V
0 V
Low-Level
Pulse
1.3 V
t
t
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(Low-Level
Enabling)
3 V
0 V
3 V
0 V
Input
1.3 V
1.3 V
1.3 V
1.3 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
≈ V
In-Phase
Output
Output
Waveform 1
(See Note B)
CC
90%
t
1.3 V
10%
1.3 V
10%
1.3 V
1.3 V
10%
90%
OL
V
OL
t
r
f
f
t
t
t
PZH
PHL
90%
PLH
Out-of-
Phase
Output
V
V
OH
V
OH
Output
Waveform 2
(See Note B)
90%
t
1.3 V
10%
1.3 V
10%
OL
≈ 0 V
t
t
r
PHZ
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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