SN74HCT652DWE4 [TI]
HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24;
| 型号： | SN74HCT652DWE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：471K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
Operating Voltage Range of 4.5 V to 5.5 V
Low Power Consumption, 80-µA Max I
Independent Registers and Enables for
A and B Buses
CC
Multiplexed Real-Time and Stored Data
True Data Paths
Typical t = 12 ns
pd
±6-mA Output Drive at 5 V
High-Current 3-State Outputs Can Drive Up
To 15 LSTTL Loads
Low Input Current of 1 µA Max
Inputs Are TTL-Voltage Compatible
SN54HCT652 . . . FK PACKAGE
(TOP VIEW)
SN54HCT652 . . . JT OR W PACKAGE
SN74HCT652 . . . DW OR NT PACKAGE
(TOP VIEW)
CLKAB
SAB
OEAB
A1
V
CC
1
2
3
4
5
6
7
8
9
24
23
22
21
20
19
18
CLKBA
SBA
OEBA
B1
4
3
2 1 28 27 26
5
6
7
8
9
25 OEBA
A1
A2
A3
NC
A4
A5
A6
24
23
22
21
20
19
B1
B2
NC
B3
B4
B5
A2
A3
B2
A4
B3
A5
17 B4
16 B5
15 B6
10
11
A6
A7 10
12 13 14 15 16 17 18
11
12
14
13
A8
B7
B8
GND
NC – No internal connection
description/ordering information
The ’HCT652 devices consist of bus-transceiver circuits, D-type flip-flops, and control circuitry arranged for
multiplexed transmission of data directly from the data bus or from the internal storage registers. Output-enable
(OEABandOEBA)inputsareprovidedtocontrolthetransceiverfunctions. Select-control(SABandSBA)inputs
are provided to select real-time or stored data transfer. A low input level selects real-time data; a high input level
selects stored data. Figure 1 illustrates the four fundamental bus-management functions that can be performed
with these devices.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – NT
SOIC – DW
Tube
SN74HCT652NT
SN74HCT652DW
SN74HCT652DWR
SNJ54HCT652JT
SNJ54HCT652W
SNJ54HCT652FK
SN74HCT652NT
–40°C to 85°C
–55°C to 125°C
Tube
HCT652
Tape and reel
Tube
CDIP – JT
CFP – W
SNJ54HCT652JT
SNJ54HCT652W
SNJ54HCT652FK
Tube
LCCC – FK
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
description/ordering information (continued)
Data on the A or B data bus, or both, can be stored in the internal D-type flip-flops by low-to-high transitions at
the appropriate clock (CLKAB or CLKBA) terminals, regardless of the select- or output-control terminals. When
SAB and SBA are in the real-time transfer mode, it is possible to store data without using the internal D-type
flip-flops by simultaneously enabling OEAB and OEBA. In this configuration, each output reinforces its input.
When all other data sources to the two sets of bus lines are at high impedance, each set of bus lines remains
at its last state.
To ensure the high-impedance state during power up or power down, OEBA should be tied to V
through a
CC
pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor
is determined by the current-sinking/current-sourcing capability of the driver.
FUNCTION TABLE
†
INPUTS
CLKAB
DATA I/O
OPERATION OR FUNCTION
OEAB
OEBA
CLKBA
SAB
X
SBA
X
A1–A8
Input
B1–B8
Input
L
L
H
H
H
H
X
L
H or L
H or L
Isolation
↑
↑
X
X
Input
Input
Store A and B data
‡
X
H
L
↑
H or L
X
X
Input
Unspecified
Output
Input
Store A, hold B
‡
X
↑
↑
X
Input
Store A in both registers
Hold A, store B
‡
H or L
↑
X
X
Unspecified
Output
Output
Output
Input
‡
X
L
↑
X
↑
X
X
X
X
L
Input
Store B in both registers
Real-time B data to A bus
Stored B data to A bus
Real-time A data to B bus
Stored A data to B bus
L
L
L
Input
L
L
X
H or L
X
H
X
X
Input
H
H
H
H
X
Output
Output
H or L
X
H
Input
Stored A data to B bus and
stored B data to A bus
H
L
H or L
H or L
H
H
Output
Output
†
‡
The data-output functions can be enabled or disabled by a variety of level combinations at OEAB or OEBA. Data-input functions always are
enabled; i.e., data at the bus terminals is stored on every low-to-high transition on the clock inputs.
Select control = L: clocks can occur simultaneously.
Select control = H: clocks must be staggered to load both registers.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
3
21
1
23
2
22
SBA
L
3
21
1
23
2
22
SBA
X
CLKAB CLKBA SAB
CLKAB CLKBA SAB
OEAB OEBA
OEAB OEBA
L
L
X
X
X
H
H
X
X
L
REAL-TIME TRANSFER
BUS B TO BUS A
REAL-TIME TRANSFER
BUS A TO BUS B
3
21
23
2
22
3
21
1
23
CLKAB CLKBA SAB
H or L H or L
2
22
SBA
H
1
CLKAB CLKBA SAB
SBA
X
OEAB OEBA
OEAB OEBA
X
L
L
H
X
H
X
↑
X
X
X
H
L
H
↑
X
X
X
↑
↑
STORAGE FROM
A, B, OR A AND B
TRANSFER STORED DATA
TO A AND/OR B
Pin numbers shown are for the DW, JT, NT, and W packages.
Figure 1. Bus-Management Functions
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
logic diagram (positive logic)
21
OEBA
3
OEAB
23
CLKBA
22
SBA
1
CLKAB
2
SAB
One of Eight Channels
1D
C1
4
A1
20
B1
1D
C1
To Seven Other Channels
Pin numbers shown are for the DW, JT, NT, and W packages.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
(see Note 3): NT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
3. The package thermal impedance is calculated in accordance with JESD 51-3.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
recommended operating conditions (see Note 4)
SN54HCT652
MIN NOM MAX
SN74HCT652
MIN NOM MAX
UNIT
V
V
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 4.5 V to 5.5 V
= 4.5 V to 5.5 V
CC
0.8
0.8
V
CC
0
0
V
V
0
0
V
V
V
CC
CC
Output voltage
V
O
CC
CC
t
Input transition (rise and fall) time
Operating free-air temperature
500
125
500
85
ns
°C
t
T
–55
–40
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HCT652 SN74HCT652
A
PARAMETER
TEST CONDITIONS
V
UNIT
V
CC
MIN
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
I
I
I
= –20 µA
= –6 mA
= 20 µA
= 6 mA
4.4 4.499
OH
OH
OL
OL
V
V
V = V or V
IH
4.5 V
4.5 V
OH
I
IL
3.98
4.3
0.001
0.17
3.7
3.84
0.1
0.26
±100
0.1
0.4
0.1
0.33
V = V or V
V
OL
I
IH
IL
I
I
I
Control inputs V = V
or 0
5.5 V
5.5 V
5.5 V
5.5 V
±0.1
±1000
±1000
nA
µA
µA
mA
I
I
CC
V
O
= V
Data = V
or 0, V = V or V ,
IH IL
CC
CC
I
A or B
±0.01
±0.5
8
±10
160
3
±5
80
OZ
CC
or 0
V = V
I
or 0,
I = 0
O
CC
One input at 0.5 V or 2.4 V,
Other inputs at 0 or V
†
1.4
3
2.4
2.9
∆I
CC
CC
4.5 V
to 5.5 V
C
Control inputs
10
10
10
pF
i
†
This is the increase in supply current for each input that is at one of the specified TTL voltage levels, rather than 0 V or V
CC
.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HCT652 SN74HCT652
A
V
UNIT
MHz
ns
CC
MIN
MAX
25
MIN
MAX
17
MIN
MAX
20
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
t
t
t
Clock frequency
clock
28
19
22
20
18
15
14
5
30
27
23
21
5
25
23
19
17
5
Pulse duration, CLKBA or CLKAB high or low
w
ns
Setup time, A before CLKAB↑ or B before CLKBA↑
Hold time, A after CLKAB↑ or B after CLKBA↑
su
h
ns
5
5
5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 2)
T
A
= 25°C
TYP
35
40
18
16
14
12
20
17
25
22
25
22
9
SN54HCT652 SN74HCT652
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
25
MAX
MIN
17
MAX
MIN
20
MAX
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
f
MHz
max
pd
28
19
22
36
32
27
24
38
34
49
44
49
44
12
11
54
49
41
37
57
51
74
67
74
67
18
16
45
41
34
31
48
43
61
55
61
55
15
14
CLKBA or CLKAB
A or B
A or B
B or A
A or B
A or B
A or B
Any
t
ns
†
SBA or SAB
t
t
t
ns
ns
ns
OEBA or OEAB
OEBA or OEAB
en
dis
t
7
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 2)
T
A
= 25°C
TYP
24
SN54HCT652 SN74HCT652
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
53
47
44
39
55
49
66
59
42
38
MIN
MAX
80
MIN
MAX
66
60
55
50
69
62
82
74
53
48
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
4.5 V
5.5 V
CLKBA or CLKAB
A or B
A or B
B or A
A or B
A or B
Any
22
72
22
70
t
pd
ns
20
60
26
83
†
SBA or SAB
24
74
33
100
90
t
t
ns
ns
OEBA or OEAB
en
30
17
63
t
14
57
†
These parameters are measured with the internal output state of the storage register opposite that of the bus input.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
TYP
UNIT
C
Power dissipation capacitance
No load
50
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HCT652, SN74HCT652
OCTAL BUS TRANSCEIVERS AND REGISTERS
WITH 3-STATE OUTPUTS
SCLS179D – MARCH 1984 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
S1
S2
L
L
50 pF
or
150 pF
t
t
Open
Closed
Closed
Open
PZH
S1
S2
Test
Point
t
t
1 kΩ
1 kΩ
en
R
PZL
L
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
dis
C
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
3 V
Reference
Input
1.3 V
3 V
0 V
High-Level
0 V
1.3 V
1.3 V
1.3 V
Pulse
t
t
h
su
3 V
0 V
t
Data
Input
w
2.7 V
2.7 V
1.3 V
0.3 V
1.3 V
0.3 V
3 V
0 V
Low-Level
Pulse
1.3 V
t
t
r
f
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
Control
(Low-Level
Enabling)
3 V
0 V
3 V
0 V
Input
1.3 V
1.3 V
1.3 V
1.3 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
≈V
CC
In-Phase
Output
Output
Waveform 1
(See Note B)
90%
t
1.3 V
10%
1.3 V
10%
1.3 V
1.3 V
10%
t
OL
V
OL
OH
t
r
f
f
t
t
t
PZH
PHZ
PHL
90%
PLH
Out-of-
Phase
Output
V
V
OH
V
Output
Waveform 2
(See Note B)
90%
t
90%
1.3 V
10%
1.3 V
10%
OL
≈0 V
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT RISE AND FALL TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. For clock inputs, f
is measured when the input duty cycle is 50%.
max
E. The outputs are measured one at a time with one input transition per measurement.
F.
G.
H.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74HCT652DW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
24
24
24
24
24
24
24
24
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HCT652DWE4
SN74HCT652DWG4
SN74HCT652DWR
SN74HCT652DWRE4
SN74HCT652DWRG4
SN74HCT652NT
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
NT
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HCT652NTE4
NT
15
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74HCT652DWR
SOIC
DW
24
2000
330.0
24.4
10.75
15.7
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 24
SPQ
Length (mm) Width (mm) Height (mm)
346.0 346.0 41.0
SN74HCT652DWR
2000
Pack Materials-Page 2
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相关型号：
SN74HCT652DWRE4
HCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, SOIC-24
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