SN74LS04DRG4_技术文档

ꢀꢁꢂ ꢃ ꢄ ꢃ ꢅ ꢀꢁ ꢂꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃꢀ ꢄꢃ ꢅ

ꢀꢁ ꢇꢃ ꢄ ꢃ ꢅ ꢀꢁꢇ ꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢇ ꢃꢀ ꢄꢃ

ꢈꢉꢊ ꢋꢁ ꢌꢉ ꢍ ꢎꢉ ꢍꢀ

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

SN5404 . . . J PACKAGE

SN54LS04, SN54S04 . . . J OR W PACKAGE

SN7404, SN74S04 . . . D, N, OR NS PACKAGE

SN74LS04 . . . D, DB, N, OR NS PACKAGE

(TOP VIEW)

D

Dependable Texas Instruments Quality and

Reliability

description/ordering information

1A

1Y

2A

2Y

3A

1

2

3

4

5

6

7

14

V

CC

These devices contain six independent inverters.

13 6A

12 6Y

11 5A

5Y

4A

4Y

10

9

3Y

GND

8

SN5404 . . . W PACKAGE

(TOP VIEW)

1A

2Y

2A

1

2

3

4

5

6

7

14 1Y

13 6A

12 6Y

11 GND

V

CC

3A

3Y

4A

5Y

5A

4Y

10

9

8

SN54LS04, SN54S04 . . . FK PACKAGE

(TOP VIEW)

3

2

1

20 19

18

6Y

NC

5A

NC

5Y

2A

NC

2Y

4

5

6

7

8

17

16

15

14

NC

3A

9 10 11 12 13

NC − No internal connection

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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Copyright  2004, Texas Instruments Incorporated

ꢐ ꢖ ꢡ ꢙ ꢘꢤ ꢟꢞ ꢜꢝ ꢞꢘ ꢚꢡ ꢣꢕ ꢛꢖ ꢜ ꢜꢘ ꢫꢋ ꢆꢬ ꢏꢍ ꢭ ꢬꢮꢯꢂ ꢮꢂꢅ ꢛꢣꢣ ꢡꢛ ꢙ ꢛ ꢚꢠ ꢜꢠꢙ ꢝ ꢛ ꢙ ꢠ ꢜꢠ ꢝꢜꢠ ꢤ

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ꢜ ꢠ ꢝ ꢜꢕ ꢖꢪ ꢘꢗ ꢛ ꢣꢣ ꢡꢛ ꢙ ꢛ ꢚ ꢠ ꢜ ꢠ ꢙ ꢝ ꢥ

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

T

A

PACKAGE

Tube

SN7404N

SN74LS04N

SN74S04N

SN74LS04N

SN74S04N

PDIP − N

SOIC − D

SOP − NS

SN7404D

7404

LS04

S04

Tape and reel

Tube

SN7404DR

SN74LS04D

SN74LS04DR

SN74S04D

Tape and reel

Tube

0°C to 70°C

Tape and reel

SN74S04DR

SN7404NSR

SN74LS04NSR

SN74S04NSR

SN74LS04DBR

SN5404J

SN7404

74LS04

74S04

SSOP − DB Tape and reel

LS04

Tube

SN5404J

SNJ5404J

SN54LS04J

SN54S04J

SNJ54LS04J

SNJ54S04J

SNJ5404W

SNJ54LS04W

SNJ54S04W

SNJ54LS04FK

SNJ54S04FK

SN54LS04J

SN54S04J

CDIP − J

Tube

SNJ54LS04J

SNJ54S04J

SNJ5404W

−55°C to 125°C

Tube

SNJ54LS04W

SNJ54S04W

SNJ54LS04FK

SNJ54S04FK

CFP − W

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each inverter)

INPUT

A

OUTPUT

Y

H

L

H

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄ ꢃ ꢅ ꢀꢁ ꢂꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃꢀ ꢄꢃ ꢅ

ꢀꢁ ꢇꢃ ꢄ ꢃ ꢅ ꢀꢁꢇ ꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢇ ꢃꢀ ꢄꢃ

ꢈꢉꢊ ꢋꢁ ꢌꢉ ꢍ ꢎꢉ ꢍꢀ

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

logic diagram (positive logic)

1A

2A

3A

4A

5A

1Y

2Y

3Y

4Y

5Y

6Y

6A

Y = A

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

schematics (each gate)

’04

V

CC

4 kΩ

1.6 kΩ

130 Ω

Input A

Output Y

1 kΩ

GND

’LS04

’S04

V

CC

V

CC

20 kΩ

8 kΩ

120 Ω

50 Ω

2.8 kΩ

900 Ω

Input

A

3.5 kΩ

250 Ω

Output

Y

Input

A

Output

Y

4 kΩ

3 kΩ

12 kΩ

500 Ω

1.5 kΩ

GND

Resistor values shown are nominal.

4

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ꢀꢁ ꢇꢃ ꢄ ꢃ ꢅ ꢀꢁꢇ ꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢇ ꢃꢀ ꢄꢃ

ꢈꢉꢊ ꢋꢁ ꢌꢉ ꢍ ꢎꢉ ꢍꢀ

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

CC

Input voltage, V : ’04, ’S04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

I

’LS04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Package thermal impedance, θ (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W

JA

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. This are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values are with respect to network ground terminal.

2. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 3)

SN7404

SN5404

MIN NOM

UNIT

MAX

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

IH

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

0.8

−0.4

16

0.8

−0.4

16

V

IL

I

mA

°C

OH

OL

T

A

−55

125

0

70

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN5404

SN7404

‡

PARAMETER

UNIT

TEST CONDITIONS

§

MIN TYP

MAX

MIN TYP

MAX

V

= MIN,

= MAX,

= MAX

I = −12 mA

−1.5

V

IK

CC

I

V

= 0.8 V,

= 2 V,

I

= −0.4 mA

= 16 mA

2.4

3.4

0.2

2.4

3.4

0.2

OH

OL

IL

OH

OL

V

IH

0.4

1

0.4

1

V

I

V = 5.5 V

I

V = 2.4 V

I

V = 0.4 V

I

mA

µA

mA

I

40

IH

IL

−1.6

−55

−1.6

−55

¶

−20

−18

I

OS

V

CC

V

CC

= MAX,

V = 0 V

I

V = 4.5 V

I

6

12

33

6

12

33

mA

CCH

CCL

18

‡

§

¶

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

CC

A

Not more than one output should be shorted at a time.

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

switching characteristics, V

= 5 V, T = 25°C (see Figure 1)

CC

A

SN5404

SN7404

FROM

TO

(OUTPUT)

PARAMETER

(INPUT)

TEST CONDITIONS

UNIT

MIN

TYP

12

8

MAX

22

t

PLH

PHL

A

Y

R

= 400 Ω,

C

= 15 pF

L

ns

L

15

recommended operating conditions (see Note 3)

SN74LS04

SN54LS04

UNIT

MIN NOM

MAX

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

IH

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

0.7

−0.4

4

0.8

−0.4

8

V

IL

I

mA

°C

OH

OL

T

A

−55

125

0

70

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LS04

SN74LS04

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

= MIN,

I = −18 mA

−1.5

V

IK

CC

I

V

IL

= MAX,

= 2 V

I

= −0.4 mA

= 4 mA

2.5

3.4

2.7

3.4

OH

OL

0.25

0.4

0.5

V

OL

V

CC

= MIN,

V

IH

V

= 8 mA

0.25

I

V

= MAX,

= MAX

V = 7 V

0.1

20

0.1

mA

µA

mA

I

CC

I

V = 2.7 V

I

V = 0.4 V

I

20

IH

IL

−0.4

−100

−0.4

−100

§

−20

I

OS

V

CC

V

CC

= MAX,

V = 0 V

I

V = 4.5 V

I

1.2

3.6

2.4

6.6

1.2

3.6

2.4

6.6

mA

CCH

CCL

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

CC

A

switching characteristics, V

= 5 V, T = 25°C (see Figure 2)

CC

A

SN54LS04

SN74LS04

FROM

TO

(OUTPUT)

PARAMETER

(INPUT)

TEST CONDITIONS

UNIT

MIN

TYP

9

MAX

15

t

PLH

PHL

A

Y

R

= 2 kΩ,

C

= 15 pF

L

ns

L

10

15

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢇꢃ ꢄ ꢃ ꢅ ꢀꢁꢇ ꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢇ ꢃꢀ ꢄꢃ

ꢈꢉꢊ ꢋꢁ ꢌꢉ ꢍ ꢎꢉ ꢍꢀ

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

recommended operating conditions (see Note 3)

SN74S04

SN54S04

UNIT

MIN NOM

MAX

MIN NOM

MAX

V

Supply voltage

4.5

2

5

5.5

4.75

2

5

5.25

V

CC

IH

High-level input voltage

Low-level input voltage

High-level output current

Low-level output current

Operating free-air temperature

0.8

−1

0.8

−1

20

70

V

IL

I

mA

°C

OH

20

OL

T

A

−55

125

0

NOTE 3: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54S04

SN74S04

†

PARAMETER

UNIT

TEST CONDITIONS

‡

MIN TYP

MAX

MIN TYP

MAX

V

= MIN,

= MAX,

= MAX

I = −18 mA

−1.2

V

IK

CC

I

V

= 0.8 V,

= 2 V,

I

= −1 mA

= 20 mA

2.5

3.4

2.7

3.4

OH

OL

IL

OH

OL

V

IH

0.5

1

0.5

1

V

I

V = 5.5 V

I

V = 2.7 V

I

V = 0.5 V

I

mA

µA

mA

I

50

IH

IL

−2

§

−40

−100

−40

−100

I

OS

V

CC

V

CC

= MAX,

V = 0 V

I

V = 4.5 V

I

15

30

24

54

15

30

24

54

mA

CCH

CCL

†

‡

§

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

All typical values are at V = 5 V, T = 25°C.

CC

A

Not more than one output should be shorted at a time, and the duration of the short-circuit should not exceed one second.

switching characteristics, V

= 5 V, T = 25°C (see Figure 1)

CC

A

SN54S04

SN74S04

FROM

TO

(OUTPUT)

PARAMETER

(INPUT)

TEST CONDITIONS

UNIT

MIN

TYP

3

MAX

4.5

5

t

PLH

PHL

PLH

PHL

A

Y

R

= 280 Ω,

C

= 15 pF

= 50 pF

ns

L

3

4.5

5

7

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 AND 54S/74S DEVICES

V

CC

Test

Point

R

L

Test

Point

S1

V

CC

From Output

Under Test

V

CC

(see Note B)

R

L

C

L

(see Note A)

From Output

Under Test

1 kΩ

R

L

(see Note B)

From Output

Under Test

C

Test

Point

C

L

(see Note A)

L

(see Note A)

S2

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.5 V

Pulse

0 V

t

h

w

t

su

3 V

0 V

Low-Level

Pulse

Data

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

Output

Control

(low-level

enabling)

1.5 V

3 V

0 V

Input

1.5 V

t

PLZ

PZL

t

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

1.5 V

V

OH

Output

(see Note D)

V

OL

+ 0.5 V

1.5 V

V

OL

V

OL

t

PZH

PHZ

t

PLH

PHL

V

OH

Waveform 2

(see Notes C

and D)

V

OH

− 0.5 V

Out-of-Phase

Output

(see Note D)

V

OH

1.5 V

≈1.5 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C

includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

PZH

; S1 is closed and S2 is open for t

.

PLH PHL PHZ

PLZ

PZL

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series

O

r

f

54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.

r

f

F. The outputs are measured one at a time, with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁꢂ ꢃ ꢄ ꢃ ꢅ ꢀꢁ ꢂꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢂ ꢃꢀ ꢄꢃ ꢅ

ꢀꢁ ꢇꢃ ꢄ ꢃ ꢅ ꢀꢁꢇ ꢃ ꢆ ꢀꢄ ꢃ ꢅ ꢀ ꢁꢇ ꢃꢀ ꢄꢃ

ꢈꢉꢊ ꢋꢁ ꢌꢉ ꢍ ꢎꢉ ꢍꢀ

SDLS029C − DECEMBER 1983 − REVISED JANUARY 2004

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

V

CC

Test

Point

R

L

Test

Point

S1

V

CC

From Output

Under Test

V

CC

(see Note B)

R

L

C

L

(see Note A)

From Output

Under Test

5 kΩ

R

L

(see Note B)

From Output

Under Test

C

Test

Point

C

L

(see Note A)

L

(see Note A)

S2

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.3 V

Pulse

0 V

t

h

w

t

su

3 V

0 V

Low-Level

Pulse

Data

Input

1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

3 V

0 V

Control

(low-level

enabling)

1.3 V

3 V

0 V

Input

1.3 V

t

PLZ

PZL

t

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

Output

(see Note D)

1.3 V

V

OH

V

OL

+ 0.5 V

1.3 V

V

OL

t

PHZ

OL

t

PZH

t

PLH

PHL

V

OH

Waveform 2

(see Notes C

and D)

V

OH

− 0.5 V

Out-of-Phase

Output

(see Note D)

V

OH

1.3 V

≈1.5 V

OL

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

C

includes probe and jig capacitance.

L

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open and S2 is closed for t

; S1 is closed and S2 is open for t .

PLH PHL PHZ

PLZ

PZH

PZL

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.

O

r

f

G. The outputs are measured one at a time, with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

9

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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www.ti.com/automotive

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www.ti.com/military

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interface.ti.com

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Microcontrollers

power.ti.com

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Security

www.ti.com/opticalnetwork

www.ti.com/security

microcontroller.ti.com

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www.ti.com/telephony

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Wireless

www.ti.com/video

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

23-Apr-2007

PACKAGING INFORMATION

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

CDIP

CFP

Drawing

JM38510/00105BCA

JM38510/00105BDA

JM38510/07003BCA

JM38510/30003B2A

JM38510/30003BCA

JM38510/30003BDA

JM38510/30003SCA

JM38510/30003SDA

SN5404J

ACTIVE

J

W

J

14

20

14

1

TBD

A42 SNPB

A42

N / A for Pkg Type

CDIP

LCCC

CDIP

CFP

A42 SNPB

FK

J

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

J

CDIP

CFP

A42 SNPB

A42

W

J

CDIP

SOIC

A42 SNPB

SN54LS04J

J

SN54S04J

J

SN7404D

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN7404DE4

SN7404DG4

SN7404DR

ACTIVE

SOIC

PDIP

D

N

14

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN7404DRE4

SN7404DRG4

SN7404N

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN7404N3

OBSOLETE

ACTIVE

PDIP

N

14

TBD

Call TI

SN7404NE4

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN7404NSR

SN7404NSRE4

SN74LS04D

ACTIVE

SO

NS

D

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS04DE4

SN74LS04DG4

SN74LS04DR

SN74LS04DRE4

SN74LS04DRG4

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LS04J

SN74LS04N

OBSOLETE

ACTIVE

CDIP

PDIP

J

14

TBD

Call TI

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

23-Apr-2007

Orderable Device

Status ⁽¹⁾

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

PDIP

Drawing

SN74LS04N3

OBSOLETE

ACTIVE

N

14

TBD

Call TI

SN74LS04NE4

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74LS04NSR

SN74LS04NSRG4

SN74S04D

ACTIVE

SO

NS

D

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

PDIP

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74S04DE4

SN74S04DG4

SN74S04DR

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74S04DRE4

SN74S04DRG4

SN74S04N

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

N

25

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74S04N3

OBSOLETE

ACTIVE

PDIP

N

14

TBD

Call TI

SN74S04NE4

Pb-Free

(RoHS)

CU NIPDAU N / A for Pkg Type

SN74S04NSR

ACTIVE

SO

NS

14

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74S04NSRE4

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SNJ5404J

SNJ5404W

ACTIVE

CDIP

CFP

J

W

FK

J

14

20

14

20

14

1

TBD

A42 SNPB

A42

N / A for Pkg Type

SNJ54LS04FK

SNJ54LS04J

SNJ54LS04W

SNJ54S04FK

SNJ54S04J

SNJ54S04W

LCCC

CDIP

CFP

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

FK

J

LCCC

CDIP

CFP

POST-PLATE N / A for Pkg Type

A42 SNPB

A42

N / A for Pkg Type

W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

23-Apr-2007

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Apr-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Apr-2007

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

(mm)

16

SN7404DR

SN7404NSR

SN74LS04DR

SN74LS04NSR

SN74S04DR

SN74S04NSR

D

NS

D

14

MLA

6.5

8.2

6.5

8.2

6.5

8.2

9.0

10.5

9.0

2.1

2.5

2.1

2.5

2.1

2.5

8

12

8

16

Q1

16

NS

D

16

10.5

9.0

12

8

16

NS

16

10.5

12

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

SN7404DR

SN7404NSR

SN74LS04DR

SN74LS04NSR

SN74S04DR

SN74S04NSR

D

NS

D

14

MLA

333.2

28.58

NS

D

NS

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

30-Apr-2007

Pack Materials-Page 3

MECHANICAL DATA

MLCC006B – OCTOBER 1996

FK (S-CQCC-N**)

LEADLESS CERAMIC CHIP CARRIER

28 TERMINAL SHOWN

A

B

NO. OF

TERMINALS

**

18 17 16 15 14 13 12

MIN

MAX

MIN

MAX

0.342

(8,69)

0.358

(9,09)

0.307

(7,80)

0.358

(9,09)

19

20

11

10

9

20

28

44

52

68

84

0.442

(11,23)

0.458

(11,63)

0.406

(10,31)

0.458

(11,63)

21

B SQ

22

0.640

(16,26)

0.660

(16,76)

0.495

(12,58)

0.560

(14,22)

8

A SQ

23

0.739

(18,78)

0.761

(19,32)

0.495

(12,58)

0.560

(14,22)

7

24

25

6

0.938

(23,83)

0.962

(24,43)

0.850

(21,6)

0.858

(21,8)

5

1.141

(28,99)

1.165

(29,59)

1.047

(26,6)

1.063

(27,0)

26 27 28

1

2

3

4

0.080 (2,03)

0.064 (1,63)

0.020 (0,51)

0.010 (0,25)

0.020 (0,51)

0.010 (0,25)

0.055 (1,40)

0.045 (1,14)

0.035 (0,89)

0.045 (1,14)

0.035 (0,89)

0.028 (0,71)

0.022 (0,54)

0.050 (1,27)

4040140/D 10/96

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. This package can be hermetically sealed with a metal lid.

D. The terminals are gold plated.

E. Falls within JEDEC MS-004