SN74LS147N-00 [TI]

LS SERIES, 9-BIT ENCODER, PDIP16;


型号：	SN74LS147N-00
厂家：	TEXAS INSTRUMENTS
描述：	LS SERIES, 9-BIT ENCODER, PDIP16 编码器光电二极管逻辑集成电路
文件：	总26页 (文件大小：1200K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

’147, ’LS147

’148, ’LS148

Encode 10-Line Decimal to 4-Line BCD

Encode 8 Data Lines to 3-Line Binary

(Octal)

Applications Include:

− Keyboard Encoding

− Range Selection

Applications Include:

− n-Bit Encoding

− Code Converters and Generators

SN54147, SN54LS147 . . . J OR W PACKAGE

SN74147, SN74LS147 . . . D OR N PACKAGE

(TOP VIEW)

SN54148, SN54LS148 . . . J OR W PACKAGE

SN74148, SN74LS148 . . . D, N, OR NS PACKAGE

(TOP VIEW)

GND

SN54LS147 . . . FK PACKAGE

(TOP VIEW)

SN54LS148 . . . FK PACKAGE

(TOP VIEW)

1 20 19

16 NC

9 10 11 12 13

NC − No internal connection

TYPICAL

DATA

DELAY

TYPICAL

POWER

TYPE

’147

DISSIPATION

225 mW

190 mW

60 mW

10 ns

15 ns

’148

’LS147

’LS148

60 mW

NOTE: The SN54147, SN54LS147, SN54148, SN74147, SN74LS147, and SN74148 are obsolete and are no longer supplied.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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ꢒ ꢜ ꢧ ꢟ ꢞꢪ ꢥꢤ ꢢꢣ ꢤꢞ ꢠꢧ ꢩꢛ ꢡꢜ ꢢ ꢢꢞ ꢌꢋ ꢈꢐ ꢖꢗ ꢱ ꢐꢕꢇꢂ ꢕꢂꢆ ꢡꢩꢩ ꢧꢡ ꢟ ꢡ ꢠꢦ ꢢꢦꢟ ꢣ ꢡ ꢟ ꢦ ꢢꢦ ꢣꢢꢦ ꢪ

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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ

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ꢥ ꢜꢩ ꢦꢣꢣ ꢞ ꢢꢬꢦ ꢟ ꢮꢛ ꢣꢦ ꢜ ꢞꢢꢦ ꢪꢫ ꢒ ꢜ ꢡꢩ ꢩ ꢞ ꢢꢬꢦ ꢟ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢣ ꢆ ꢧꢟ ꢞ ꢪꢥꢤ ꢢꢛꢞ ꢜ

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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢂ ꢃꢄ ꢃ ꢇ ꢆ ꢀ ꢁꢂ ꢃ ꢈꢀ ꢄ ꢃꢅ ꢆ ꢀ ꢁꢂ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

description/ordering information

These TTL encoders feature priority decoding of the inputs to ensure that only the highest-order data line is

encoded. The ’147 and ’LS147 devices encode nine data lines to four-line (8-4-2-1) BCD. The implied decimal

zero condition requires no input condition, as zero is encoded when all nine data lines are at a high logic level.

The ’148 and ’LS148 devices encode eight data lines to three-line (4-2-1) binary (octal). Cascading circuitry

(enable input EI and enable output EO) has been provided to allow octal expansion without the need for external

circuitry. For all types, data inputs and outputs are active at the low logic level. All inputs are buffered to represent

one normalized Series 54/74 or 54/74LS load, respectively.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

PDIP − N

SOIC − D

Tube

SN74LS148N

SN74LS148D

SN74LS148DR

SN74LS148NSR

SNJ54LS148J

SNJ54LS148W

SNJ54LS148FK

SN74LS148N

Tube

0°C to 70°C

LS148

Tape and reel

Tube

SOP − NS

CDIP − J

74LS148

SNJ54LS148J

SNJ54LS148W

SNJ54LS148FK

−55°C to 125°C

CFP − W

LCCC − FK

Tube

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are

available at www.ti.com/sc/package.

FUNCTION TABLE − ’147, ’LS147

INPUTS

OUTPUTS

H = high logic level, L = low logic level, X = irrelevant

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

FUNCTION TABLE − ’148, ’LS148

INPUTS

OUTPUTS

H = high logic level, L = low logic level, X = irrelevant

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

’147, ’LS147 logic diagram (positive logic)

(11)

(12)

(9)

(13)

(1)

(7)

(2)

(3)

(4)

(6)

(5)

(14)

(10)

Pin numbers shown are for D, J, N, and W packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

’148, ’LS148 logic diagram (positive logic)

(10)

(15)

(14)

(11)

(12)

(9)

(13)

(1)

(7)

(2)

(3)

(4)

(6)

(5)

Pin numbers shown are for D, J, N, NS, and W packages.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

schematics of inputs and outputs

’147, ’148

EQUIVALENT OF EACH INPUT

TYPICAL OF ALL OUTPUTS

ꢀ ꢁ Ω NOM

Input

Output

0 input (’148): R = 2 kΩ NOM

All other inputs: R = 4 kΩ NOM

’LS147, ’LS148

TYPICAL OF ALL OUTPUTS

EQUIVALENT OF ALL INPUTS

120 Ω NOM

Input

Output

’LS148 inputs 1–7: R = 9 kΩ NOM

All other inputs: R = 18 kΩ NOM

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

†

absolute maximum ratings over operating free-air temperature (unless otherwise noted)

Supply voltage, V

(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Input voltage, V : ’147, ’148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

’LS147, ’LS148 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

Inter-emitter voltage: ’148 only (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V

Package thermal impedance θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

Storage temperature range, T

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. Voltage values, except inter-emitter voltage, are with respect to the network ground terminal.

2. This is the voltage between two emitters of a multiple-emitter transistor. For ’148 circuits, this rating applies between any two of the

eight data lines, 0 through 7.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

recommended operating conditions (see Note 4)

SN54’

SN74’

SN54LS’

SN74LS’

UNIT

MIN NOM MAX

Supply voltage

4.5

5.5 4.75

−800

5.25

−800

4.5

5.5 4.75

−400

5.25

−400

High-level output current

Low-level output current

Operating free-air temperature

µA

°C

−55

125

−55

125

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

’147

’148

†

PARAMETER

TEST CONDITIONS

UNIT

‡

MIN TYP

MAX

MIN TYP

MAX

High-level input voltage

Low-level input voltage

Input clamp voltage

0.8

= MIN,

I = −12 mA

−1.5

= 2 V,

= −800 µA

High-level output voltage

Low-level output voltage

2.4

3.3

2.4

3.3

= 0.8 V,

= MIN,

= 0.8 V,

= 2 V,

= 16 mA

0.2

0.4

0.2

0.4

Input current at maximum input

voltage

= MIN,

= MAX,

V = 5.5 V

0 input

High-level input

current

V = 2.4 V

µA

Any input except 0

0 input

−1.6

−3.2

−85

Low-level input

current

V = 0.4 V

Any input except 0

−1.6

−85

Short-circuit output current

= MAX

−35

Condition 1

Condition 2

Supply current

(See Note 5)

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡

All typical values are at V

Not more than one output should be shorted at a time.

= 5 V, T = 25°C.

NOTE 5: For ’147, I

(Condition 1) is measured with input 7 grounded, other inputs and outputs open; I

(Condition 2) is measured with all

(Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open; I

inputs and outputs open. For ’148, I

(Condition 2) is measured with all inputs and outputs open.

SN54147, SN74147 switching characteristics, V

= 5 V, T = 255C (see Figure 1)

FROM

TEST

PARAMETER

WAVEFORM

MIN

TYP

MAX

UNIT

(INPUT)

(OUTPUT)

CONDITIONS

PLH

PHL

PLH

PHL

Any

In-phase output

= 15 pF,

= 400 Ω

Out-of-phase output

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

SN54148, SN74148 switching characteristics, V

= 5 V, T = 255C (see Figure 1)

FROM

TEST

†

PARAMETER

WAVEFORM

In-phase output

Out-of-phase output

In-phase output

MIN

TYP

MAX

UNIT

(INPUT)

(OUTPUT)

CONDITIONS

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

1–7

0–7

A0, A1, or A2

= 15 pF,

= 400 Ω

A0, A1, or A2

†

= propagation delay time, low-to-high-level output.

= propagation delay time, high-to-low-level output.

PLH

PHL

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LS’

SN74LS’

†

PARAMETER

TEST CONDITIONS

UNIT

‡

MIN TYP

MAX

MIN TYP

MAX

High-level input voltage

Low-level input voltage

Input clamp voltage

0.7

0.8

= MIN,

I = −18 mA

−1.5

= 2 V,

= −400 µA

High-level output voltage

2.5

3.4

2.7

3.4

= 0.8 V,

= MIN,

= 2 V,

= 4 mA

= 8 mA

0.25

0.4

0.25

0.35

0.4

0.5

0.2

0.1

Low-level output voltage

= V MAX

Input current at

maximum input

voltage

’LS148 inputs 1–7

All other inputs

0.2

0.1

= MAX,

V = 7 V

’LS148 inputs 1–7

All other inputs

High-level input

current

= MAX,

V = 2.7 V

µA

’LS148 inputs 1–7

All other inputs

−0.8

−0.4

−100

−0.8

−0.4

−100

Low-level input

current

V = 0.4 V

Short-circuit output current

= MAX

−20

Condition 1

Condition 2

Supply current

(See Note 6)

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

‡

All typical values are at V

Not more than one output should be shorted at a time.

= 5 V, T = 25°C.

NOTE 6: For ’LS147, I

(Condition 1) is measured with input 7 grounded, other inputs and outputs open; I

(Condition 2) is measured with

(Condition 1) is measured with inputs 7 and EI grounded, other inputs and outputs open;

all inputs and outputs open. For ’LS148, I

(Condition 2) is measured with all inputs and outputs open.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

SN54LS147, SN74LS147 switching characteristics, V

= 5 V, T = 255C (see Figure 2)

FROM

TEST

PARAMETER

WAVEFORM

MIN

TYP

MAX

UNIT

(INPUT)

(OUTPUT)

CONDITIONS

PLH

PHL

PLH

PHL

Any

In-phase output

= 15 pF,

= 2 kΩ

Out-of-phase output

SN54LS148, SN74LS148 switching characteristics, V

= 5 V, T = 255C (see Figure 2)

FROM

TEST

†

PARAMETER

WAVEFORM

MIN

TYP

MAX

UNIT

(INPUT)

(OUTPUT)

CONDITIONS

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PHL

1–7

0–7

A0, A1, or A2

In-phase output

Out-of-phase output

In-phase output

A0, A1, or A2

= 15 pF,

= 2 kΩ

A0, A1, or A2

†

= propagation delay time, low-to-high-level output

= propagation delay time, high-to-low-level output

PLH

PHL

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION

SERIES 54/74 DEVICES

Test

Point

Test

Point

From Output

Under Test

(see Note B)

(see Note A)

From Output

Under Test

1 kΩ

(see Note B)

From Output

Under Test

Test

Point

(see Note A)

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.5 V

Pulse

0 V

3 V

0 V

Low-Level

Pulse

Data

Input

1.5 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

3 V

0 V

Output

Control

(low-level

enabling)

1.5 V

3 V

0 V

Input

1.5 V

PLZ

PZL

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

1.5 V

Output

(see Note D)

+ 0.5 V

1.5 V

PZH

PHZ

PLH

PHL

Waveform 2

(see Notes C

and D)

− 0.5 V

Out-of-Phase

Output

(see Note D)

1.5 V

≈1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open, and S2 is closed for t

PZH

; S1 is closed, and S2 is open for t

PLH PHL PHZ

PLZ

PZL

E. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω; t and t ≤ 7 ns for Series

54/74 devices and t and t ≤ 2.5 ns for Series 54S/74S devices.

F. The outputs are measured one at a time, with one input transition per measurement.

Figure 1. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢀꢁ ꢅ ꢃꢄꢃ ꢇ ꢉꢊ ꢋ ꢌꢍ ꢍꢎ ꢅ ꢏꢆ ꢀ ꢁꢅ ꢃ ꢈꢀ ꢄꢃ ꢅ ꢆ ꢀꢁꢅ ꢃ ꢈ ꢀꢄ ꢃ ꢇ

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

PARAMETER MEASUREMENT INFORMATION

SERIES 54LS/74LS DEVICES

Test

Point

Test

Point

From Output

Under Test

(see Note B)

(see Note A)

From Output

Under Test

5 kΩ

(see Note B)

From Output

Under Test

Test

Point

(see Note A)

LOAD CIRCUIT

FOR 2-STATE TOTEM-POLE OUTPUTS

FOR OPEN-COLLECTOR OUTPUTS

FOR 3-STATE OUTPUTS

3 V

High-Level

Timing

Input

1.3 V

Pulse

0 V

3 V

0 V

Low-Level

Pulse

Data

Input

1.3 V

VOLTAGE WAVEFORMS

PULSE DURATIONS

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

Output

3 V

0 V

Control

(low-level

enabling)

1.3 V

3 V

0 V

Input

1.3 V

PLZ

PZL

PHL

PLH

Waveform 1

(see Notes C

and D)

≈1.5 V

In-Phase

Output

(see Note D)

1.3 V

+ 0.5 V

1.3 V

PHZ

PZH

PLH

PHL

Waveform 2

(see Notes C

and D)

− 0.5 V

Out-of-Phase

Output

(see Note D)

1.3 V

≈1.5 V

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS

NOTES: A.

includes probe and jig capacitance.

B. All diodes are 1N3064 or equivalent.

C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

D. S1 and S2 are closed for t

, t

, and t

; S1 is open, and S2 is closed for t

; S1 is closed, and S2 is open for t .

PLH PHL PHZ

PLZ

PZH

PZL

E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.

F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.

G. The outputs are measured one at a time, with one input transition per measurement.

Figure 2. Load Circuits and Voltage Waveforms

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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SDLS053B − OCTOBER 1976 − REVISED MAY 2004

APPLICATION INFORMATION

16-Line Data (active low)

9 10 11 12 13 14 15

Enable

(active low)

7 EI

’148/’LS148

’148/LS148

EO A0

A2 GS

’08/’LS08

Priority Flag

(active low)

Encoded Data (active low)

16-Line Data (active low)

9 10 11 12 13 14 15

Enable

(active low)

7 EI

’148/’LS148

EO A0

A2 GS

’HC00

Priority Flag

(active high)

Encoded Data (active high)

Figure 3. Priority Encoder for 16 Bits

Because the ’147/’LS147 and ’148/’LS148 devices are combinational logic circuits, wrong addresses can appear

during input transients. Moreover, for the ’148/’LS148 devices, a change from high to low at EI can cause a transient

low on GS when all inputs are high. This must be considered when strobing the outputs.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

PACKAGING INFORMATION

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

78027012A

ACTIVE

LCCC

TBD

POST-PLATE

N / A for Pkg Type

-55 to 125

78027012A

SNJ54LS

148FK

7802701EA

ACTIVE

CDIP

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

7802701EA

SNJ54LS148J

7802701FA

SNJ54LS148W

JM38510/36001B2A

JM38510/36001BEA

JM38510/36001BFA

M38510/36001B2A

M38510/36001BEA

M38510/36001BFA

LCCC

CDIP

CFP

POST-PLATE

A42

JM38510/

36001B2A

JM38510/

36001BEA

A42

JM38510/

36001BFA

LCCC

CDIP

CFP

POST-PLATE

A42

JM38510/

36001B2A

JM38510/

36001BEA

A42

JM38510/

36001BFA

SN54148J

OBSOLETE

ACTIVE

CDIP

TBD

Call TI

A42

Call TI

-55 to 125

SN54LS148J

N / A for Pkg Type

SN54LS148J

SN74147N

SN74148J

OBSOLETE

ACTIVE

PDIP

CDIP

PDIP

SOIC

PDIP

SOIC

TBD

Call TI

0 to 70

SN74148N

Call TI

SN74148N3

SN74LS147DR

SN74LS147N

SN74LS148D

Call TI

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

LS148

SN74LS148DE4

SN74LS148DG4

ACTIVE

SOIC

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

Green (RoHS

& no Sb/Br)

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

Orderable Device

Status Package Type Package Pins Package

Eco Plan Lead/Ball Finish

MSL Peak Temp

Op Temp (°C)

0 to 70

Device Marking

Samples

Drawing

Qty

(1)

(2)

(3)

(4/5)

SN74LS148DR

SN74LS148DRE4

SN74LS148DRG4

ACTIVE

SOIC

2500

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

LS148

ACTIVE

2500

Green (RoHS

& no Sb/Br)

0 to 70

LS148

Green (RoHS

& no Sb/Br)

0 to 70

SN74LS148J

SN74LS148N

OBSOLETE

ACTIVE

CDIP

PDIP

TBD

Call TI

0 to 70

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

SN74LS148N

SN74LS148N3

SN74LS148NE4

OBSOLETE

ACTIVE

PDIP

TBD

Call TI

0 to 70

Pb-Free

(RoHS)

CU NIPDAU

N / A for Pkg Type

SN74LS148N

74LS148

SN74LS148NSR

SN74LS148NSRE4

SN74LS148NSRG4

ACTIVE

2000

Green (RoHS

& no Sb/Br)

CU NIPDAU

Level-1-260C-UNLIM

0 to 70

Green (RoHS

& no Sb/Br)

74LS148

Green (RoHS

& no Sb/Br)

74LS148

SNJ54148J

SNJ54148W

OBSOLETE

ACTIVE

CDIP

CFP

TBD

Call TI

-55 to 125

SNJ54LS148FK

LCCC

POST-PLATE

N / A for Pkg Type

78027012A

SNJ54LS

148FK

SNJ54LS148J

SNJ54LS148W

ACTIVE

CDIP

CFP

TBD

A42

N / A for Pkg Type

-55 to 125

7802701EA

SNJ54LS148J

7802701FA

SNJ54LS148W

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

⁽²⁾Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

Addendum-Page 2

PACKAGE OPTION ADDENDUM

www.ti.com

25-Sep-2013

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

⁽³⁾MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

⁽⁴⁾There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

⁽⁵⁾Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF SN54147, SN54148, SN54LS147, SN54LS148, SN74147, SN74148, SN74LS147, SN74LS148 :

Catalog: SN74147, SN74148, SN74LS147, SN74LS148

•

Military: SN54147, SN54148, SN54LS147, SN54LS148

•

NOTE: Qualified Version Definitions:

Catalog - TI's standard catalog product

•

Military - QML certified for Military and Defense Applications

•

Addendum-Page 3

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LS148DR

SOIC

2500

330.0

16.4

6.5

10.3

2.1

8.0

16.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

8-Apr-2013

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SOIC 16

SPQ

Length (mm) Width (mm) Height (mm)

333.2 345.9 28.6

SN74LS148DR

2500

Pack Materials-Page 2

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SN74LS147N-00 [TI]

相关型号：

SN74LS147N-10

SN74LS147N1

SN74LS147N3

SN74LS147ND

SN74LS147NDS

SN74LS147NP1

SN74LS147NP1

SN74LS147NP3

SN74LS147NS

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SN74LS148D

SN74LS148D