SN74LS17 [TI]
HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS; HEX缓冲器/带集电极开路高压输出驱动程序
| 型号： | SN74LS17 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS |
| 文件： | 总11页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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The SN54LS07 and SN74LS17 are
obsolete and are no longer supplied.
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SDLS021C − MAY 1990 − REVISED FEBRUARY 2004
SN54LS07 . . . J PACKAGE
SN74LS07, SN74LS17 . . . D, DB, N, OR NS PACKAGE
(TOP VIEW)
D
D
D
D
Convert TTL Voltage Levels to MOS Levels
High Sink-Current Capability
Input Clamping Diodes Simplify System
Design
1A
1Y
2A
2Y
3A
1
2
3
4
5
6
7
14
V
CC
13 6A
12 6Y
11 5A
10 5Y
Open-Collector Driver for Indicator Lamps
and Relays
description/ordering information
3Y
GND
9
8
4A
4Y
These hex buffers/drivers feature high-voltage
open-collector outputs to interface with high-level
circuits or for driving high-current loads. They are
also characterized for use as buffers for driving TTL inputs. The ’LS07 devices have a rated output voltage of
30 V, and the SN74LS17 has a rated output voltage of 15 V. The maximum sink current is 30 mA for the
SN54LS07 and 40 mA for the SN74LS07 and SN74LS17.
These circuits are compatible with most TTL families. Inputs are diode-clamped to minimize transmission-line
effects, which simplifies design. Typical power dissipation is 140 mW, and average propagation delay time is
12 ns.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP − N
Tube
SN74LS07N
SN74LS07N
Tube
SN74LS07D
SOIC − D
SOP − NS
LS07
Tape and reel
Tape and reel
SN74LS07DR
SN74LS07NSR
SN74LS07DBR
0°C to 70°C
74LS07
LS07
SSOP − DB Tape and reel
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB
design guidelines are available at www.ti.com/sc/package.
logic diagram (positive logic)
2
4
1
3
1A
2A
3A
4A
5A
6A
1Y
2Y
3Y
4Y
5Y
6Y
6
5
9
8
10
12
11
13
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
ꢖ ꢝ ꢨ ꢠ ꢟꢫ ꢦꢥ ꢣꢤ ꢥꢟ ꢡꢨ ꢪꢜ ꢢꢝ ꢣ ꢣꢟ ꢲꢒ ꢄꢘ ꢗꢏ ꢎ ꢘꢳꢴꢂ ꢳꢂꢇ ꢢꢪꢪ ꢨꢢ ꢠ ꢢ ꢡꢧ ꢣꢧꢠ ꢤ ꢢ ꢠ ꢧ ꢣꢧ ꢤꢣꢧ ꢫ
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ꢦ ꢝꢪ ꢧꢤꢤ ꢟ ꢣꢭꢧ ꢠ ꢯꢜ ꢤꢧ ꢝ ꢟꢣꢧ ꢫꢬ ꢖ ꢝ ꢢꢪ ꢪ ꢟ ꢣꢭꢧ ꢠ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢤ ꢇ ꢨꢠ ꢟ ꢫꢦꢥ ꢣꢜꢟ ꢝ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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The SN54LS07 and SN74LS17 are
obsolete and are no longer supplied.
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SDLS021C − MAY 1990 − REVISED FEBRUARY 2004
schematic (each gate)
V
CC
1 kΩ
9 kΩ
5 kΩ
Output
Input
2 kΩ
2 kΩ
GND
Resistor values shown are nominal.
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
CC
Input voltage, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
I
Output voltage, V (see Notes 1 and 2): SN54LS07, SN74LS07 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V
O
SN74LS17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
Storage temperature range,T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltage values are with respect to GND.
2. This is the maximum voltage that should be applied to any output when it is in the off state.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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The SN54LS07 and SN74LS17 are
obsolete and are no longer supplied.
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SDLS021C − MAY 1990 − REVISED FEBRUARY 2004
recommended operating conditions (see Note 4)
SN74LS07
SN74LS17
SN54LS07
MIN NOM
UNIT
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.75
2
5
5.25
V
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
0.8
30
0.8
30
15
40
70
’LS07
SN74LS17
V
OH
High-level output voltage
V
I
Low-level output current
30
mA
OL
T
A
Operating free-air temperature
−55
125
0
°C
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN74LS07
SN54LS07
SN74LS17
‡
PARAMETER
UNIT
TEST CONDITIONS
MIN
MAX
−1.5
0.25
MIN
MAX
V
V
V
= MIN,
= MIN,
I = −12 mA
−1.5
0.25
0.25
0.4
0.7
1
V
IK
CC
I
’LS07, V
= 30 V
OH
I
V
IH
= 2 V
mA
OH
CC
SN74LS17, V
OH
= 15 V
I
= 16 mA
0.4
0.7
1
OL
OL
V
OL
V
CC
= MIN,
V
IL
= 0.8 V
V
§
I
= MAX
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
= MAX,
= MAX,
= MAX,
= MAX
= MAX
V = 7 V
mA
µA
I
I
V = 2.4 V
I
20
20
IH
V = 0.4 V
I
−0.2
14
−0.2
14
mA
mA
mA
IL
CCH
CCL
45
45
‡
§
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
= 30 mA for SN54 series parts and 40 mA for SN74 series parts.
I
OL
switching characteristics, V
= 5 V, T = 25°C (see Figure 1)
CC
A
FROM
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
MIN
TYP
MAX
UNIT
(INPUT)
t
t
6
10
30
PLH
A
Y
R
= 110 Ω,
C
= 15 pF
L
ns
L
19
PHL
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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The SN54LS07 and SN74LS17 are
obsolete and are no longer supplied.
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SDLS021C − MAY 1990 − REVISED FEBRUARY 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Test
Point
R
L
Test
Point
S1
V
CC
From Output
Under Test
V
CC
(see Note B)
R
L
C
L
(see Note A)
From Output
Under Test
5 kΩ
R
L
(see Note B)
From Output
Under Test
C
Test
Point
C
L
(see Note A)
L
(see Note A)
S2
LOAD CIRCUIT
LOAD CIRCUIT
LOAD CIRCUIT
FOR 2-STATE TOTEM-POLE OUTPUTS
FOR OPEN-COLLECTOR OUTPUTS
FOR 3-STATE OUTPUTS
3 V
High-Level
Timing
Input
1.3 V
1.3 V
1.3 V
1.3 V
Pulse
0 V
t
t
h
w
t
su
3 V
0 V
Low-Level
Pulse
Data
Input
1.3 V
1.3 V
1.3 V
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
Output
3 V
0 V
Control
(low-level
enabling)
1.3 V
1.3 V
3 V
0 V
Input
1.3 V
1.3 V
t
t
PLZ
PZL
t
t
PHL
PLH
Waveform 1
(see Notes C
and D)
≈1.5 V
In-Phase
Output
(see Note D)
1.3 V
V
V
OH
V
OL
+ 0.5 V
1.3 V
1.3 V
1.3 V
V
OL
t
PHZ
OL
t
PZH
t
t
PLH
PHL
V
OH
Waveform 2
(see Notes C
and D)
V
OH
− 0.5 V
Out-of-Phase
Output
(see Note D)
V
V
OH
1.3 V
1.3 V
≈1.5 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS
NOTES: A.
C
includes probe and jig capacitance.
L
B. All diodes are 1N3064 or equivalent.
C. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
D. S1 and S2 are closed for t
, t
, t
, and t
; S1 is open and S2 is closed for t
; S1 is closed and S2 is open for t .
PLH PHL PHZ
PLZ
PZH
PZL
E. Phase relationships between inputs and outputs have been chosen arbitrarily for these examples.
F. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z ≈ 50 Ω, t ≤ 1.5 ns, t ≤ 2.6 ns.
O
r
f
G. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuits and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
24-Apr-2006
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LS07D
ACTIVE
SOIC
D
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS07DBLE
SN74LS07DBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS07DBRE4
SN74LS07DBRG4
SN74LS07DE4
SN74LS07DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
SOIC
SOIC
SOIC
PDIP
PDIP
SO
DB
DB
D
14
14
14
14
14
14
14
14
14
14
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS07DRE4
SN74LS07N
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74LS07NE4
SN74LS07NSR
SN74LS07NSRE4
SN74LS07NSRG4
N
25
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
NS
NS
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LS17D
SN74LS17N
OBSOLETE
OBSOLETE
SOIC
PDIP
D
N
14
14
TBD
TBD
Call TI
Call TI
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
Addendum-Page 1
PACKAGE OPTION ADDENDUM
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24-Apr-2006
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Addendum-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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