SN74LV02ANSE4 [TI]
LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, SO-14;
| 型号： | SN74LV02ANSE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LV/LV-A/LVX/H SERIES, QUAD 2-INPUT NOR GATE, PDSO14, PLASTIC, SO-14 输入元件 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄꢅ ꢆꢇ
ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢇ ꢑꢒꢁ ꢏꢋꢓ ꢏꢔ ꢀꢒ ꢓ ꢒꢅꢐ ꢑꢁꢔꢎ ꢕ ꢌꢓꢐ ꢀ
SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996
SN54LV02 . . . J OR W PACKAGE
SN74LV02 . . . D, DB, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at V , T = 25°C
CC
A
1Y
1A
V
CC
1
2
3
4
5
6
7
14
13
12
11
Typical V
(Output V
Undershoot)
4Y
4B
4A
OHV
OH
> 2 V at V , T = 25°C
1B
CC
A
2Y
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
2A
10 3Y
9
8
2B
3B
3A
GND
D
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
SN54LV02 . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
and Ceramic Flat (W) Packages, Ceramic
Chip Carriers (FK), and Ceramic (J)
300-mil DIPs
3
2
1
20 19
18
4B
NC
4A
1B
NC
2Y
4
5
6
7
8
17
16
15 NC
14
9 10 11 12 13
NC
2A
description
3Y
These quadruple 2-input positive-NOR gates are
designed for 2.7-V to 5.5-V V operation.
CC
The ’LV02 perform Boolean function Y = A + B or
Y = A • B in positive logic.
NC − No internal connection
The SN74LV02 is available in TI’s shrink
small-outline package (DB), which provides the
same I/O pin count and functionality of standard
small-outline packages in less than half the
printed-circuit-board area.
The SN54LV02 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV02 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
L
L
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
ꢋ ꢁ ꢄꢐꢀꢀ ꢔ ꢓꢖ ꢐꢎꢗ ꢒꢀ ꢐ ꢁ ꢔꢓꢐꢍ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢏꢎ ꢔ ꢍ ꢋ ꢤꢓ ꢒꢔ ꢁ
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1
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢀꢁ ꢉ ꢃ ꢄꢅ ꢆ ꢇ
ꢎ
ꢊ
ꢋ
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ꢍ
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ꢐ
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SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996
†
logic symbol
logic diagram, each gate (positive logic)
2
A
B
≥ 1
1A
1B
2A
2B
3A
3B
4A
4B
Y
1
4
3
1Y
2Y
3Y
4Y
5
6
8
10
13
9
11
12
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for the D, DB, J, PW, and W packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Maximum power dissipation at T = 55°C (in still air) (see Note 3): D package . . . . . . . . . . . . . . . . . . . 1.25 W
A
DB or PW package . . . . . . . . . . . . . 0.5 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄꢅ ꢆꢇ
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SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV02
SN74LV02
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
High-level input voltage
V
V
IH
3.15
3.15
0.8
0.8
V
IL
Low-level input voltage
1.65
1.65
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
−6
V
CC
−6
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
I
High-level output current
Low-level output current
mA
mA
OH
−12
6
−12
6
I
OL
12
12
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
100
125
0
100
85
ns/V
T
A
−55
−40
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV02
TYP
SN74LV02
TYP
†
PARAMETER
TEST CONDITIONS
= −100 µA
V
CC
UNIT
MIN
MAX
MIN
MAX
I
I
I
I
I
I
MIN to MAX
3 V
V
− 0.2
V
− 0.2
OH
OH
OH
OL
OL
OL
CC
2.4
3.6
CC
2.4
3.6
= −6 mA
= −12 mA
= 100 µA
= 6 mA
V
OH
V
4.5 V
MIN to MAX
3 V
0.2
0.4
0.55
1
0.2
0.4
0.55
1
V
OL
V
= 12 mA
4.5 V
3.6 V
I
I
V = V
or GND
or GND,
µA
I
I
CC
5.5 V
1
1
3.6 V
20
20
V = V
I = 0
O
µA
µA
CC
I
CC
5.5 V
20
20
One input at V
CC
− 0.6 V,
or GND
nI
CC
3 V to 3.6 V
500
500
Other inputs at V
CC
3.3 V
5 V
2.5
2.5
2.5
2.5
C
V = V
I CC
or GND
pF
i
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LV02
FROM
(INPUT)
TO
(OUTPUT)
V
CC
MIN
= 5 V 0.5 V
V
CC
MIN
= 3.3 V 0.3 V
V
CC
MIN
= 2.7 V
MAX
16
PARAMETER
UNIT
TYP
MAX
10
TYP
MAX
13
t
pd
A
Y
5
8
ns
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ꢜꢡ ꢛ ꢚ ꢮꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢯ ꢡ ꢩꢝ ꢧꢠꢡ ꢢꢘꢪ ꢤ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
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ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈ ꢀꢁ ꢉ ꢃ ꢄꢅ ꢆ ꢇ
ꢊꢋ ꢌꢍ ꢎ ꢋꢏ ꢄ ꢐ ꢇ ꢑꢒ ꢁꢏ ꢋꢓ ꢏ ꢔꢀ ꢒ ꢓꢒ ꢅ ꢐꢑ ꢁꢔ ꢎ ꢕ ꢌꢓ ꢐꢀ
SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN74LV02
FROM
(INPUT)
TO
(OUTPUT)
V
CC
MIN
= 5 V 0.5 V
V
CC
MIN
= 3.3 V 0.3 V
V
CC
MIN
= 2.7 V
MAX
16
PARAMETER
UNIT
TYP
MAX
10
TYP
MAX
13
t
pd
A
Y
5
8
ns
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
V
TYP
16
UNIT
CC
3.3 V
C
Power dissipation capacitance per gate
C
= 50 pF, f = 10 MHz
pF
pd
L
5 V
20
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢀ ꢁꢉ ꢃꢄꢅ ꢆꢇ
ꢊ ꢋꢌꢍꢎ ꢋꢏꢄ ꢐ ꢇ ꢑꢒꢁ ꢏꢋꢓ ꢏꢔ ꢀꢒ ꢓ ꢒꢅꢐ ꢑꢁꢔꢎ ꢕ ꢌꢓꢐ ꢀ
SCLS183B − FEBRUARY 1993 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
V
z
TEST
S1
S1
Open
1 kΩ
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
t
V
z
GND
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
1 kΩ
(see Note A)
WAVEFORM
CONDITION
V
= 4.5 V
V
= 2.7 V
CC
to 5.5 V
CC
to 3.6 V
1.5 V
2.7 V
6 V
V
m
0.5 × V
CC
V
i
V
z
V
CC
LOAD CIRCUIT
2 × V
CC
V
i
V
m
Timing Input
0 V
t
w
t
t
su
h
V
i
V
i
V
m
V
m
Input
V
m
V
m
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
i
i
Output
Control
V
V
m
m
Input
V
m
V
m
0 V
0 V
V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
0.5 × V
z
OH
V
V
V
m
V
m
m
Output
Output
V
+ 0.3 V
− 0.3 V
S1 at V
(see Note B)
OL
z
V
OL
V
OL
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
V
V
m
m
m
[ 0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. includes probe and jig capacitance.
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
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POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
Samples Not Available
Samples Not Available
Samples Not Available
Samples Not Available
Samples Not Available
SN74LV02D
SN74LV02DBLE
SN74LV02DR
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
SOIC
SSOP
SOIC
D
14
14
14
14
14
TBD
TBD
TBD
TBD
TBD
Call TI
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DB
D
SN74LV02PWLE
SN74LV02PWR
TSSOP
TSSOP
PW
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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Addendum-Page 1
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