SN74LV123ADBRE4 [TI]
DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS; 施密特触发器输入双可再触发单稳态触发器
| 型号： | SN74LV123ADBRE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL RETRIGGERABLE MONOSTABLE MULTIVIBRATORS WITH SCHMITT-TRIGGER INPUTS |
| 文件： | 总23页 (文件大小：531K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
D
D
D
D
D
D
D
2-V to 5.5-V V
Operation
D
D
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 11 ns at 5 V
pd
Retriggerable for Very Long Output Pulses,
up to 100% Duty Cycle
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
− 1000-V Charged-Device Model (C101)
SN74LV123A . . . RGY PACKAGE
(TOP VIEW)
SN54LV123A . . . FK PACKAGE
(TOP VIEW)
SN54LV123A . . . J OR W PACKAGE
SN74LV123A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
1
16
1A
1B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
15
14
13
12
11
10
1B
1CLR
1Q
2
3
4
5
6
7
1R /C
1R /C
ext ext
ext ext
1C
1Q
2Q
3
2
1 20 19
18
ext
1CLR
1Q
1C
1Q
ext
1C
1Q
1CLR
1Q
4
5
6
7
8
ext
17
16
2Q
2Q
12 2Q
NC
NC
2C
2CLR
2B
ext
11
10
9
2C
2CLR
2B
ext
15 2Q
2Q
2R /C
ext ext
2R /C
ext ext
GND
14
9 10 11 12 13
2CLR
2C
ext
8
9
2A
NC − No internal connection
description/ordering information
The ’LV123A devices are dual retriggerable monostable multivibrators designed for 2-V to 5.5-V V
operation.
CC
These edge-triggered multivibrators feature output pulse-duration control by three methods. In the first method,
the A input is low and the B input goes high. In the second method, the B input is high and the A input goes low.
In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C
and R /C
(positive) and an external resistor
ext
ext ext
connected between R /C
resistance between R /C and V . The output pulse duration also can be reduced by taking CLR low.
and V . To obtain variable pulse durations, connect an external variable
ext ext
CC
ext ext
CC
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒ ꢏ ꢎꢉꢓ ꢄꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎꢀ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢙꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢚ ꢍꢐ ꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
description/ordering information (continued)
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
Pin assignments for these devices are identical to those of the ’AHC123A and ’AHCT123A devices for
interchangeability, when allowed.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
QFN − RGY
SOIC − D
Reel of 1000
Tube of 40
SN74LV123ARGYR
SN74LV123AD
LV123A
LV123A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV123ADR
SN74LV123ANSR
SN74LV123ADBR
SN74LV123APW
SN74LV123APWR
SN74LV123APWT
SN74LV123ADGVR
SNJ54LV123AJ
SOP − NS
74LV123A
LV123A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV123A
TVSOP − DGV
CDIP − J
LV123A
SNJ54LV123AJ
SNJ54LV123AW
SNJ54LV123AFK
CFP − W
Tube of 150
Tube of 55
SNJ54LV123AW
SNJ54LV123AFK
−55°C to 125°C
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
CLR
L
A
X
H
X
L
B
X
X
L
Q
Q
L
H
‡
L
‡
X
H
H
‡
L
‡
X
H
↑
H
↓
L
H
H
↑
‡
These outputs are based on the
assumption that the indicated
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
logic diagram, each multivibrator (positive logic)
R
C
/C
ext ext
A
B
ext
Q
Q
CLR
R
input/output timing diagram
t
rr
A
B
CLR
R
/C
ext ext
Q
Q
t
t
t
+ t
w
w
w
rr
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
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SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range in high or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Output voltage range in power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢌꢍꢉ ꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎꢀ
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢙꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢚ ꢍ ꢐꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
recommended operating conditions (see Note 5)
SN54LV123A
SN74LV123A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
V
V
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
V
V
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−6
−12
50
2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
OH
OL
mA
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
Low-level output current
External timing resistance
6
6
mA
12
12
5k
1k
5k
1k
R
C
Ω
ext
ext
≥ 3 V
External timing capacitance
Power-up ramp rate
No restriction
1
No restriction
1
pF
ms/V
°C
∆t/∆V
CC
T
Operating free-air temperature
−55
125
−40
85
A
NOTE 5: Unused R /C
terminals should be left unconnected. All remaining unused inputs of the device must be held at V
or GND to ensure
proper device operation. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
ext ext
CC
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ꢡ ꢜꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
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5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒ ꢏ ꢎꢉꢓ ꢄꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎꢀ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢙꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢚ ꢍꢐ ꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV123A
SN74LV123A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
−0.1
2
TYP
MAX
MIN
−0.1
2
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
3 V
V
CC
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
V
V
OH
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
3 V
0.1
0.4
0.44
0.55
2.5
1
0.1
0.4
0.44
0.55
2.5
1
V
V
OL
= 6 mA
= 12 mA
4.5 V
2 V to 5.5 V
0
†
V = 5.5 V or GND
I
R
/C
ext ext
I
I
µA
µA
I
V = 5.5 V or GND
I
A, B, and CLR
Quiescent
0 to 5.5 V
5.5 V
2.3 V
3 V
1
1
V = V
or GND,
I = 0
O
20
20
CC
I
CC
220
280
650
975
220
280
650
975
5
Active state
(per circuit)
V = V
/C
ext ext
or GND,
= 0.5 V
I
CC
I
µA
CC
off
R
4.5 V
5.5 V
0
CC
I
V or V = 0 to 5.5 V
µA
I
O
3.3 V
5 V
1.9
1.9
1.9
1.9
C
V = V
or GND
pF
i
I
CC
†
This test is performed with the terminal in the off-state condition.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
A
= 25°C
SN54LV123A SN74LV123A
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CLR
6
6.5
6.5
Pulse
duration
t
t
ns
w
A or B trigger
6
‡
6.5
‡
6.5
‡
C
C
= 100 pF
94
2
ns
ext
ext
Pulse retrigger time
R
= 1 kΩ
rr
ext
‡
‡
‡
= 0.01 mF
ms
‡
See retriggering data in the application information section.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
A
= 25°C
SN54LV123A SN74LV123A
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CLR
5
5
5
Pulse
duration
t
t
ns
w
A or B trigger
5
‡
5
‡
5
‡
C
C
= 100 pF
76
ns
ext
ext
Pulse retrigger time
R
= 1 kΩ
rr
ext
‡
‡
‡
= 0.01 mF
1.8
ms
‡
See retriggering data in the application information section.
ꢚ
ꢎ
ꢕ
ꢌ
ꢍ
ꢘ
ꢐ
ꢚ
ꢎ
ꢏ
ꢅ
ꢑ
ꢏ
ꢖ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢟ ꢤ ꢞ ꢝ ꢰ ꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢱ ꢤ ꢫ ꢠꢩ ꢣꢤ ꢥ ꢛꢬ ꢘ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢱ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢰ
ꢥ
ꢰ
ꢠ
ꢦ
ꢫ
ꢞ
ꢬ
ꢐ
ꢤ
ꢭ
ꢦ
ꢞ
ꢑ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢡ ꢜ ꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢱ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢌꢍꢉ ꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎꢀ
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢙꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢚ ꢍ ꢐꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
A
= 25°C
SN54LV123A SN74LV123A
TEST CONDITIONS
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
CLR
5
5
5
Pulse
duration
t
t
ns
w
A or B trigger
5
†
5
†
5
†
C
C
= 100 pF
59
ns
ext
ext
Pulse retrigger time
R
= 1 kΩ
rr
ext
†
†
†
= 0.01 mF
1.5
ms
†
See retriggering data in the application information section.
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54LV123A SN74LV123A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
14.5* 31.4*
13* 25*
15.1* 33.4*
1*
37*
1
37
A or B
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
1* 29.5*
1
1
1
1
1
29.5
39
t
C
C
= 15 pF
ns
CLR
CLR trigger
A or B
pd
L
1*
1
39*
42
16.6
14.7
17.4
36
32.8
38
42
1
34.5
44
34.5
44
t
pd
= 50 pF
= 50 pF,
= 28 pF,
= 2 kΩ
ns
CLR
L
1
CLR trigger
C
L
C
R
197
100
260
110
1.1
320
110
1.1
320
110
1.1
ns
ext
ext
C
= 50 pF,
= 0.01 µF,
= 10 kΩ
L
‡
t
C
90
90
90
ms
Q or Q
ext
w
R
ext
C
= 50 pF,
= 0.1 µF,
= 10 kΩ
L
C
R
0.9
1
1
0.9
0.9
ms
%
ext
ext
§
∆t
C
= 50 pF
L
w
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
‡
§
t
= Duration of pulse at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
ꢚ
ꢎ
ꢕ
ꢌ
ꢍ
ꢘ
ꢐ
ꢚ
ꢎ
ꢏ
ꢅ
ꢑ
ꢏ
ꢖ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢟꢤ ꢞ ꢝ ꢰꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢱ ꢤ ꢫꢠ ꢩꢣꢤ ꢥꢛꢬ ꢘ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢡ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢱ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢰ
ꢥ
ꢰ
ꢠ
ꢦ
ꢫ
ꢞ
ꢬ
ꢐ
ꢤ
ꢭ
ꢦ
ꢞ
ꢑ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢡ ꢜꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠꢟ ꢢꢡꢛ ꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢱ
ꢤ
ꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒ ꢏ ꢎꢉꢓ ꢄꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎꢀ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢙꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢚ ꢍꢐ ꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54LV123A
SN74LV123A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
MIN
TYP
MAX
MIN
MAX
MIN
MAX
10.2* 20.6*
9.3* 15.8*
10.6* 22.4*
1*
24*
1
24
A or B
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
1* 18.5*
1
1
1
1
1
18.5
26
t
C
C
= 15 pF
ns
CLR
CLR trigger
A or B
pd
L
1*
1
26*
27.5
22
11.8
10.5
12.3
24.1
19.3
25.9
27.5
22
1
t
pd
= 50 pF
= 50 pF,
= 28 pF,
= 2 kΩ
ns
CLR
L
1
29.5
29.5
CLR trigger
C
L
C
R
182
100
240
110
1.1
300
110
1.1
300
110
1.1
ns
ext
ext
C
= 50 pF,
= 0.01 µF,
= 10 kΩ
L
†
t
C
90
90
90
ms
Q or Q
ext
w
R
ext
C
= 50 pF,
= 0.1 µF,
= 10 kΩ
L
C
R
0.9
1
1
0.9
0.9
ms
%
ext
ext
‡
∆t
C
= 50 pF
L
w
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
t
= Duration of pulse at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV123A
SN74LV123A
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
7.1*
12*
1*
14*
1
14
A or B
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
Q or Q
6.5*
9.4*
1*
1*
1
11*
15*
16
1
1
1
1
1
11
15
16
13
17
t
pd
C
C
= 15 pF
ns
CLR
CLR trigger
A or B
L
7.4* 12.9*
8.3
7.4
8.7
14
11.4
14.9
1
13
t
pd
= 50 pF
= 50 pF,
= 28 pF,
= 2 kΩ
ns
CLR
L
1
17
CLR trigger
C
L
C
R
167
100
200
110
1.1
240
110
1.1
240
110
1.1
ns
ext
ext
C
= 50 pF,
= 0.01 µF,
= 10 kΩ
L
†
t
C
90
90
90
ms
Q or Q
ext
w
R
ext
C
= 50 pF,
= 0.1 µF,
= 10 kΩ
L
C
R
0.9
1
1
0.9
0.9
ms
%
ext
ext
‡
∆t
w
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
†
‡
t
= Duration of pulse at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
ꢚ
ꢎ
ꢕ
ꢌ
ꢍ
ꢘ
ꢐ
ꢚ
ꢎ
ꢏ
ꢅ
ꢑ
ꢏ
ꢖ
ꢝ
ꢥ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢡ
ꢠ
ꢥ
ꢡ
ꢤ
ꢨ
ꢥ
ꢞ
ꢩ
ꢨ
ꢠ
ꢟ
ꢢ
ꢡ
ꢟ ꢤ ꢞ ꢝ ꢰ ꢥ ꢩꢜ ꢦ ꢞ ꢤ ꢠꢧ ꢟꢤ ꢱ ꢤ ꢫ ꢠꢩ ꢣꢤ ꢥ ꢛꢬ ꢘ ꢜꢦ ꢨꢦ ꢡꢛ ꢤꢨ ꢝꢞ ꢛꢝ ꢡ ꢟꢦ ꢛꢦ ꢦꢥ ꢟ ꢠꢛ ꢜꢤꢨ
ꢛ
ꢞ
ꢝ
ꢥ
ꢛ
ꢜ
ꢤ
ꢧ
ꢠ
ꢨ
ꢣ
ꢦ
ꢛ
ꢝ
ꢱ
ꢤ
ꢠ
ꢨ
ꢞ
ꢩ
ꢤ
ꢡ
ꢝ
ꢧ
ꢝ
ꢡ
ꢦ
ꢛ
ꢝ
ꢠ
ꢥ
ꢞ
ꢦ
ꢨ
ꢤ
ꢟ
ꢤ
ꢞ
ꢝ
ꢰ
ꢥ
ꢰ
ꢠ
ꢦ
ꢫ
ꢞ
ꢬ
ꢐ
ꢤ
ꢭ
ꢦ
ꢞ
ꢑ
ꢥ
ꢞ
ꢛ
ꢨ
ꢢ
ꢣ
ꢤ
ꢥ
ꢡ ꢜ ꢦ ꢥ ꢰꢤ ꢠꢨ ꢟꢝ ꢞ ꢡ ꢠꢥ ꢛꢝ ꢥꢢ ꢤ ꢛ ꢜꢤ ꢞ ꢤ ꢩꢨ ꢠ ꢟꢢꢡ ꢛꢞ ꢮ ꢝꢛꢜ ꢠꢢꢛ ꢥꢠꢛ ꢝꢡꢤ ꢬ
ꢛ
ꢞ
ꢨ
ꢤ
ꢞ
ꢤ
ꢨ
ꢱ
ꢤꢞ
ꢛ
ꢜ
ꢤ
ꢨ
ꢝ
ꢰ
ꢜ
ꢛ
ꢛ
ꢠ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢌꢍꢉ ꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎꢀ
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢙꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢚ ꢍ ꢐꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
44
UNIT
CC
3.3 V
5 V
C
Power dissipation capacitance
C
pF
pd
49
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
t
w
V
CC
C
L
Inputs or
Outputs
(see Note A)
50% V
CC
50% V
CC
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Input A
(see Note B)
50% V
CC
0 V
V
V
CC
Input CLR
(see Note B)
50% V
CC
50% V
CC
CC
Input B
0 V
50% V
(see Note B)
CC
t
t
t
0 V
PLH
PHL
t
t
V
PLH
OH
In-Phase
Output
V
V
OH
50% V
50% V
CC
CC
V
In-Phase
Output
50% V
CC
OL
OL
t
PHL
PLH
PHL
V
V
V
OH
OH
Out-of-Phase
Output
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
V
OL
OL
VOLTAGE WAVEFORMS
DELAY TIMES
VOLTAGE WAVEFORMS
DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t + 3 ns, t + 3 ns.
O
r
f
C. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒ ꢏ ꢎꢉꢓ ꢄꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎꢀ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢙꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢚ ꢍꢐ ꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
†
APPLICATION INFORMATION
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
1.00E+07
1.00E+06
1.00E+07
1.00E+06
V
T
A
= 3 V
V
= 4.5 V
CC
= 25°C
CC
T = 25°C
A
R
= 1 MΩ
R
= 1 MΩ
T
T
1.00E+05
1.00E+04
1.00E+05
1.00E+04
R
= 100 kΩ
R
= 100 kΩ
T
T
T
T
R
= 10 kΩ
= 1 kΩ
R
= 10 kΩ
= 1 kΩ
1.00E+03
1.00E+02
1.00E+03
1.00E+02
R
R
T
T
1
2
10
3
10
4
10
5
10
1
2
10
3
10
4
10
5
10
10
10
C
− External Timing Capacitance − pF
C
− External Timing Capacitance − pF
T
T
Figure 2
Figure 3
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
10
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢌꢍꢉ ꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎꢀ
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢙꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢚ ꢍ ꢐꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
†
APPLICATION INFORMATION
1.00E+09
V
T
A
= 5 V
CC
= 25°C
1.00E+08
1.00E+07
R
= 200k Ω
T
R
= 150k Ω
T
1.00E+06
1.00E+05
1.00E+04
1.00E+03
1.00E+02
1.00E+01
1.00E+00
R
= 80k Ω
R
= 10k Ω
T
T
R
= 5k Ω
T
R
= 1k Ω
T
2
10
3
10
4
10
5
10
6
10
7
10
1
10
C
− External Timing Capacitance − pF
T
Figure 4. Output Pulse Duration vs External Timing Capacitance
14%
t
= 866 ns at:
= 5 V
= 10 kΩ
= 50 pF
= 25°C
w
CC
T
T
A
V
R
C
12%
10%
V
CC
= 2.5 V
V
V
= 3 V
CC
CC
T
= 3.5 V
8%
6%
4%
2%
V
CC
V
CC
V
CC
V
CC
= 4 V
= 5 V
= 6 V
= 7 V
0%
−2%
−4%
−6%
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
Temperature − °C
Figure 5. Variations in Output Pulse Duration vs Temperature
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
11
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒ ꢏ ꢎꢉꢓ ꢄꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎꢀ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢙꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢚ ꢍꢐ ꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
†
APPLICATION INFORMATION
OUTPUT PULSE-DURATION CONSTANT
MINIMUM TRIGGER TIME
vs
vs
SUPPLY VOLTAGE
V
CHARACTERISTICS
CC
10.00
1.00
0.10
1.20
1.15
R
T
= 10 kΩ
= 25°C
R
T
= 1 kΩ
= 25°C
T
A
T
A
t
= K × C × R
W
T T
C
= 0.01 µF
T
1.10
1.05
1.00
C
= 1000 pF
T
C
= 1000 pF
T
C
= 0.01 µF
T
C
= 100 pF
T
0.95
0.90
C
= 0.1 µF
T
0.01
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
0
1
2
3
4
5
6
V
CC
− Supply Voltage − V
V
CC
− Supply Voltage − V
Figure 7
Figure 6
DISTRIBUTION OF UNITS
vs
OUTPUT PULSE DURATION
EXTERNAL CAPACITANCE
vs
V
= 5 V
MULTIPLIER FACTOR
CC
T
= 25°C
= 50 pF
= 10 kW
0.001
A
For Capacitor Values of
0.001 µF or Greater,
K = 1.0
C
R
T
T
(K is Independent of R)
Mean = 856 ns
Median = 856 ns
Std. Dev. = 3.5 ns
0.0001
T
V
= 25°C
A
= 5 V
CC
−3 Std. Dev.
+3 Std. Dev.
0.00001
Median
1.00 1.50 2.00 2.50 3.00 3.50 4.00 4.50
Multiplier Factor − K
99% of Data Units
t
− Output Pulse Duration
w
Figure 8
Figure 9
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
12
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢌꢍꢉ ꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎꢀ
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢙꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢚ ꢍ ꢐꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
APPLICATION INFORMATION
caution in use
To prevent malfunctions due to noise, connect a high-frequency capacitor between V
and GND, and keep
CC
the wiring between the external components and C and R /C terminals as short as possible.
ext
ext ext
power-down considerations
Large values of C can cause problems when powering down the ’LV123A devices because of the amount
ext
of energy stored in the capacitor. When a system containing this device is powered down, the capacitor can
discharge from V
must be limited to 30 mA; therefore, the turn-off time of the V
through the protection diodes at pin 2 or pin 14. Current through the input protection diodes
CC
power supply must not be faster than
CC
t = V
× C /30 mA. For example, if V
= 5 V and C = 15 pF, the V
supply must turn off no faster than
CC
ext
CC
ext
CC
t = (5 V) × (15 pF)/30 mA = 2.5 ns. Usually, this is not a problem because power supplies are heavily filtered
and cannot discharge at this rate. When a more rapid decrease of V to zero occurs, the ’LV123A devices can
CC
sustain damage. To avoid this possibility, use external clamping diodes.
output pulse duration
The output pulse duration, t , is determined primarily by the values of the external capacitance (C ) and timing
w
T
resistance (R ). The timing components are connected as shown in Figure 10.
T
V
CC
R
T
C
T
To R /C
ext ext
Terminal
To C
ext
Terminal
Figure 10. Timing-Component Connections
The pulse duration is given by:
tw + K RT CT
(1)
if C is ≥1000 pF, K = 1.0 or
T
if C is <1000 pF, K can be determined from Figure 8
T
where:
t
= pulse duration in ns
w
R
C
K
= external timing resistance in kΩ
= external capacitance in pF
= multiplier factor
T
T
Equation 1 and Figure 3 can be used to determine values for pulse duration, external resistance, and external
capacitance.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒ ꢏ ꢎꢉꢓ ꢄꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎꢀ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢙꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢚ ꢍꢐ ꢀ
SCLS393O − APRIL 1998 − REVISED OCTOBER 2005
APPLICATION INFORMATION
retriggering data
The minimum input retriggering time (t
) is the minimum time required after the initial signal before retriggering
MIR
the input. After t
, the device retriggers the output. Experimentally, it also can be shown that to retrigger the
MIR
output pulse, the two adjacent input signals should be t
duration is calculated as shown in Figure 11.
apart, where t
= 0.30 × t . The retrigger pulse
MIR
MIR w
t
MIR
Input
t
= t + t
w PLH
= (K × R × C ) + t
PLH
RT
T
T
Where:
t
t
RT
PLH
t
t
t
t
= Minimum Input Retriggering Time
= Propagation Delay
= Retrigger Time
t
MIR
PLH
RT
w
Output
= Output Pulse Duration Before Retriggering
w
Figure 11. Retrigger Pulse Duration
The minimum value from the end of the input pulse to the beginning of the retriggered output should be
approximately 15 ns to ensure a retriggered output (see Figure 12).
Input
t
MRT
Output
t
t
= Minimum Time Between the End of the Second Input Pulse and the Beginning of the Retriggered Output
= 15 ns
MRT
MRT
Figure 12. Input/Output Requirements
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV123AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV123ADBR
SN74LV123ADBRE4
SN74LV123ADE4
SSOP
SSOP
SOIC
DB
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV123ADGVR
SN74LV123ADGVRE4
SN74LV123ADR
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV123ADRE4
SN74LV123ANSR
SN74LV123ANSRE4
SN74LV123APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
PW
PW
PW
PW
PW
RGY
RGY
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV123APWE4
SN74LV123APWG4
SN74LV123APWR
SN74LV123APWRE4
SN74LV123APWRG4
SN74LV123APWT
SN74LV123APWTE4
SN74LV123APWTG4
SN74LV123ARGYR
SN74LV123ARGYRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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