SN74LV123ATPWRG4Q1 [TI]
汽车类双路可再触发单稳多谐振荡器 | PW | 16 | -40 to 125;
| 型号： | SN74LV123ATPWRG4Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类双路可再触发单稳多谐振荡器 | PW | 16 | -40 to 125 时钟 输入元件 光电二极管 逻辑集成电路 触发器 振荡器 |
| 文件： | 总10页 (文件大小：164K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢊꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢙ ꢍ ꢐꢀ
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
PW PACKAGE
(TOP VIEW)
D
Qualification in Accordance With
AEC-Q100
†
D
Qualified for Automotive Applications
1A
1B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
1R /C
ext ext
1CLR
1Q
1C
1Q
ext
2Q
12 2Q
D
D
D
D
D
D
D
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
11
10
9
2C
ext
2CLR
2B
= 3.3 V, T = 25°C
A
2R /C
ext ext
GND
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
2A
= 3.3 V, T = 25°C
A
Supports Mixed-Mode Voltage Operation on
All Ports
Schmitt-Trigger Circuitry on A, B, and CLR
Inputs for Slow Input Transition Rates
Edge Triggered From Active-High or
Active-Low Gated Logic Inputs
I
Supports Partial-Power-Down Mode
off
Operation
Retriggerable for Very Long Output Pulses,
Up To 100% Duty Cycle
D
D
D
Overriding Clear Terminates Output Pulse
Glitch-Free Power-Up Reset on Outputs
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
†
Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74LV123A is a dual retriggerable monostable multivibrator designed for 2-V to 5.5-V V
operation.
CC
This edge-triggered multivibrator features output pulse-duration control by three methods. In the first method,
the A input is low, and the B input goes high. In the second method, the B input is high, and the A input goes
low. In the third method, the A input is low, the B input is high, and the clear (CLR) input goes high.
The output pulse duration is programmable by selecting external resistance and capacitance values. The
external timing capacitor must be connected between C
and R /C
(positive) and an external resistor
ext
ext ext
connected between R /C
resistance between R /C and V . The output pulse duration also can be reduced by taking CLR low.
and V . To obtain variable pulse durations, connect an external variable
ext ext
CC
ext ext
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
T
PACKAGE
TSSOP − PW
A
−40°C to 105°C
Tape and reel SN74LV123ATPWRQ1 L123ATQ
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
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ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢊꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢙ ꢍꢐ ꢀ
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
description/ordering information (continued)
Pulse triggering occurs at a particular voltage level and is not directly related to the transition time of the input
pulse. The A, B, and CLR inputs have Schmitt triggers with sufficient hysteresis to handle slow input transition
rates with jitter-free triggering at the outputs.
Once triggered, the basic pulse duration can be extended by retriggering the gated low-level-active (A) or
high-level-active (B) input. Pulse duration can be reduced by taking CLR low. The input/output timing diagram
illustrates pulse control by retriggering the inputs and early clearing.
During power up, Q outputs are in the low state, and Q outputs are in the high state. The outputs are glitch free,
without applying a reset pulse.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(each multivibrator)
INPUTS
OUTPUTS
CLR
L
A
X
H
X
L
B
X
X
L
Q
Q
L
H
†
†
X
L
L
H
H
†
†
X
H
↑
H
↓
L
H
H
↑
†
These outputs are based on the
assumption that the indicated
steady-state conditions at the A and
B inputs have been set up long enough to
complete any pulse started before the
setup.
logic diagram, each multivibrator (positive logic)
R
C
/C
ext ext
A
B
ext
Q
Q
CLR
R
2
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SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
input/output timing diagram
t
rr
A
B
CLR
R
/C
ext ext
Q
Q
t
t
t
+ t
w
w
w
rr
†
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range in high or low state, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Output voltage range in power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
JA
stg
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
recommended operating conditions (see Note 4)
MIN
2
MAX
UNIT
V
Supply voltage
5.5
V
CC
IH
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
CC
CC
CC
V
High-level input voltage
V
V
× 0.7
× 0.7
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
5.5
V
V
Input voltage
0
0
V
V
I
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
OH
OL
mA
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
Low-level output current
External timing resistance
6
mA
12
5
1
R
C
kΩ
ext
ext
≥ 3 V
External timing capacitance
Power-up ramp rate
No restriction
1
pF
ms/V
°C
∆t/∆V
CC
T
Operating free-air temperature
−40
105
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
−0.1
2
TYP
MAX
UNIT
V
CC
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
3 V
V
CC
OH
OH
OH
OH
OL
OL
OL
OL
V
V
V
OH
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
3 V
0.1
0.4
0.44
0.55
2.5
1
V
OL
= 6 mA
= 12 mA
4.5 V
2 V to 5.5 V
0
†
V = 5.5 V or GND
I
R
/C
ext ext
I
I
µA
µA
µA
I
V = 5.5 V or GND
I
A, B, and CLR
Quiescent
0 to 5.5 V
5.5 V
3 V
1
V = V
or GND,
I = 0
O
20
CC
I
CC
280
650
975
5
Active state
(per circuit)
V = V
I
R
or GND,
CC
4.5 V
5.5 V
0
I
CC
off
/C
ext ext
= 0.5 V
CC
I
V or V = 0 to 5.5 V
µA
I
O
3.3 V
5 V
1.9
1.9
C
V = V
or GND
pF
i
I
CC
†
This test is performed with the terminal in the off-state condition.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
A
= 25°C
TEST CONDITIONS
MIN
MAX
UNIT
MIN
TYP
MAX
CLR
5
5
Pulse
duration
t
t
ns
w
A or B trigger
5
‡
5
‡
C
C
= 100 pF
76
ns
ext
ext
Pulse retrigger time
R
= 1 kΩ
rr
ext
‡
‡
= 0.01 µF
1.8
µs
‡
See retriggering data in the application information section.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
A
= 25°C
TEST CONDITIONS
MIN
MAX
UNIT
MIN
TYP
MAX
CLR
5
5
Pulse
duration
t
t
ns
w
A or B trigger
5
‡
5
‡
C
C
= 100 pF
59
ns
ext
ext
Pulse retrigger time
R
= 1 kΩ
rr
ext
‡
‡
= 0.01 µF
1.5
µs
‡
See retriggering data in the application information section.
5
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ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢊꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢙ ꢍꢐ ꢀ
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
MAX
UNIT
MIN
MAX
11.8
24.1
1
1
1
27.5
22
A or B
Q or Q
Q or Q
Q or Q
10.5
12.3
19.3
25.9
t
pd
C
= 50 pF
= 50 pF,
= 28 pF,
= 2 kΩ
ns
CLR
L
29.5
CLR trigger
C
L
C
R
182
100
240
110
1.1
300
110
1.1
ns
ext
ext
C
= 50 pF,
= 0.01 µF,
= 10 kΩ
L
†
C
90
90
µs
t
w
Q or Q
ext
R
ext
C
= 50 pF,
= 0.1 µF,
= 10 kΩ
L
C
R
0.9
1
1
0.9
ms
%
ext
ext
‡
∆t
w
C
= 50 pF
L
†
‡
t
= Duration of pulse at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
8.3
FROM
(INPUT)
TO
(OUTPUT)
TEST
CONDITIONS
PARAMETER
MIN
MAX
UNIT
MIN
MAX
14
1
1
1
16
13
17
A or B
Q or Q
Q or Q
Q or Q
7.4
8.7
11.4
14.9
t
C
= 50 pF
= 50 pF,
ns
CLR
pd
L
CLR trigger
C
L
C
R
= 28 pF,
167
100
200
110
1.1
240
110
1.1
ns
ext
= 2 kΩ
ext
C
= 50 pF,
= 0.01 µF,
L
†
C
90
90
µs
t
Q or Q
ext
R
w
= 10 kΩ
ext
C
= 50 pF,
L
C
R
= 0.1 µF,
= 10 kΩ
0.9
1
1
0.9
ms
%
ext
ext
‡
∆t
w
†
‡
t
= Duration of pulse at Q and Q outputs
w
∆t = Output pulse-duration variation (Q and Q) between circuits in same package
w
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
44
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
49
6
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ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢆ
ꢌ ꢍꢉꢄ ꢎꢏ ꢐꢎꢑ ꢒ ꢒꢏ ꢎꢉꢓꢄ ꢏ ꢔ ꢕꢁ ꢕꢀ ꢐꢉꢓꢄ ꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑ ꢓꢎ ꢉꢐꢕ ꢎ
ꢖ ꢑꢐ ꢗ ꢀꢘ ꢗꢔꢑ ꢐꢐꢊꢐ ꢎꢑꢒ ꢒ ꢏ ꢎ ꢑ ꢁꢙ ꢍ ꢐꢀ
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
Test
Point
t
w
V
CC
C
L
Inputs or
Outputs
(see Note A)
50% V
50% V
CC
CC
0 V
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PULSE DURATION
V
CC
Input A
(see Note B)
50% V
CC
0 V
V
V
CC
Input CLR
(see Note B)
50% V
CC
50% V
CC
CC
Input B
0 V
50% V
(see Note B)
CC
t
t
t
0 V
PLH
PHL
t
t
V
PLH
OH
In-Phase
Output
V
V
OH
50% V
50% V
CC
CC
V
In-Phase
Output
50% V
CC
OL
OL
t
PHL
PLH
PHL
V
V
V
OH
OH
Out-of-Phase
Output
Out-of-Phase
Output
50% V
50% V
50% V
CC
CC
CC
V
OL
OL
VOLTAGE WAVEFORMS
DELAY TIMES
VOLTAGE WAVEFORMS
DELAY TIMES
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t + 3 ns, t + 3 ns.
O
r
f
C. The outputs are measured one at a time, with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊꢋꢆ
ꢌ ꢍꢉꢄ ꢎ ꢏꢐ ꢎ ꢑꢒꢒꢏ ꢎꢉ ꢓꢄ ꢏ ꢔꢕ ꢁꢕ ꢀꢐꢉꢓ ꢄꢏ ꢔ ꢍꢄꢐ ꢑꢅ ꢑꢓꢎꢉꢐꢕ ꢎ
ꢖꢑ ꢐ ꢗ ꢀꢘ ꢗ ꢔꢑ ꢐ ꢐꢊꢐ ꢎꢑ ꢒ ꢒꢏ ꢎ ꢑ ꢁꢙ ꢍꢐ ꢀ
SCLS467B − FEBRUARY 2003 − REVISED MAY 2004
†
APPLICATION INFORMATION
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
OUTPUT PULSE DURATION
vs
EXTERNAL TIMING CAPACITANCE
1.00E+07
1.00E+06
1.00E+07
1.00E+06
V
T
A
= 3 V
V
= 4.5 V
CC
= 25°C
CC
T = 25°C
A
R
= 1 MΩ
R
= 1 MΩ
T
T
1.00E+05
1.00E+04
1.00E+05
1.00E+04
R
= 100 kΩ
R
= 100 kΩ
T
T
T
T
R
= 10 kΩ
= 1 kΩ
R
= 10 kΩ
= 1 kΩ
1.00E+03
1.00E+02
1.00E+03
1.00E+02
R
R
T
T
1
2
10
3
10
4
10
5
10
1
2
10
3
10
4
10
5
10
10
10
C
− External Timing Capacitance − pF
C
− External Timing Capacitance − pF
T
T
Figure 2
Figure 3
MINIMUM TRIGGER TIME
vs
OUTPUT PULSE-DURATION CONSTANT
vs
V
CHARACTERISTICS
CC
SUPPLY VOLTAGE
10.00
1.00
0.10
1.20
1.15
R
T
A
= 1 kΩ
= 25°C
R
T
t
= 10 kΩ
= 25°C
T
T
A
w
= K × C × R
T T
C
= 0.01 µF
T
1.10
1.05
1.00
C
= 1000 pF
T
C
= 1000 pF
T
C
= 0.01 µF
T
C
= 1 µF, C = 0.1 µF
T
T
C
= 100 pF
T
0.95
0.90
0.01
0
1
2
3
4
5
6
1.5
2
2.5
V
3
3.5
4
4.5
5
5.5
6
V
CC
− Supply Voltage − V
− Supply Voltage − V
CC
Figure 5
Figure 4
†
Operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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