SN74LV138A-Q1 [TI]
汽车类三线至八线解码器/多路信号分离器;
| 型号： | SN74LV138A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类三线至八线解码器/多路信号分离器 解码器 |
| 文件： | 总25页 (文件大小：1861K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV138-Q1
ZHCSPK2 –DECEMBER 2022
SN74LV138A-Q1 汽车类3 线至8 线解码器或多路解复用器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
SN74LV138A-Q1 器件是旨在于 2V 至 5.5V VCC 下运
行的3 线至8 线解码器/多路解复用器。
– 器件温度等级1：–40°C 至+125°C，TA
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C6
二进制选择输入（A0 、A1 、A2 ）和三个使能输入
（G2、G0、G1）条件可从八条输出线路中选择其中一
条。两个低电平有效使能输入（G0、G1）和一个高电
平有效使能输入 (G2) 可在扩展时减少对外部门电路或
反相器的需求。
• 在2V 至5.5V VCC 下运行
• 5V 时tpd 最大值为9.5ns
• VOLP（输出接地反弹）典型值
小于0.8V（VCC = 3.3V、TA = 25°C 时）
• VOHV（输出VOH 下冲）典型值
大于2.3V（VCC = 3.3V、TA = 25°C 时）
• 支持所有端口上的混合模式电压运行
• Ioff 支持局部断电模式运行
器件信息
器件型号
封装(1)
封装尺寸
SN74LV138A-Q1
BQB（WQFN，16） 3.60mm × 2.60mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 闩锁性能超过250mA，符合JESD 17 规范
2 应用
• 输出扩展
• LED 矩阵控制
• 7 段显示控制
• 8 位数据存储
3:8 DECODER
OUTPUT
ENABLE
000
001
010
011
100
101
110
111
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A1
A2
G0
G1
G2
逻辑图（正逻辑）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS885
SN74LV138-Q1
ZHCSPK2 –DECEMBER 2022
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
10 Power Supply Recommendations..............................15
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 接收文档更新通知................................................... 17
12.2 支持资源..................................................................17
12.3 Trademarks.............................................................17
12.4 Electrostatic Discharge Caution..............................17
12.5 术语表..................................................................... 17
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions(1) .................... 5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics - VCC = 2.5 V ± 0.25 V....... 6
6.7 Switching Characteristics - VCC = 3.3 V ± 0.3 V......... 6
6.8 Switching Characteristics - VCC = 5 V ± 0.5 V............ 7
6.9 Operating Characteristics........................................... 7
6.10 Typical Characteristics..............................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
Information.................................................................... 18
4 Revision History
DATE
REVISION
NOTES
December 2022
*
Initial Release
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5 Pin Configuration and Functions
A0
1
VCC
16
A1
2
15 Y0
A2
G0
G1
G2
Y7
3
4
5
6
7
Y1
Y2
14
13
PAD
12
11
10
Y3
Y4
Y5
8
9
GND Y6
图5-1. BQB Package 16-Pin (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1
A0
A1
I
I
Address select 0
Address select 1
2
3
A2
I
Address select 2
G2
G0
G1
6
4
I
I
Strobe input
Strobe input, active low
Strobe input, active low
Ground
5
I
GND
VCC
8
G
P
16
Positive supply
15
Y0
Y1
Y2
O
O
O
Output 0
Output 1
Output 2
14
13
12
11
10
Y3
Y4
Y5
Y6
O
O
O
O
Output 3
Output 4
Output 5
Output 6
9
7
Y7
O
-
Output 7
Thermal Pad
Thermal Pad(2)
(1) Signal Types: I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power
(2) BQB package only
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
7
V
V
Input voltage range(2)
7
7
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2) (3)
V
VCC + 0.5
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
–20
–50
±25
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
Storage temperature range
VO = 0 to VCC
±50
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
±2000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level
C4B
±1000
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions(1)
SN74LV138A-Q1
UNIT
MIN
2
MAX
VCC
Supply voltage
5.5
V
VCC = 2 V
1.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
VCC × 0.7
VCC × 0.7
VCC × 0.7
VIH
High-level input voltage
V
V
0.5
VCC × 0.3
VCC × 0.3
VCC × 0.3
5.5
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VIL
Low-level input voltage
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
VCC = 2 V
–50 μA
–2
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level output current
Low-level output current
mA
–6
–12
50
μA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
IOL
6
mA
12
200
Input transition rise or fall rate
Operating free-air temperature
100 ns/V
20
Δt/Δv
TA
125 °C
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs.
6.4 Thermal Information
SN74LV138A-Q1
THERMAL METRIC(1)
UNIT
WBQB (WQFN)
16 PINS
86
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
82.6
54.9
9.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
54.9
32.5
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see IC Package Thermal Metrics.
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6.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
SN74LV138A-Q1
PARAMETER
TEST CONDITIONS
VCC
UNIT
MAX
MIN
TYP
2 V to 5.5 V
2.3 V
IOH = –50 μA
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 μA
VCC –0.1
2
VOH High-Level Output Voltage
V
3 V
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
IOL = 2 mA
0.4
V
VOL Low-Level Output Voltage
IOL = 6 mA
3 V
0.44
IOL = 12 mA
4.5 V
0.55
VI = 5.5 V or GND
VI = VCC or GND, IO = 0
II
Input Current
0 to 5.5 V
5.5 V
±1
20
5
μA
μA
μA
pF
ICC Supply Current
Ioff
Ci
Input/Output Power-Off Leakage Current
Input Capacitance
VI or VO = 0 to 5.5 V
VI = VCC or GND
0
3.3 V
2.1
6.6 Switching Characteristics - VCC = 2.5 V ± 0.25 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
SN74LV138A-
Q1
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
TYP
11.7
12.3
11.4
14.9
15.7
14.8
MAX
17.6
19.2
18.2
21.4
22.6
22
MIN
1
MAX
A0, A1, A2
G2
21
22
21
25
26
25
tpd
Y
Y
CL = 15 pF
CL = 50 pF
1
ns
G0 or G1
A0, A1, A2
G2
1
1
tpd
1
ns
G0 or G1
1
6.7 Switching Characteristics - VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
SN74LV138A-
Q1
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
TYP
8.1
MAX
11.4
12.8
11.4
15.8
16.3
14.9
MIN
1
MAX
A0, A1, A2
G2
13.5
15
tpd
Y
Y
CL = 15 pF
CL = 50 pF
8.4
1
ns
G0 or G1
A0, A1, A2
G2
7.8
1
13.5
18
10.3
10.6
10
1
tpd
1
18.5
17
ns
G0 or G1
1
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6.8 Switching Characteristics - VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
SN74LV138A-
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
Q1
PARAMETER
UNIT
MIN
TYP
5.6
5.7
5.4
7
MAX
8.1
MIN
1
MAX
9.5
A0, A1, A2
G2
tpd
Y
Y
CL = 15 pF
CL = 50 pF
8.1
1
9.5
ns
G0 or G1
A0, A1, A2
G2
8.1
1
9.5
10.1
10.1
10.1
1
11.5
11.5
11.5
tpd
7.1
6.8
1
ns
G0 or G1
1
6.9 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
TYP UNIT
3.3 V
5 V
16.8
pF
19.1
Cpd
Power dissipation capacitance
CL = 50 pF, f = 10 MHz
6.10 Typical Characteristics
80
5.5
5
-40°C
125°C
72
25°C
64
4.5
4
56
48
40
32
24
16
8
3.5
3
2.5
2
2.5 V
3.3 V
5 V
1.5
1
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
-16
-14
-12
-10
-8
-6
-4
-2
0
VCC (V)
IOH (mA)
图6-1. Supply Current (ICC) vs Supply Voltage (VCC
)
图6-2. Output Voltage vs Current in HIGH State
0.4
0.35
0.3
0.25
0.2
0.15
0.1
2.5 V
3.3 V
5 V
0.05
0
0
2
4
6
8
10
12
14
16
IOL (mA)
图6-3. Output Voltage vs Current in LOW State
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7 Parameter Measurement Information
V
CC
S1
Open
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
Test
From Output
Under Test
GND
Point
t
t
Open
PLH PHL
C
C
L
(see Note A)
t
/t
PLZ PZL
V
CC
L
(see Note A)
/t
PHZ PZH
GND
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
Input
CC
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
CC
Input
CC
CC
CC
0 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
≈V
V
CC
OH
In-Phase
Output
Waveform 1
S1 at V
50% V
50% V
CC
50% V
CC
CC
V
V
+ 0.3 V
OL
CC
(see Note B)
V
OL
V
OL
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
OL
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
f
O
r
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
t
t
t
and t
and t
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
are the same as t
.
PZH
en
are the same as t .
G.
and t
PLH pd
H. All parameters and waveforms are not applicable to all devices.
图7-1. Load Circuits and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV138A-Q1 devices are 3-line to 8-line decoders/demultiplexers designed for 2 V to 5.5 V VCC
operation.
These devices are designed for high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, these decoders can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of these decoders and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs (A0, A1, A2) and the three enable inputs (G2, G0, G1) select one of
eight output lines. The two active-low (G0, G1) and one active-high (G2) enable inputs reduce the need for
external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
8.2 Functional Block Diagram
3:8 DECODER
000
OUTPUT
ENABLE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A1
A2
G0
G1
G2
001
010
011
100
101
110
111
图8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Standard CMOS Inputs
This device includes standard CMOS inputs. Standard CMOS inputs are high impedance and are typically
modeled as a resistor in parallel with the input capacitance given in the Electrical Characteristics. The worst case
resistance is calculated with the maximum input voltage, given in the Absolute Maximum Ratings, and the
maximum input leakage current, given in the Electrical Characteristics, using Ohm's law (R = V ÷ I).
Standard CMOS inputs require that input signals transition between valid logic states quickly, as defined by the
input transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification
will result in excessive power consumption and could cause oscillations. More details can be found in
Implications of Slow or Floating CMOS Inputs.
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Do not leave standard CMOS inputs floating at any time during operation. Unused inputs must be terminated at
VCC or GND. If a system will not be actively driving an input at all times, then a pull-up or pull-down resistor can
be added to provide a valid input voltage during these times. The resistor value will depend on multiple factors; a
10-kΩresistor, however, is recommended and will typically meet all requirements.
8.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.3 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
8.3.4 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Standard Lead
We able Flank Lead
Pad
PCB
图8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with
automatic optical inspection (AOI). As shown in 图 8-2, a wettable flank can be dimpled or step-cut to provide
additional surface area for solder adhesion which assists in reliably creating a side fillet. See the mechanical
drawing for additional details.
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8.3.5 Clamp Diode Structure
图8-3 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
图8-3. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
Function Table
ENABLE INPUTS(1) SELECT INPUTS
G2 G0 G1 A0
OUTPUTS(2)
A2
A1
Y0
Y1
Y20
Y3
Y4
Y5
Y6
Y7
X
H
X
X
X
X
H
H
H
H
H
H
H
L
H
H
H
H
H
X
L
X
X
L
L
L
L
L
L
L
L
H
X
L
L
L
L
L
L
L
L
X
X
L
X
X
L
X
X
L
H
H
L
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
H
H
L
H
H
L
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
L
H
H
H
H
H
H
H
H
H
(1) H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
(2) H = Driving High, L = Driving Low, Z = High Impedance State
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9 Application and Implementation
备注
以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客 户应负责确定
器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。
9.1 Application Information
The SN74LV138A-Q1 is a low drive CMOS device that can be used for a multitude of output expansion
applications where output ringing is a concern. The low-drive and slow-edge rates minimize overshoot and
undershoot on the outputs.
9.2 Typical Application
Y0
Device 1
A0
A1
A2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Device 2
Device 3
Device 4
Device 5
Device 6
Device 7
Device 8
System
Controller
G2
G1
G0
CONTROL
LOGIC
Data Bus
图9-1. Output Exapnsion with Multiplexer
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9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV138A-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV138A-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV138A-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74LV138A-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV138A-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74LV138A-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined
in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
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9.2.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LV138A-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.5 Application Curves
G2
A2
A1
A0
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
图9-2. Application Timing Diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC
terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for
best results.
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11 Layout
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital
logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage
specifications, to prevent them from floating. The logic level that must be applied to any particular unused input
depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more
sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1 ꢀF
16
Unused
inputs tied to
VCC
A0
1
VCC
A1
A2
2
3
4
5
6
7
8
15
14
13
12
11
10
9
Y0
Y1
Y2
Y3
Y4
Y5
Y6
G0
Unused input
tied to GND
G1
G2
Avoid 90°
corners for
signal lines
Y7
GND
Unused
output left
floating
图11-1. Layout Example for the SN74LV138A-Q1
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
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13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV138AQWBQBRQ1
ACTIVE
WQFN
BQB
16
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV138Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV138A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
31-Jan-2023
Catalog : SN74LV138A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
GENERIC PACKAGE VIEW
BQB 16
2.5 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226161/A
www.ti.com
PACKAGE OUTLINE
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
A
2.6
2.4
B
PIN 1 INDEX AREA
3.6
3.4
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.1
0.9
2X 0.5
(0.2) TYP
9
8
10X 0.5
7
10
(0.16)
SYMM
SYMM
2X
2.5
17
2.1
1.9
0.3
16X
0.2
0.1
0.05
C A B
C
15
2
PIN 1 ID
(OPTIONAL)
1
16
0.5
0.3
16X
SYMM
4226135/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(1)
1
16
16X (0.6)
16X (0.25)
2
15
10X (0.5)
SYMM
17
(2)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
(Ø 0.2) VIA
TYP
8
9
2X (0.5)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(0.95)
1
16
16X (0.6)
16X (0.25)
2
15
17
10X (0.5)
SYMM
(1.79)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
METAL TYP
8
9
2X (0.5)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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相关型号：
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