SN74LV138ATPWG4 [TI]
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER; 3线至8线译码器/多路解复用器
| 型号： | SN74LV138ATPWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER |
| 文件： | 总20页 (文件大小：867K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV138AT
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
www.ti.com
SCLS691–AUGUST 2005
FEATURES
•
•
•
•
Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Max tpd of 7.6 ns at 5 V
•
•
•
Ioff Supports Partial-Power Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 5 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All
Ports
– 1000-V Charged-Device Model (C101)
D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
A
B
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
Y0
Y1
Y2
1
16
C
15
14
13
12
11
10
B
C
G2A
G2B
G1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
G2A
G2B
G1
12 Y3
11
10
9
Y4
Y5
Y6
Y7
GND
Y7
8
9
DESCRIPTION/ORDERING INFORMATION
The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding
or data-routing applications requiring very short propagation delay times. In high-performance memory systems,
this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories
utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less
than the typical access time of the memory. This means that the effective system delay introduced by the
decoder is negligible.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LV138ATRGYR
SN74LV138ATD
TOP-SIDE MARKING
VV138AT
QFN – RGY
SOIC – D
Reel of 1000
Tube of 40
LV138AT
Reel fo 2500
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 90
SN74LV138ATDR
SOP – NS
SN74LV138ATNSR
SN74LV138ATDBR
SN74LV138ATDGVR
SN74LV138ATPW
74LV138AT
LV138AT
LV138AT
–40°C to 125°C
SSOP – DB
TVSOP – DGV
TSSOP – PW
Reel of 2000
Reel of 250
SN74LV138ATPWR
SN74LV138ATPWT
LV138AT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV138AT
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
www.ti.com
SCLS691–AUGUST 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of
eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for
external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters
and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing
applications.
This device is fully specified for partial-power-down application susing Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
Y3
G1
G2A
H
X
X
L
G2B
C
X
X
X
L
B
X
X
X
L
A
X
X
X
L
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
X
L
X
H
X
L
L
L
L
L
L
L
L
H
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
2
SN74LV138AT
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
www.ti.com
SCLS691–AUGUST 2005
LOGIC DIAGRAM (POSITIVE LOGIC)
15
14
13
12
11
10
9
Y0
Y1
1
2
A
B
Select
Inputs
Y2
Y3
Y4
Y5
Y6
3
C
Data
Outputs
6
4
5
G1
Enable
Inputs
7
G2A
G2B
Y7
3
SN74LV138AT
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
www.ti.com
SCLS691–AUGUST 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage
Input voltage range(2)
7
7
V
V
VO
IIK
Output voltage range(2)(3)
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–20
±50
±25
±50
73
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
Continuous current through VCC or GND
D package(4)
DB package(4)
DGV package(4)
NS package(4)
PW package(4)
RGY package(5)
82
120
64
θJA
Package thermal impedance
Storage temperature range
°C/W
°C
108
39
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited of 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
MIN
4.5
2
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
5.5
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
0.8
5.5
VCC
–12
12
V
0
0
V
VO
Output voltage
V
IOH
IOL
∆t/∆v
TA
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
mA
mA
ns/V
°C
20
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
4
SN74LV138AT
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
www.ti.com
SCLS691–AUGUST 2005
Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TA = –40°C
to 85°C
TA = –40°C
to 125°C
TA = 25°C
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VCC
UNIT
MIN
4.4
TYP
MAX
MIN
4.4
MAX
MIN
4.4
MAX
4.5 V
4.5 V
4.5
VOH
V
V
IOH = –12 mA
3.8
3.8
3.8
IOL = 50 µA
4.5 V
0
0.1
0.55
±0.1
2
0.1
0.55
±1
0.1
0.55
±1
VOL
IOL = 12 mA
4.5 V
II
VI = 5.5 V or GND
VI = VCC or GND, IO = 0
0 to 5.5 V
5.5 V
µA
µA
ICC
20
20
One input at 3.4 V,
Other inputs at VCC or GND
(1)
∆ICC
5.5 V
0
1.35
1.5
1.5
mA
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
0.5
10
5
5
µA
4
10
10
pF
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V ot VCC
.
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = –40°C TA = –40°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
to 85°C
to 125°C
PARAMETER
UNIT
MIN TYP MAX MIN MAX MIN MAX
A, B, or C
G1
2.7
2.5
2.8
3.9
3.7
4
7.6 10.4
1
1
1
1
1
1
12
10.5
11
1
1
1
1
1
1
13
tpd
Y
Y
CL = 15 pF
CL = 50 pF
6.6
7
9.1
9.6
12 ns
12
G2A or G2B
A, B, or C
G1
8.1 11.4
7.1 10.1
7.5 10.6
13
14
tpd
11.5
12
12 ns
13
G2A or G2B
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
TYP UNIT
Cpd
79
pF
5
SN74LV138AT
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
www.ti.com
SCLS691–AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
Open
PLH PHL
C
L
C
L
t
/t
V
CC
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
≈V
V
CC
OH
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
CC
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHL
PHZ
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
PACKAGING INFORMATION
Orderable Device
SN74LV138ATD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV138ATDBR
SN74LV138ATDBRE4
SN74LV138ATDBRG4
SN74LV138ATDE4
SN74LV138ATDG4
SN74LV138ATDGVR
SN74LV138ATDGVRE4
SN74LV138ATDGVRG4
SN74LV138ATDR
SSOP
SSOP
SSOP
SOIC
DB
DB
DB
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV138ATDRE4
SN74LV138ATDRG4
SN74LV138ATNSR
SN74LV138ATNSRE4
SN74LV138ATNSRG4
SN74LV138ATPW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
RGY
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV138ATPWE4
SN74LV138ATPWG4
SN74LV138ATPWR
SN74LV138ATPWRE4
SN74LV138ATPWRG4
SN74LV138ATPWT
SN74LV138ATPWTE4
SN74LV138ATPWTG4
SN74LV138ATRGYR
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
Orderable Device
SN74LV138ATRGYRG4
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
ACTIVE
VQFN
RGY
16
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV138ATDBR
SN74LV138ATDGVR
SN74LV138ATDR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
16
2000
2000
2500
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
16.4
12.4
12.4
12.4
8.2
6.8
6.5
8.2
6.9
6.9
3.8
6.6
4.0
2.5
1.6
2.1
2.5
1.6
1.6
1.5
12.0
8.0
16.0
12.0
16.0
16.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
10.3
10.5
5.6
8.0
SN74LV138ATNSR
SN74LV138ATPWR
SN74LV138ATPWT
SN74LV138ATRGYR
SO
NS
12.0
8.0
TSSOP
TSSOP
VQFN
PW
PW
RGY
5.6
8.0
3000
4.3
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV138ATDBR
SN74LV138ATDGVR
SN74LV138ATDR
SSOP
TVSOP
SOIC
DB
DGV
D
16
16
16
16
16
16
16
2000
2000
2500
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
35.0
38.0
38.0
35.0
35.0
35.0
SN74LV138ATNSR
SN74LV138ATPWR
SN74LV138ATPWT
SN74LV138ATRGYR
SO
NS
TSSOP
TSSOP
VQFN
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
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