SN74LV163APWRG4 [TI]
4-BIT SYNCHRONOUS BINARY COUNTERS;
| 型号： | SN74LV163APWRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 4-BIT SYNCHRONOUS BINARY COUNTERS 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总20页 (文件大小：498K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁꢋ ꢃꢄꢅ ꢆꢇ ꢈꢉ
ꢃ ꢌꢍꢎ ꢏ ꢀꢐ ꢁꢑꢒꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁꢉꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
D
D
D
2-V to 5.5-V V
Operation
D
D
D
Synchronous Counting
CC
Max t of 9.5 ns at 5 V
Synchronously Programmable
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
I
Supports Partial-Power-Down Mode
OLP
CC
off
= 3.3 V, T = 25°C
Operation
A
D
D
Typical V
>2.3 V at V
(Output V
Undershoot)
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
OHV
CC
OH
= 3.3 V, T = 25°C
A
Support Mixed-Mode Voltage Operation on
All Ports
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
D
Internal Look Ahead for Fast Counting
Carry Output for n-Bit Cascading
− 1000-V Charged-Device Model (C101)
D
SN54LV163A . . . J OR W PACKAGE
SN74LV163A . . . D, DB, DGV, NS,
OR PW PACKAGE
SN74LV163A . . . RGY PACKAGE
(TOP VIEW)
SN54LV163A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
16
CLR
CLK
A
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
CC
RCO
3
2
1 20 19
18
CLK
A
15
14
13
12
11
10
2
3
4
5
6
7
RCO
A
B
Q
Q
4
5
6
7
8
A
B
Q
17
16
15
14
A
Q
Q
Q
Q
A
B
C
D
B
C
D
Q
B
NC
C
NC
B
C
D
Q
C
Q
Q
C
D
Q
D
ENT
D
9 10 11 12 13
ENP
ENP
GND
ENT
LOAD
8
9
NC − No internal connection
description/ordering information
ORDERING INFORMATION
ORDERABLE
TOP-SIDE
MARKING
†
PACKAGE
T
A
PART NUMBER
SN74LV163ARGYR
SN74LV163AD
QFN − RGY
SOIC − D
Reel of 1000
Tube of 40
LV163A
LV163A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV163ADR
SN74LV163ANSR
SN74LV163ADBR
SN74LV163APW
SN74LV163APWR
SN74LV163APWT
SN74LV163ADGVR
SNJ54LV163AJ
SOP − NS
74LV163A
LV163A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV163A
TVSOP − DGV
CDIP − J
LV163A
SNJ54LV163AJ
SNJ54LV163AW
SNJ54LV163AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV163AW
SNJ54LV163AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢕ ꢁ ꢄꢖꢀꢀ ꢔ ꢏꢒ ꢖꢓꢗ ꢎꢀ ꢖ ꢁ ꢔꢏꢖꢘ ꢙꢚ ꢛꢜ ꢝꢞꢟ ꢠꢡꢢ ꢣꢙ ꢟꢞ ꢣꢙꢤ ꢛꢣꢜ ꢥꢓ ꢔ ꢘ ꢕ ꢑꢏ ꢎꢔ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢌ ꢍꢎ ꢏ ꢀꢐ ꢁꢑ ꢒ ꢓ ꢔꢁ ꢔꢕ ꢀ ꢍꢎ ꢁ ꢉꢓꢐ ꢑꢔ ꢕꢁ ꢏꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
The ’LV163A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V V
operation.
CC
These synchronous, presettable counters feature an internal carry look ahead for application in high-speed
counting designs. The ’LV163A devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by
the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV163A devices is synchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with Q high). This high-level overflow ripple-carry pulse
A
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
FUNCTION
LOAD
ENP
X
ENT
X
CLK
QB
L
QC
L
QD
L
CLR
L
QA
L
X
L
X
Reset to “0”
Preset data
No count
No count
Count
H
X
X
A
B
C
D
H
H
H
H
X
X
L
No change
No change
Count up
H
L
X
H
H
H
H
X
X
No change
No count
2
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢃ ꢌꢍꢎ ꢏ ꢀꢐ ꢁꢑꢒꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁꢉꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
logic diagram (positive logic)
9
LOAD
10
ENT
15
RCO
†
LD
7
ENP
†
CK
2
CLK
1
CK
LD
CLR
R
M1
G2
14
1, 2T/1C3
G4
Q
Q
A
B
3
3D
4R
A
M1
G2
13
12
11
1, 2T/1C3
G4
3D
4R
4
B
M1
G2
1, 2T/1C3
Q
C
G4
3D
4R
5
C
M1
G2
1, 2T/1C3
Q
D
G4
3D
4R
6
D
†
For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown
on the logic diagram of the D/T flip-flops.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, RGY, and W packages.
3
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ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢌ ꢍꢎ ꢏ ꢀꢐ ꢁꢑ ꢒ ꢓ ꢔꢁ ꢔꢕ ꢀ ꢍꢎ ꢁ ꢉꢓꢐ ꢑꢔ ꢕꢁ ꢏꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
logic diagram, each D/T flip-flop (positive logic)
CK
LD
TE
†
TG
TG
LD
TG
Q
TG
†
LD
†
CK
D
R
†
CK
TG
TG
†
†
CK
CK
†
The origins of LD and CK are shown in the overall logic diagram of the device.
4
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢉ
ꢃ
ꢌ
ꢍ
ꢎ
ꢏ
ꢀ
ꢐ
ꢁ
ꢑ
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ꢓ
ꢔ
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ꢍ
ꢎ
ꢁ
ꢓ
ꢐ
ꢑ
ꢔ
ꢕ
ꢁ
ꢏ
ꢖ
ꢓ
ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
typical clear, preset, count, and inhibit sequence
The following sequence is illustrated below:
1. Clear outputs to zero (synchronous)
2. Preset to binary 12
3. Count to 13, 14, 15, 0, 1, and 2
4. Inhibit
CLR
LOAD
A
B
Data
Inputs
C
D
CLK
ENP
ENT
Q
A
Q
Q
Q
B
C
D
Data
Outputs
RCO
12
13
14
15
0
1
2
Count
Inhibit
Sync Preset
Clear
Async
Clear
5
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ꢃꢌ ꢍꢎ ꢏ ꢀꢐ ꢁꢑ ꢒ ꢓ ꢔꢁ ꢔꢕ ꢀ ꢍꢎ ꢁ ꢉꢓꢐ ꢑꢔ ꢕꢁ ꢏꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range applied in high or low state, V (see Notes 1 and 2) . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Voltage range applied to any output in the power-off state, V (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
6
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢃ ꢌꢍꢎ ꢏ ꢀꢐ ꢁꢑꢒꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁꢉꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV163A
SN74LV163A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
IH
V
V
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
× 0.3
× 0.3
5.5
× 0.3
× 0.3
5.5
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV163A
SN74LV163A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I
O
= 0
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.8
1.8
i
I
CC
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ꢟ
ꢤ
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ꢤ
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ꢝ
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ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢏ
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ꢬ
ꢤ
ꢜ
ꢎ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞꢝ ꢠꢟꢙ ꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
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ꢞ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢌ ꢍꢎ ꢏ ꢀꢐ ꢁꢑ ꢒ ꢓ ꢔꢁ ꢔꢕ ꢀ ꢍꢎ ꢁ ꢉꢓꢐ ꢑꢔ ꢕꢁ ꢏꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
timing
CC
requirements
over
recommended
operating
free-air
temperature
range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
T
= 25°C
SN54LV163A SN74LV163A
A
UNIT
MIN
7
MAX
MIN
7
MAX
MIN
7
MAX
t
w
Pulse duration, CLK high or low
ns
CLR
6
6
6
Data (A, B, C, and D)
ENP, ENT
7.5
9.5
10
1.5
8.5
11
8.5
11
t
ns
Setup time before CLK↑
su
h
LOAD low
11.5
1.5
11.5
1.5
t
Hold time, all synchronous inputs after CLK↑
ns
timing
CC
requirements
over
recommended
operating
free-air
temperature
range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
T
= 25°C
SN54LV163A SN74LV163A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
Pulse duration, CLK high or low
ns
CLR
4
4
4
Data (A, B, C, and D)
ENP, ENT
5.5
7.5
8
6.5
9
6.5
9
t
ns
ns
Setup time before CLK↑
su
h
LOAD low
9.5
1
9.5
1
t
Hold time, all synchronous inputs after CLK↑
1
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV163A SN74LV163A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
t
w
Pulse duration, CLK high or low
ns
CLR
3.5
4.5
5
3.5
4.5
6
3.5
4.5
6
Data (A, B, C, and D)
ENP, ENT
t
ns
ns
Setup time before CLK↑
su
h
LOAD low
5
6
6
t
Hold time, all synchronous inputs after CLK↑
1
1
1
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ꢞ
ꢞ
ꢦ
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ꢰ
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ꢯ
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ꢞ
ꢞ
ꢤ
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ꢪ
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ꢡ
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ꢏ
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ꢢ
ꢠ
ꢙ
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ꢞ
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ꢛ
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ꢧ
ꢟ
ꢝ
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ꢧ
ꢙ
ꢰ
ꢤ
ꢢ
ꢤ
ꢣ
ꢢ
ꢝ
ꢞ
ꢙ
ꢚ
ꢙ
ꢢ
ꢧ
ꢜ
ꢨ
ꢛ
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ꢛ
ꢟ
ꢤ
ꢙ
ꢛ
ꢞ
ꢧ
ꢢ
ꢝ
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ꢠ
ꢜ
ꢛ
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ꢤ
ꢙ
ꢜ
ꢎ
ꢧ
ꢠ
ꢢ
ꢜ
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ꢜ
ꢙ
ꢚ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢞ
ꢟ
ꢚ
ꢯ
ꢢ
ꢞ
ꢧ
ꢛ
ꢜ
ꢣ
ꢙ
ꢛ
ꢣ
ꢢ
ꢙ
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ꢞ
ꢜ
ꢭ
ꢞ
ꢠ
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ꢫ
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢃ ꢌꢍꢎ ꢏ ꢀꢐ ꢁꢑꢒꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁꢉꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
115*
90
SN54LV163A SN74LV163A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50*
30
MAX
MIN
40*
25
MAX
MIN
40
25
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
8.5* 16.2*
1* 19.5*
19.5
20.5
Q
RCO
(count mode)
9.1* 17*
1* 20.5*
1
1
CLK
ENT
t
C
C
= 15 pF
ns
ns
L
L
RCO
(preset mode)
12.1* 20.6*
8.7* 15.7*
1* 24.5*
24.5
1*
1
19*
1
1
19
RCO
Q
11
19.2
20
22.5
22.5
RCO
(count mode)
11.9
1
23.5
1
23.5
CLK
ENT
t
pd
= 50 pF
RCO
(preset mode)
14.6
11.7
23.6
18.7
1
1
27.5
22
1
1
27.5
22
RCO
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV163A SN74LV163A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
80*
55
MAX
MIN
70*
50
MAX
MIN
70
50
1
MAX
C
C
= 15 pF
= 50 pF
160*
125
L
L
f
MHz
max
pd
6.2* 12.8*
1*
15*
16*
15
16
Q
RCO
(count mode)
6.8* 13.6*
1*
1*
1
1
CLK
ENT
t
C
C
= 15 pF
ns
ns
L
L
RCO
(preset mode)
8.8* 17.2*
6.5* 12.3*
20*
20
1* 14.5*
1
1
14.5
18.5
RCO
Q
8
16.3
17.1
1
1
18.5
19.5
RCO
(count mode)
8.8
1
19.5
CLK
ENT
t
pd
= 50 pF
RCO
(preset mode)
10.7
8.2
20.7
15.8
1
1
23.5
18
1
1
23.5
18
RCO
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢥ
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ꢞ
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ꢡ
ꢤ
ꢙ
ꢛ
ꢞ
ꢣ
ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢝꢢ ꢜ ꢛ ꢯꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪꢞ ꢨꢡꢢ ꢣꢙꢫ ꢑ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢟ
ꢙ
ꢜ
ꢛ
ꢣ
ꢙ
ꢚ
ꢢ
ꢦ
ꢞ
ꢧ
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ꢤ
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ꢰ
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ꢞ
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ꢞ
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ꢜ
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ꢧ
ꢢ
ꢝ
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ꢜ
ꢛ
ꢯ
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ꢞ
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ꢬ
ꢤ
ꢜ
ꢎ
ꢣ
ꢜ
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ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞꢝ ꢠꢟꢙ ꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ
ꢃꢌ ꢍꢎ ꢏ ꢀꢐ ꢁꢑ ꢒ ꢓ ꢔꢁ ꢔꢕ ꢀ ꢍꢎ ꢁ ꢉꢓꢐ ꢑꢔ ꢕꢁ ꢏꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
210*
160
SN54LV163A SN74LV163A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
135*
95
MAX
MIN
115*
85
MAX
MIN
115
85
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
pd
4.7*
8.1*
8.1*
1*
9.5*
9.5*
1
9.5
9.5
Q
RCO
(count mode)
5.2*
1*
1*
1
1
CLK
ENT
t
C
C
= 15 pF
ns
ns
L
L
RCO
(preset mode)
6.4* 10.3*
12*
12
4.9*
6.1
8.1*
10.1
1*
1
9.5*
11.5
1
1
9.5
RCO
Q
11.5
RCO
(count mode)
6.6
10.1
1
11.5
1
11.5
CLK
ENT
t
pd
= 50 pF
RCO
(preset mode)
7.8
6.3
12.3
10.1
1
1
14
1
1
14
11.5
11.5
RCO
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 6)
CC
L
A
SN74LV163A
PARAMETER
UNIT
MIN
TYP
0.3
−0.2
3
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.8
OL
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
23.8
26
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
ꢥ
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ꢟ
ꢞ
ꢣ
ꢟ
ꢢ
ꢧ
ꢣ
ꢜ
ꢨ
ꢧ
ꢞ
ꢝ
ꢠ
ꢟ
ꢝ ꢢ ꢜ ꢛ ꢯ ꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪ ꢞꢨ ꢡꢢ ꢣ ꢙꢫ ꢑ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ
ꢙ
ꢜ
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ꢚ
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ꢦ
ꢞ
ꢧ
ꢡ
ꢤ
ꢙ
ꢛ
ꢰ
ꢢ
ꢞ
ꢧ
ꢜ
ꢨ
ꢢ
ꢟ
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ꢦ
ꢛ
ꢟ
ꢤ
ꢙ
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ꢞ
ꢣ
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ꢤ
ꢧ
ꢢ
ꢝ
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ꢛ
ꢯ
ꢣ
ꢯ
ꢞ
ꢤ
ꢪ
ꢜ
ꢫ
ꢏ
ꢢ
ꢬ
ꢤ
ꢜ
ꢎ
ꢣ
ꢜ
ꢙ
ꢧ
ꢠ
ꢡ
ꢢ
ꢣ
ꢟ ꢚ ꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞ ꢝꢠꢟ ꢙꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ
ꢙ
ꢜ
ꢧ
ꢢ
ꢜ
ꢢ
ꢧ
ꢰ
ꢢ
ꢜ
ꢙ
ꢚ
ꢢ
ꢧ
ꢛ
ꢯ
ꢚ
ꢙ
ꢙ
ꢞ
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢋꢃ ꢄꢅ ꢆꢇ ꢈꢉ
ꢃ ꢌꢍꢎ ꢏ ꢀꢐ ꢁꢑꢒꢓꢔ ꢁꢔ ꢕꢀ ꢍꢎ ꢁꢉꢓꢐ ꢑꢔ ꢕ ꢁꢏ ꢖꢓ ꢀ
SCLS405F − APRIL 1998 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
From Output
Under Test
Test
Point
From Output
Under Test
TEST
S1
t
t
/t
Open
C
C
PLH PHL
/t
L
L
t
V
CC
(see Note A)
(see Note A)
PLZ PZL
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
PLZ
t
t
t
PZL
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
PACKAGING INFORMATION
Orderable Device
SN74LV163AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV163ADBR
SN74LV163ADBRE4
SN74LV163ADE4
SN74LV163ADGVR
SN74LV163ADGVRE4
SN74LV163ADR
SSOP
SSOP
SOIC
DB
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
D
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
SOIC
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV163ADRE4
SN74LV163ANSR
SN74LV163ANSRE4
SN74LV163APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
QFN
PW
PW
PW
PW
PW
PW
RGY
RGY
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV163APWE4
SN74LV163APWR
SN74LV163APWRE4
SN74LV163APWT
SN74LV163APWTE4
SN74LV163ARGYR
SN74LV163ARGYRG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
QFN
1000 Green (RoHS & CU NIPDAU Level-2-260C-1YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
6-Dec-2006
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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