SN74LV165A-Q1 [TI]
汽车类八位并行负载移位寄存器;
| 型号： | SN74LV165A-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类八位并行负载移位寄存器 移位寄存器 |
| 文件： | 总27页 (文件大小：1914K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV165A-Q1
ZHCSPK1A –JULY 2022 –REVISED DECEMBER 2022
SN74LV165A-Q1 汽车并联负载8 位移位寄存器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 器件温度等级1：
SN74LV165A-Q1 器件是 8 位并行负载移位寄存器，
旨在于2V 至5.5V VCC 下运行。
• 40°C 至+ 125°C，TA
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C6
• 采用具有可湿性侧面的QFN (WBQB) 封装
• 2 V 至5.5 V VCC 运行
• 5V 时tpd 最大值为10.5 ns
• 所有端口上均支持以混合模式电压运行
• Ioff 支持局部断电模式运行
器件计时时，数据通过串行输出 QH 传输。当移位/负
载 (SH/LD) 输入为低电平时，可支持八个单独的直接
数据输入， 从而实现在每个级的并行输入。
SN74LV165A-Q1 器件具有时钟抑制功能和补充串行输
出Q H。
该器件专用于使用Ioff 的局部断电应用。Ioff 电路会禁用
输出，从而在器件断电时防止电流回流损坏器件。
器件信息(1)
• 闩锁性能超过250mA，符合JESD 17 规范
封装尺寸（标称值）
器件型号
封装
2 应用
WBQB（WQFN、
16）
SN74LV165A-Q1
3.60 × 2.60mm
• 增加微控制器上的输入数量
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
A
H
B
C
D
E
F
G
SH/LD
5 Additional
Shift Register
Stages
S
D
R
Q
S
D
R
Q
S
D
R
Q
Q
QH
QH
SER
CLK INH
CLK
逻辑图（正逻辑）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS884
SN74LV165A-Q1
ZHCSPK1A –JULY 2022 –REVISED DECEMBER 2022
www.ti.com.cn
Table of Contents
8.1 Overview................................................................... 11
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................16
11 布局................................................................................17
11.1 Layout Guidelines................................................... 17
11.2 Layout Example...................................................... 17
12 Device and Documentation Support..........................18
12.1 Related Documentation.......................................... 18
12.2 Receiving Notification of Documentation Updates..18
12.3 支持资源..................................................................18
12.4 Trademarks.............................................................18
12.5 Electrostatic Discharge Caution..............................18
12.6 术语表..................................................................... 18
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V.................6
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V.................6
6.8 Timing Requirements, VCC = 5 V ± 0.5 V....................7
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........8
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V.........8
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V............8
6.12 Operating Characteristics......................................... 8
6.13 Typical Characteristics..............................................9
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................11
Information.................................................................... 18
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (July 2022) to Revision A (December 2022)
Page
• 将数据表的状态从预告信息更改为“量产数据”.............................................................................................. 1
• Updated the Detailed Design Procedure section..............................................................................................16
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5 Pin Configuration and Functions
VCC
16
SH/LD
1
CLK
2
15 CLK INH
E
F
3
4
5
6
7
D
14
13
C
B
PAD
G
12
11
10
H
A
QH
SER
8
9
GND QH
图5-1. SN74LV165A: WBQB Package, 16-Pin WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
11
12
13
2
A
I
I
I
I
I
I
I
I
I
Serial input A
Serial input B
Serial input C
Storage clock
Storage clock
Serial input D
Serial input E
Serial input F
Serial input G
Ground pin
B
C
CLK
CLK INH
15
14
3
D
E
F
4
G
5
GND
H
8
—
6
I
Serial input H
Output H, inverted
Q H
7
O
O
QH
9
Output H
SH/ LD
SER
1
I
Load Input
10
16
I
Serial input
VCC
Power pin
—
—
Thermal pad
Thermal Pad(2)
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
(2) WBQB Package Only
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VCC
VI
Supply voltage
7
–0.5
–0.5
–0.5
–0.5
Input voltage(2)
7
7
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage (2) (3)
V
VCC + 0.5
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
–20
–50
±25
IOK
IO
Output clamp current
VO < 0
Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND
Storage temperature
±50
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
±4000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level
C4B
±2000
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
2
MAX
UNIT
VCC
VIH
Supply voltage
5.5
V
VCC = 2 V
1.5
High-level input voltage
V
V
VCC = 2.3 V to 5.5 V
VCC = 2 V
VCC × 0.7
0.5
VCC × 0.3
5.5
VIL
Low-level input voltage
VCC = 2.3 V to 5.5 V
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
–50
–2
VCC = 2 V
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level output current
Low-level output current
mA
–6
–12
50
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
IOL
6
mA
12
200
100
20
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
Δt/Δv
TA
125
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs.
6.4 Thermal Information
SN74LV165A-Q1
THERMAL METRIC(1)
UNIT
WBQB (WQFN)
16 PINS
86
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
82.6
54.9
9.5
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
54.9
32.5
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted).
PARAMETER
VCC
2 V to 5.5 V
2.3 V
MIN
VCC –0.1
2
TYP
MAX
UNIT
IOH = –50 mA
IOH = –2 mA
VOH
V
3 V
2.48
IOH = –6 mA
4.5 V
3.8
IOH = –12 mA
IOL = 50 mA
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
±1
IOL = 2 mA
VOL
V
IOL = 6 mA
3 V
IOL = 12 mA
4.5 V
II
VI = 5.5 V or GND
VI = VCC or GND, IO = 0
VI or VO = 0 to 5.5 V
VI = VCC or GND
0 V to 5.5 V
5.5 V
µA
µA
µA
pF
ICC
Ioff
Ci
20
0 V
5
3.3 V
1.7
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
25°C
–40°C to 125°C
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
MIN
MAX
CLK high or low
SH/ LD low
8.5
11
7
9
13
8.5
9.5
7
tw
Pulse duration
ns
SH/ LD high before CLK↑
SER before CLK↑
8.5
7
tsu
Setup time
Hold time
ns
ns
CLK INH before CLK↑
Data before SH/ LD↑
SER data after CLK↑
Parallel data after SH/ LD↑
SH/ LD high after CLK↑
12
0
11.5
-1
0
0
th
0
0
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
25°C
–40°C to 125°C
MIN MAX
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
CLK high or low
SH/ LD low
6
7.5
5
7
9
tw
Pulse duration
ns
6
SH/ LD high before CLK↑
SER before CLK↑
6
5
tsu
Setup time
Hold time
ns
ns
5
5
CLK INH before CLK↑
Data before SH/ LD↑
SER data after CLK↑
Parallel data after SH/ LD↑
SH/ LD high after CLK↑
8.5
0
7.5
0
0.5
0
th
0.5
0
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6.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
25°C
–40°C to 125°C
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
MIN
MAX
CLK high or low
SH/ LD low
4
5
4
6
tw
Pulse duration
ns
4
4
SH/ LD high before CLK↑
SER before CLK↑
4
4
tsu
Setup time
Hold time
ns
ns
3.5
5
3.5
5
CLK INH before CLK↑
Data before SH/ LD↑
SER data after CLK↑
Parallel data after SH/ LD↑
SH/ LD high after CLK↑
0.5
1
0.5
1
th
0.5
0.5
CLK
CLK INH
SER
L
SH/LD
A
H
L
B
C
H
Data
L
D
E
F
Inputs
H
L
H
H
G
H
L
L
L
Q
H
H
L
H
L
H
L
H
L
H
L
Q
H
H
H
H
Inhibit
Load
Serial Shift
图6-1. Typical Shift, Load, and Inhibit Sequences
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6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over operating free-air temperature range (unless otherwise noted), (see 图7-1)
25°C
–40°C to 125°C
MIN TYP MAX
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
UNIT
MIN
50
40
TYP
80
MAX
CL = 15 pF
CL = 50 pF
45
35
1
fmax
MHz
65
12.2
13.1
12.9
15.3
16.1
15.9
CLK
SH/ LD
H
19.8
22
tpd
QH or Q
QH or Q
CL = 15 pF
CL = 50 pF
21.5
21.7
23.3
25.1
25.3
1
23.5
24
ns
ns
1
CLK
SH/ LD
H
1
26
tpd
1
28
1
28
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over operating free-air temperature range (unless otherwise noted), (see 图7-1)
25°C
–40°C to 125°C
MIN TYP MAX
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
UNIT
MIN
65
60
TYP
115
MAX
CL = 15 pF
CL = 50 pF
55
50
1
fmax
MHz
90
8.6
CLK
SH/ LD
H
15.4
15.8
14.1
14.9
19.3
17.6
18
18.5
16.5
16.9
22
tpd
QH or Q
QH or Q
CL = 15 pF
CL = 50 pF
9.1
1
ns
ns
8.9
1
CLK
SH/ LD
H
10.9
11.3
11.1
1
tpd
1
1
20
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted), (see 图7-1)
25°C
–40°C to 125°C
MIN TYP MAX
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
UNIT
MIN
110
95
TYP
165
MAX
CL = 15 pF
CL = 50 pF
90
85
1
fmax
MHz
125
6
CLK
SH/ LD
H
9.9
11.5
11.5
10.5
13.5
13.5
12.5
tpd
QH or Q
QH or Q
CL = 15 pF
CL = 50 pF
6
9.9
9.9
1
ns
ns
6
1
CLK
SH/ LD
H
7.7
7.7
7.6
11.9
11.9
11
1
tpd
1
1
6.12 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
CL = 50 pF f = 10 MHz
VCC
TYP
UNIT
3.3 V
5 V
36.1
37.5
Cpd
Power dissipation capacitance
pF
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6.13 Typical Characteristics
16
15
14
13
12
11
10
9
CL=15pF
CL=50pF
8
7
6
2.5 2.75
3
3.25 3.5 3.75
Vcc(V)
4
4.25 4.5 4.75
5
D001
图6-2. TPD Typical (25°C) vs Vcc
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7 Parameter Measurement Information
V
CC
S1
Open
R
= 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
From Output
Under Test
GND
Point
t
t
Open
PLH PHL
C
C
L
(see Note A)
t
/t
PLZ PZL
V
L
(see Note A)
CC
/t
PHZ PZH
GND
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
Input
CC
CC
CC
CC
0 V
0 V
t
t
t
t
PZL
PLH
PHL
PLZ
Output
V
≈V
OH
CC
In-Phase
Output
Waveform 1
50% V
50% V
CC
50% V
CC
CC
V
V
+ 0.3 V
OL
S1 at V
CC
V
OL
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
50% V
CC
OH
Out-of-Phase
Output
V
− 0.3 V
OH
50% V
50% V
CC
CC
V
OL
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
INVERTING AND NONINVERTING OUTPUTS
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tr ≤3 ns,
and tf ≤3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis
.
F. tPZL and tPZH are the same as ten
.
G. tPHL and tPLH are the same as tpd
.
H. All parameters and waveforms are not applicable to all devices.
图7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV165A-Q1 device is a parallel-load, 8-bit shift registers designed for 2 V to 5.5 V VCC operation.
When the device is clocked, data is shifted toward the serial output QH. Parallel-in access to each stage is
provided by eight individual direct data inputs that are enabled by a low level at the shift/load (SH/ LD) input. The
SN74LV165A-Q1 features a clock-inhibit function and a complemented serial output, Q H.
Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/ LD is held high and clock
inhibit (CLK INH) is held low. The functions of CLK and CLK INH are interchangeable. Since a low CLK and a
low-to-high transition of CLK INH accomplishes clocking, CLK INH must be changed to the high level only while
CLK is high. Parallel loading is inhibited when SH/ LD is held high. The parallel inputs to the register are enabled
while SH/ LD is held low, independently of the levels of CLK, CLK INH, or SER.
The SN74LV165A-Q1 is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
8.2 Functional Block Diagram
A
H
B
C
D
E
F
G
SH/LD
5 Additional
Shift Register
Stages
S
D
R
Q
S
D
R
Q
S
D
R
Q
Q
QH
QH
SER
CLK INH
CLK
图8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads, so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
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8.3.2 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip-
flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
8.3.3 Partial Power Down (Ioff)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
8.3.4 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Standard Lead
We able Flank Lead
Pad
PCB
图8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with
automatic optical inspection (AOI). As shown in 图 8-2, a wettable flank can be dimpled or step-cut to provide
additional surface area for solder adhesion which assists in reliably creating a side fillet. See the mechanical
drawing for additional details.
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8.3.5 Clamp Diode Structure
图8-3 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
图8-3. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
The Operating Mode Table and the Output Function Table list the functional modes of the SN74LV165A-Q1.
表8-1. Operating Mode Table
INPUTS(1)
FUNCTION
SH/LD
CLK
CLK INH
L
X
H
X
X
X
H
Parallel load
No change
No change
Shift(2)
H
H
H
H
L
↑
L
Shift(2)
↑
(1) H = High Voltage Level, L = Low Voltage Level, X = Do Not
Care, ↑= Low to High transition
(2) Shift: content of each internal register shifts towards serial
output QH. Data at SER is shifted into the first register.
表8-2. Output Function Table
INTERNAL REGISTERS(1) (2)
OUTPUTS(2)
H
Q
Q
A —G
X
X
L
L
H
L
H
H
(1) Internal registers refer to the shift registers inside the device.
These values are set by either loading data from the parallel
inputs, or by clocking data in from the serial input.
(2) H = High Voltage Level, L = Low Voltage Level, X = Do Not Care
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
The SN74LV165A-Q1 is a low drive CMOS device that can be used for a multitude of bus interface type
applications where output ringing is a concern. The low-drive and slow-edge rates minimize overshoot and
undershoot on the outputs.
9.2 Typical Application
DATA[7:0]
A B C D E F G H
SH/LD
Data Loading Gates
QH
SER
8-Bit Shift Register
Peripheral
System
Controller
QH
CLK
Control
Logic
CLK INH
图9-1. Input Expansion with Shift Registers
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9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV165A-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV165A-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV165A-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74LV165A-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV165A-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74LV165A-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined
in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
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9.2.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LV165A-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.5 Application Curves
DATA[7:0]
SH/LD
CLK
0x00
0x11
0x00
QH
图9-2. Application Timing Diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC
terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for
best results.
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11 布局
11.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital
logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage
specifications, to prevent them from floating. The logic level that must be applied to any particular unused input
depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more
sense for the logic function or is more convenient.
11.2 Layout Example
VCC GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
0.1 F
VCC
16
SH/LD
1
Bypass capacitor
placed close to the
device
CLK INH
2
3
4
5
6
7
15
14
13
CLK
E
D
C
Unused input
tied to VCC
F
PAD
G
12 B
H
A
11
10
QH
SER
8
9
Unused output
left floating
Avoid 90°
corners for
signal lines
QH
GND
图11-1. Layout Example for the SN74LV165A-Q1 in the WBQB Package
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12 Device and Documentation Support
12.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Power-Up Behavior of Clocked Devices
• Texas Instruments, Introduction to Logic
12.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV165AQWBQBRQ1
ACTIVE
WQFN
BQB
16
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV165Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV165A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2023
Catalog : SN74LV165A
•
Enhanced Product : SN74LV165A-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV165AQWBQBRQ1 WQFN
BQB
16
3000
180.0
12.4
2.8
3.8
1.2
4.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
30-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
WQFN BQB 16
SPQ
Length (mm) Width (mm) Height (mm)
210.0 185.0 35.0
SN74LV165AQWBQBRQ1
3000
Pack Materials-Page 2
GENERIC PACKAGE VIEW
BQB 16
2.5 x 3.5, 0.5 mm pitch
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226161/A
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PACKAGE OUTLINE
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
A
2.6
2.4
B
PIN 1 INDEX AREA
3.6
3.4
0.1 MIN
(0.13)
SECTION A-A
TYPICAL
C
0.8 MAX
SEATING PLANE
0.05
0.00
0.08 C
1.1
0.9
2X 0.5
(0.2) TYP
9
8
10X 0.5
7
10
(0.16)
SYMM
SYMM
2X
2.5
17
2.1
1.9
0.3
16X
0.2
0.1
0.05
C A B
C
15
2
PIN 1 ID
(OPTIONAL)
1
16
0.5
0.3
16X
SYMM
4226135/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(1)
1
16
16X (0.6)
16X (0.25)
2
15
10X (0.5)
SYMM
17
(2)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
(Ø 0.2) VIA
TYP
8
9
2X (0.5)
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271)
.
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
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EXAMPLE STENCIL DESIGN
WQFN - 0.8 mm max height
INDSTNAME
BQB0016B
(2.3)
(0.95)
1
16
16X (0.6)
16X (0.25)
2
15
17
10X (0.5)
SYMM
(1.79)
(3.3)
2X (0.75)
10
7
(R0.05) TYP
METAL TYP
8
9
2X (0.5)
SYMM
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
85% PRINTED COVERAGE BY AREA
SCALE: 20X
4226135/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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