SN74LV166ADR [TI]
8-BIT PARALLEL-LOAD SHIFT REGISTERS; 8位并联负载移位寄存器
| 型号： | SN74LV166ADR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 8-BIT PARALLEL-LOAD SHIFT REGISTERS |
| 文件： | 总15页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢇ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢆꢇ ꢇꢈ
ꢌꢍꢎ ꢏ ꢐꢈꢑꢈ ꢄꢄ ꢒꢄ ꢌꢄ ꢓ ꢈꢔ ꢀꢕꢎ ꢖ ꢏ ꢑꢒꢗ ꢎ ꢀ ꢏꢒ ꢑꢀ
ꢋ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
D
D
D
2-V to 5.5-V V
Operation
D
D
D
Direct Overriding Clear
CC
Max t of 10.5 ns at 5 V
Parallel-to-Serial Conversion
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
OLP
CC
= 3.3 V, T = 25°C
A
D
D
D
Typical V
>2.3 V at V
(Output V
Undershoot)
D
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
OHV
CC
OH
= 3.3 V, T = 25°C
A
I
Supports Partial-Power-Down-Mode
off
− 1000-V Charged-Device Model (C101)
Operation
Synchronous Load
SN54LV166A . . . J OR W PACKAGE
SN74LV166A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
SN54LV166A . . . FK PACKAGE
(TOP VIEW)
SER
V
CC
SH/LD
H
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A
3
2
1 20 19
18
B
C
H
Q
B
4
5
6
7
8
Q
H
G
C
NC
17
16
15
14
H
D
NC
G
CLK INH
CLK
F
D
E
F
CLK INH
9 10 11 12 13
GND
CLR
NC − No internal connection
description/ordering information
The ’LV166A devices are 8-bit parallel-load shift registers, designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 40
SN74LV166AD
SOIC − D
LV166A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV166ADR
SN74LV166ANSR
SN74LV166ADBR
SN74LV166APW
SN74LV166APWR
SN74LV166APWT
SN74LV166ADGVR
SNJ54LV166AJ
SOP − NS
74LV166A
LV166A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV166A
TVSOP − DGV
CDIP − J
LV166A
SNJ54LV166AJ
SNJ54LV166AW
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV166AW
SNJ54LV166AFK
LCCC − FK
SNJ54LV166AFK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2004, Texas Instruments Incorporated
ꢘ ꢁ ꢄꢒꢀꢀ ꢓ ꢏꢕ ꢒꢑꢙ ꢎꢀ ꢒ ꢁ ꢓꢏꢒꢔ ꢚꢛ ꢜꢝ ꢞꢟꢠ ꢡꢢꢣ ꢤꢚ ꢠꢟ ꢤꢚꢥ ꢜꢤꢝ ꢐꢑ ꢓ ꢔ ꢘ ꢦꢏ ꢎꢓ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢇꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢐꢈ ꢑꢈ ꢄ ꢄ ꢒꢄ ꢌꢄꢓ ꢈꢔ ꢀ ꢕꢎ ꢖ ꢏ ꢑꢒ ꢗ ꢎꢀ ꢏꢒ ꢑꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
description/ordering information (continued)
The ’LV166A parallel-in or serial-in, serial-out registers feature gated clock (CLK, CLK INH) inputs and an
overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input.
When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each
clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs
on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the
low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a
clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low
enables the other clock input. This allows the system clock to be free running, and the register can be stopped
on command with the other clock input. CLK INH should be changed to the high level only when CLK is high.
CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
OUTPUTS
INPUTS
INTERNAL
Q
PARALLEL
A . . . H
H
CLK INH CLK
SER
Q
Q
B
CLR
SH/LD
A
L
X
X
L
X
L
L
L
L
H
X
L
↑
↑
↑
↑
X
X
X
H
L
X
L
L
L
H
H
H
H
H
X
Q
Q
Q
H0
h
A0
B0
a . . . h
a
H
L
b
H
H
X
X
X
X
Q
Q
Gn
Q
Gn
Q
H0
An
An
B0
Q
Q
X
Q
A0
2
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ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢇꢈ
ꢖ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐ
ꢈ
ꢑ
ꢈ
ꢄꢄ
ꢒ
ꢄ
ꢌ
ꢄ
ꢓ
ꢈ
ꢔ
ꢀ
ꢕ
ꢎ
ꢏ
ꢑ
ꢒ
ꢗ
ꢎ
ꢀ
ꢏ
ꢒ
ꢑ
ꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
logic diagram (positive logic)
A
B
C
D
E
F
G
H
2
3
4
5
10
11
12
14
15
1
SH/LD
SER
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
1D
C1
R
6
7
CLK INH
CLK
9
13
CLR
Q
H
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
typical clear, shift, load, inhibit, and shift sequence
CLK
CLK INH
CLR
SER
SH/LD
A
H
L
B
C
H
L
D
Parallel
Inputs
E
H
L
F
G
H
H
H
L
L
L
H
H
H
H
H
Q
H
Inhibit
Serial Shift
Serial Shift
Clear
Load
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢇꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢐꢈ ꢑꢈ ꢄ ꢄ ꢒꢄ ꢌꢄꢓ ꢈꢔ ꢀ ꢕꢎ ꢖ ꢏ ꢑꢒ ꢗ ꢎꢀ ꢏꢒ ꢑꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range applied in high or low state, V (see Notes 1 and 2) . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Voltage range applied to any output in the power-off state, V (see Note 1) . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢇꢈ
ꢖ
ꢋ
ꢌ
ꢍ
ꢎ
ꢏ
ꢐꢈ
ꢑ
ꢈ
ꢄꢄ
ꢒ
ꢄ
ꢌ
ꢄ
ꢓ
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ꢎ
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ꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
recommended operating conditions (see Note 4)
SN54LV166A
SN74LV166A
MIN MAX
UNIT
MIN
2
MAX
V
V
Supply voltage
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
× 0.7
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
× 0.3
× 0.3
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−55
125
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV166A
SN74LV166A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.6
1.6
i
I
CC
ꢐ
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ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
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ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢇꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢐꢈ ꢑꢈ ꢄ ꢄ ꢒꢄ ꢌꢄꢓ ꢈꢔ ꢀ ꢕꢎ ꢖ ꢏ ꢑꢒ ꢗ ꢎꢀ ꢏꢒ ꢑꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV166A SN74LV166A
A
UNIT
MIN
8
MAX
MIN
9
MAX
MIN
9
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
8.5
7
9
9
CLK INH before CLK↑
Data before CLK↑
SH/LD before CLK↑
SER before CLK↑
CLR↑ inactive before CLK↑
Data after CLK↑
7
7
6.5
7
8.5
8.5
9.5
7
8.5
8.5
9.5
7
t
t
ns
ns
Setup time
Hold time
su
8.5
6
−0.5
0
0
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV166A SN74LV166A
A
UNIT
MIN
6
MAX
MIN
7
MAX
MIN
7
MAX
CLR low
t
w
Pulse duration
ns
CLK high or low
6
7
7
CLK INH before CLK↑
Data before CLK↑
SH/LD before CLK↑
SER before CLK↑
CLR↑ inactive before CLK↑
Data after CLK↑
5
5
5
5
6
6
5
6
6
t
t
ns
ns
Setup time
Hold time
su
5
6
6
4
4
4
0
0
0
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV166A SN74LV166A
A
UNIT
MIN
5
MAX
MIN
5
MAX MIN4
MAX
CLR low
5
4
t
w
Pulse duration
ns
CLK high or low
4
4
CLK INH before CLK↑
Data before CLK↑
SH/LD before CLK↑
SER before CLK↑
CLR↑ inactive before CLK↑
Data after CLK↑
3.5
4.5
4
3.5
4.5
4
3.5
4.5
4
t
t
ns
ns
Setup time
Hold time
su
4
4
4
3.5
1
3.5
1
3.5
1
h
ꢐ
ꢑ
ꢓ
ꢔ
ꢘ
ꢦ
ꢏ
ꢐ
ꢑ
ꢒ
ꢅ
ꢎ
ꢒ
ꢙ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢞ
ꢣ
ꢝ
ꢣ
ꢥ
ꢜ
ꢠ
ꢤ
ꢰ
ꢤ
ꢩ
ꢛ
ꢤ
ꢞ
ꢥ
ꢝ
ꢝ
ꢠ
ꢣ
ꢥ
ꢟ
ꢟ
ꢧ
ꢞ
ꢣ
ꢤ
ꢱ
ꢣ
ꢰ
ꢝ
ꢫ
ꢟ
ꢟ
ꢥ
ꢣ
ꢩ
ꢫ
ꢩ
ꢢ
ꢣ
ꢏ
ꢞ
ꢤ
ꢣ
ꢡ
ꢚ
ꢬ
ꢭ
ꢠ
ꢦ
ꢛ
ꢤ
ꢜ
ꢥ
ꢝ
ꢚ
ꢨ
ꢚ
ꢛ
ꢥ
ꢠ
ꢚ
ꢢ
ꢣ
ꢨ
ꢣ
ꢤ
ꢜ
ꢤ
ꢝ
ꢚ
ꢟ
ꢚ
ꢝ
ꢚ
ꢜ
ꢠ
ꢨ
ꢠ
ꢞ
ꢥ
ꢨ
ꢚ
ꢱ
ꢥ
ꢣ
ꢥ
ꢤ
ꢣ
ꢞ
ꢟ
ꢚ
ꢛ
ꢚ
ꢣ
ꢨ
ꢝ
ꢩ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢨ
ꢣ
ꢞ
ꢣ
ꢡ
ꢝ
ꢜ
ꢰ
ꢝ
ꢬ
ꢥ
ꢚ
ꢝ
ꢎ
ꢨ
ꢡ
ꢣ
ꢝ
ꢣ
ꢝ
ꢚ
ꢛ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢟ
ꢠ
ꢛ
ꢰ
ꢣ
ꢟ
ꢨ
ꢜ
ꢝ
ꢤ
ꢚ
ꢜ
ꢤ
ꢣ
ꢚ
ꢛ
ꢣ
ꢨ
ꢟ
ꢝ
ꢮ
ꢟ
ꢡ
ꢚ
ꢜ
ꢣ
ꢬ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢇ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢇꢈ
ꢋ ꢌꢍꢎ ꢏ ꢐꢈꢑꢈ ꢄꢄ ꢒꢄ ꢌꢄ ꢓ ꢈꢔ ꢀꢕ ꢎꢖ ꢏ ꢑꢒꢗ ꢎ ꢀ ꢏꢒ ꢑꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
105*
80
SN54LV166A SN74LV166A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50*
40
MAX
MIN
45*
35
MAX
MIN
45
35
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
8.8*
16*
1*
18*
22*
22
18
22
22
26
CLR
CLK
CLR
CLK
PHL
C
C
= 15 pF
= 50 pF
ns
ns
Q
H
L
L
9.2* 19.8*
1*
1
1
1
1
pd
11.3
11.8
19.5
23.3
PHL
pd
Q
H
1
26
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV166A SN74LV166A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
65*
60
MAX
MIN
55*
50
MAX
MIN
55
50
1
MAX
C
C
= 15 pF
= 50 pF
150*
120
L
L
f
MHz
max
t
t
t
t
6.3* 12.5*
6.6* 15.4*
1*
15*
18*
15
18
CLR
CLK
CLR
CLK
PHL
C
C
= 15 pF
= 50 pF
ns
ns
Q
H
L
L
1*
1
1
1
1
pd
7.9
8.3
16.3
18.9
18.5
21.5
18.5
21.5
PHL
pd
Q
H
1
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
205*
160
SN54LV166A SN74LV166A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
110*
95
MAX
MIN
90*
85
MAX
MIN
90
85
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
t
t
t
t
4.6*
8.6*
9.9*
10.6
11.9
1*
10*
10
11.5
12
CLR
CLK
CLR
CLK
PHL
C
C
= 15 pF
= 50 pF
ns
ns
Q
H
L
L
4.8*
5.7
6.1
1* 11.5*
1
1
1
pd
1
1
12
PHL
pd
Q
H
13.5
13.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
39.1
44.5
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
ꢐ
ꢑ
ꢓ
ꢔ
ꢘ
ꢦ
ꢏ
ꢐ
ꢑ
ꢒ
ꢅ
ꢎ
ꢒ
ꢙ
ꢜ
ꢤ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢠ
ꢟ
ꢤ
ꢠ
ꢣ
ꢨ
ꢤ
ꢝ
ꢩ
ꢨ
ꢟ
ꢞ
ꢡ
ꢞꢣ ꢝ ꢜ ꢰꢤ ꢩꢛ ꢥ ꢝ ꢣ ꢟꢧ ꢞꢣ ꢱ ꢣ ꢫꢟ ꢩꢢꢣ ꢤꢚꢬ ꢦ ꢛꢥ ꢨꢥ ꢠꢚ ꢣꢨ ꢜꢝ ꢚꢜ ꢠ ꢞꢥ ꢚꢥ ꢥꢤ ꢞ ꢟꢚ ꢛꢣꢨ
ꢠ
ꢚ
ꢝ
ꢜ
ꢤ
ꢚ
ꢛ
ꢣ
ꢧ
ꢟ
ꢨ
ꢢ
ꢥ
ꢚ
ꢜ
ꢱ
ꢣ
ꢟ
ꢨ
ꢝ
ꢩ
ꢣ
ꢠ
ꢜ
ꢧ
ꢜ
ꢠ
ꢥ
ꢚ
ꢜ
ꢟ
ꢤ
ꢝ
ꢥ
ꢨ
ꢣ
ꢞ
ꢣ
ꢝ
ꢜ
ꢰ
ꢤ
ꢰ
ꢟ
ꢥ
ꢫ
ꢝ
ꢬ
ꢏ
ꢣ
ꢭ
ꢥ
ꢝ
ꢎ
ꢤ
ꢝ
ꢚ
ꢨ
ꢡ
ꢢ
ꢣ
ꢤ
ꢠ ꢛꢥ ꢤ ꢰꢣ ꢟꢨ ꢞꢜ ꢝ ꢠ ꢟꢤ ꢚꢜ ꢤꢡꢣ ꢚ ꢛꢣ ꢝ ꢣ ꢩꢨ ꢟꢞ ꢡꢠꢚ ꢝ ꢮ ꢜꢚꢛ ꢟꢡꢚ ꢤꢟꢚ ꢜꢠꢣ ꢬ
ꢚ
ꢝ
ꢨ
ꢣ
ꢝ
ꢣ
ꢨ
ꢱ
ꢣ
ꢝ
ꢚ
ꢛ
ꢣ
ꢨ
ꢜ
ꢰ
ꢛ
ꢚ
ꢚ
ꢟ
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢇꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢇ ꢈ
ꢋꢌ ꢍꢎ ꢏ ꢐꢈ ꢑꢈ ꢄ ꢄ ꢒꢄ ꢌꢄꢓ ꢈꢔ ꢀ ꢕꢎ ꢖ ꢏ ꢑꢒ ꢗ ꢎꢀ ꢏꢒ ꢑꢀ
SCLS456B − FEBRUARY 2001 − REVISED DECEMBER 2004
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
PLZ
PZL
t
t
t
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
OL
+ 0.3 V
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
SN74LV166AD
Status (1)
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
16
16
40
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SN74LV166ADB
SN74LV166ADBR
SN74LV166ADGVR
SN74LV166ADR
SN74LV166ANSR
SN74LV166APW
SN74LV166APWR
SN74LV166APWT
SSOP
SSOP
TVSOP
SOIC
DB
DB
80
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
2000
2000
2500
2000
90
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
DGV
D
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
SO
NS
Pb-Free
(RoHS)
CU NIPDAU Level-2-260C-1 YEAR/
Level-1-235C-UNLIM
TSSOP
TSSOP
TSSOP
PW
PW
PW
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
CU NIPDAU Level-1-250C-UNLIM
2000
250
Pb-Free
(RoHS)
Pb-Free
(RoHS)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
UL1042
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