SN74LV174A_07_技术文档

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SCLS401G − APRIL 1998 − REVISED APRIL 2005

SN54LV174A . . . J OR W PACKAGE

SN74LV174A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

D

2-V to 5.5-V V

Operation

CC

Max t of 8.5 ns at 5 V

pd

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

= 3.3 V, T = 25°C

1

2

3

4

5

6

7

8

16

15

14

13

12

11

10

9

CLR

1Q

1D

2D

2Q

3D

3Q

GND

V

CC

A

6Q

6D

5D

5Q

4D

4Q

CLK

Typical V

>2.3 V at V

(Output V

Undershoot)

OHV

CC

OH

= 3.3 V, T = 25°C

A

Support Mixed-Mode Voltage Operation on

All Ports

Latch-Up Performance Exceeds 250 mA Per

JESD 17

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54LV174A . . . FK PACKAGE

(TOP VIEW)

− 1000-V Charged-Device Model (C101)

description/ordering information

3

2

1 20 19

18 6D

The ’LV174A devices are hex D-type flip-flops

1D

2D

NC

2Q

3D

4

5

6

7

8

designed for 2-V to 5.5-V V

operation.

CC

17

5D

NC

5Q

4D

These devices are positive-edge-triggered

flip-flops with a direct clear (CLR) input.

Information at the data (D) inputs meeting the

setup time requirements is transferred to the

outputs on the positive-going edge of the clock

pulse. Clock triggering occurs at a particular

voltage level and is not directly related to the

transition time of the positive-going edge of the

clock pulse. When the clock (CLK) input is at

either the high or low level, the D-input signal has

no effect at the output.

16

15

14

9 10 11 12 13

NC − No internal connection

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

Tube of 40

SN74LV174AD

SOIC − D

LV174A

Reel of 2500

Reel of 2000

Tube of 90

SN74LV174ADR

SN74LV174ANSR

SN74LV174ADBR

SN74LV174APW

SN74LV174APWR

SN74LV174APWT

SN74LV174ADGVR

SNJ54LV174AJ

SOP − NS

74LV174A

LV174A

SSOP − DB

−40°C to 85°C

Reel of 2000

Reel of 250

Reel of 2000

Tube of 25

TSSOP − PW

LV174A

TVSOP − DGV

CDIP − J

LV174A

SNJ54LV174AJ

SNJ54LV174AW

SNJ54LV174AFK

−55°C to 125°C

CFP − W

Tube of 150

Tube of 55

SNJ54LV174AW

SNJ54LV174AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2005, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ

ꢊ ꢋꢌ ꢍ ꢎꢏ ꢐꢑꢋ ꢒ ꢄ ꢓ ꢑ ꢎꢒꢄꢔ ꢑ ꢀ

ꢕꢓ ꢏ ꢊ ꢖ ꢄ ꢋꢈ ꢗ

SCLS401G − APRIL 1998 − REVISED APRIL 2005

FUNCTION TABLE

INPUTS

OUTPUT

Q

CLR

L

CLK

X

D

X

H

L

H

L

H

↑

H

↑

H

L

X

Q

0

logic diagram (positive logic)

1

CLR

9

CLK

3

1D

C1

2

1Q

R

To Five Other Channels

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high-impedance

or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V

+ 0.5 V

CC

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA

IK

OK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

O

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA

Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

JA

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢊꢋꢌ ꢍꢎꢏ ꢐꢑ ꢋ ꢒ ꢄꢓ ꢑ ꢎꢒ ꢄꢔ ꢑꢀ

ꢕ ꢓꢏ ꢊ ꢖ ꢄꢋ ꢈꢗ

SCLS401G − APRIL 1998 − REVISED APRIL 2005

recommended operating conditions (see Note 4)

SN54LV174A

SN74LV174A

UNIT

MIN

2

MAX

MIN

2

MAX

V

Supply voltage

5.5

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

1.5

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2 V

V

× 0.7

V

× 0.7

CC

High-level input voltage

V

IH

× 0.7

0.5

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

V

× 0.3

V

× 0.3

5.5

CC

V

IL

Low-level input voltage

× 0.3

5.5

V

Input voltage

0

V

I

Output voltage

V

CC

O

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

−50

−2

−50

−2

−6

−12

50

2

µA

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2 V

I

High-level output current

Low-level output current

OH

OL

−6

mA

−12

50

µA

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

2

I

6

mA

12

200

100

20

85

200

100

20

∆t/∆v Input transition rise or fall rate

ns/V

T

Operating free-air temperature

−55

125

−40

°C

A

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

CC

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LV174A

SN74LV174A

PARAMETER

TEST CONDITIONS

UNIT

V

CC

MIN

−0.1

2

TYP

MAX

MIN

−0.1

2

TYP

MAX

I

= −50 µA

= −2 mA

= −6 mA

= −12 mA

= 50 µA

= 2 mA

2 V to 5.5 V

2.3 V

V

CC

V

CC

OH

OL

V

OH

3 V

2.48

3.8

2.48

3.8

4.5 V

2 V to 5.5 V

2.3 V

0.1

0.4

0.44

0.55

1

0.1

0.4

0.44

0.55

1

V

OL

= 6 mA

3 V

= 12 mA

4.5 V

I

V = 5.5 V or GND

0 to 5.5 V

5.5 V

µA

pF

I

V = V

CC

or GND,

I = 0

O

20

CC

off

I

V or V = 0 to 5.5 V

0

5

I

O

C

V = V

or GND

3.3 V

1.7

i

I

CC

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3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ

ꢊ ꢋꢌ ꢍ ꢎꢏ ꢐꢑꢋ ꢒ ꢄ ꢓ ꢑ ꢎꢒꢄꢔ ꢑ ꢀ

ꢕꢓ ꢏ ꢊ ꢖ ꢄ ꢋꢈ ꢗ

SCLS401G − APRIL 1998 − REVISED APRIL 2005

timing requirements over recommended operating free-air temperature range, V

(unless otherwise noted) (see Figure 1)

= 2.5 V 0.2 V

CC

T

A

= 25°C

SN54LV174A SN74LV174A

UNIT

MIN

6

TYP

MAX

MIN

6.5

7

MAX

MIN

6.5

7

MAX

CLR low

t

Pulse duration

ns

w

CLK high or low

Data

7

8.5

4

9.5

4

9.5

4

t

ns

Setup time before CLK↑

su

CLR inactive

Hold time, data after CLK↑

−0.5

0

h

timing requirements over recommended operating free-air temperature range, V

(unless otherwise noted) (see Figure 1)

= 3.3 V 0.3 V

CC

T

A

= 25°C

SN54LV174A SN74LV174A

UNIT

MIN

5

TYP

MAX

MIN

5

MAX

MIN

5

MAX

CLR low

t

Pulse duration

ns

w

CLK high or low

Data

5

6

t

ns

Setup time before CLK↑

su

CLR inactive

3

Hold time, data after CLK↑

0

h

timing requirements over recommended operating free-air temperature range, V

(unless otherwise noted) (see Figure 1)

= 5 V 0.5 V

CC

T

A

= 25°C

SN54LV174A SN74LV174A

UNIT

MIN

5

TYP

MAX

MIN

5

MAX

MIN

5

MAX

CLR low

t

Pulse duration

ns

w

CLK high or low

Data

5

4.5

2.5

0.5

4.5

2.5

0.5

4.5

2.5

0.5

t

ns

Setup time before CLK↑

su

CLR inactive

Hold time, data after CLK↑

h

switching characteristics over recommended operating free-air temperature range,

V

= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

115*

90

SN54LV174A SN74LV174A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MHz

ns

MIN

55*

45

MAX

MIN

50*

40

MAX

MIN

50

40

1

MAX

C

= 15 pF

= 50 pF

L

f

max

pd

CLR

CLK

CLR

CLK

6.3* 17.3*

8.4* 17.1*

1* 19.5*

19.5

19

Q

C

= 15 pF

t

L

1*

1

19*

23.5

23

1

8.2

21.9

20.6

2

1

23.5

23

t

pd

10.8

1

C

= 50 pF

ns

L

2

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

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ꢟ ꢚ ꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠ ꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞ ꢝꢠꢟ ꢙꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ

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4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢃ ꢈꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆꢇ ꢃꢈ

ꢊꢋꢌ ꢍꢎꢏ ꢐꢑ ꢋ ꢒ ꢄꢓ ꢑ ꢎꢒ ꢄꢔ ꢑꢀ

ꢕ ꢓꢏ ꢊ ꢖ ꢄꢋ ꢈꢗ

SCLS401G − APRIL 1998 − REVISED APRIL 2005

switching characteristics over recommended operating free-air temperature range,

V

= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

SN54LV174A SN74LV174A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MHz

ns

MIN

95*

55

MAX

MIN

80*

50

MAX

MIN

80

50

1

MAX

C

= 15 pF

= 50 pF

170*

130

L

f

max

pd

CLR

CLK

CLR

CLK

4.5* 11.4*

1* 13.5*

13.5

13

Q

C

= 15 pF

t

L

5.8*

6

11*

14.9

14.5

1.5

1*

1

13*

17

1

17

t

pd

7.5

1

16.5

1

16.5

1.5

C

= 50 pF

ns

L

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

V

= 5 V 0.5 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

240*

180

3*

SN54LV174A SN74LV174A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MHz

ns

MIN

130*

90

MAX

MIN

110*

80

1*

MAX

MIN

110

80

1

MAX

C

= 15 pF

= 50 pF

L

f

max

pd

CLR

CLK

CLR

CLK

7.6*

7.2*

9.6

9.2

1

9*

8.5*

11

9

8.5

11

Q

C

= 15 pF

t

L

4.1*

4.2

1*

1

t

pd

5.5

1

10.5

1

10.5

1

C

= 50 pF

ns

L

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

noise characteristics, V

= 3.3 V, C = 50 pF, T = 25°C (see Note 5)

CC

L

A

SN74LV174A

PARAMETER

UNIT

MIN

TYP

0.34

−0.3

3.02

MAX

V

Quiet output, maximum dynamic V

0.8

V

OL(P)

OL(V)

OH(V)

IH(D)

IL(D)

OL

Quiet output, minimum dynamic V

High-level dynamic input voltage

Low-level dynamic input voltage

−0.8

OL

OH

2.31

0.99

NOTE 5: Characteristics are for surface-mount packages only.

operating characteristics, T = 25°C

A

PARAMETER

TEST CONDITIONS

= 50 pF, f = 10 MHz

L

V

TYP

14

UNIT

CC

3.3 V

C

Power dissipation capacitance

C

pF

pd

5 V

15.1

ꢑ

ꢗ

ꢔ

ꢍ

ꢘ

ꢖ

ꢏ

ꢑ

ꢗ

ꢋ

ꢅ

ꢓ

ꢋ

ꢕ

ꢛ

ꢣ

ꢥ

ꢞ

ꢦ

ꢡ

ꢤ

ꢙ

ꢛ

ꢞ

ꢣ

ꢟ

ꢞ

ꢣ

ꢟ

ꢢ

ꢦ

ꢣ

ꢜ

ꢧ

ꢦ

ꢞ

ꢝ

ꢠ

ꢝꢢ ꢜ ꢛ ꢮꢣ ꢧꢚ ꢤ ꢜ ꢢ ꢞꢥ ꢝꢢ ꢯ ꢢ ꢩꢞ ꢧꢡꢢ ꢣꢙꢪ ꢖ ꢚꢤ ꢦꢤ ꢟꢙ ꢢꢦ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢦ

ꢟ

ꢙ

ꢜ

ꢛ

ꢣ

ꢙ

ꢚ

ꢢ

ꢥ

ꢞ

ꢦ

ꢡ

ꢤ

ꢙ

ꢛ

ꢯ

ꢢ

ꢞ

ꢦ

ꢜ

ꢧ

ꢢ

ꢟ

ꢛ

ꢥ

ꢛ

ꢟ

ꢤ

ꢙ

ꢛ

ꢞ

ꢣ

ꢜ

ꢤ

ꢦ

ꢢ

ꢝ

ꢢ

ꢜ

ꢛ

ꢮ

ꢣ

ꢮ

ꢞ

ꢤ

ꢩ

ꢜ

ꢪ

ꢏ

ꢢ

ꢫ

ꢤ

ꢜ

ꢓ

ꢣ

ꢜ

ꢙ

ꢦ

ꢠ

ꢡ

ꢢ

ꢣ

ꢟ ꢚꢤ ꢣ ꢮꢢ ꢞꢦ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢧꢦ ꢞꢝ ꢠꢟꢙ ꢜ ꢬ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢪ

ꢙ

ꢜ

ꢦ

ꢢ

ꢜ

ꢢ

ꢦ

ꢯ

ꢢꢜ

ꢙ

ꢚ

ꢢ

ꢦ

ꢛ

ꢮ

ꢚ

ꢙ

ꢞ

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢃꢈ ꢉ ꢀꢁ ꢇꢃ ꢄꢅ ꢆ ꢇꢃ ꢈ

ꢊ ꢋꢌ ꢍ ꢎꢏ ꢐꢑꢋ ꢒ ꢄ ꢓ ꢑ ꢎꢒꢄꢔ ꢑ ꢀ

ꢕꢓ ꢏ ꢊ ꢖ ꢄ ꢋꢈ ꢗ

SCLS401G − APRIL 1998 − REVISED APRIL 2005

PARAMETER MEASUREMENT INFORMATION

V

CC

Open

S1

R

= 1 kΩ

L

TEST

S1

From Output

Under Test

Test

Point

From Output

Under Test

GND

t

/t

Open

PLH PHL

/t

C

L

t

V

CC

L

PLZ PZL

/t

(see Note A)

GND

PHZ PZH

Open Drain

V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

3-STATE AND OPEN-DRAIN OUTPUTS

V

CC

50% V

CC

Timing Input

0 V

t

w

t

h

t

V

CC

su

V

CC

50% V

CC

50% V

CC

Input

50% V

CC

50% V

CC

Data Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V

CC

Output

Control

50% V

CC

50% V

CC

50% V

CC

0 V

t

PLZ

PLH

PHL

PZL

Output

Waveform 1

V

≈V

OH

CC

In-Phase

Output

50% V

CC

50% V

CC

V

OL

+ 0.3 V

S1 at V

(see Note B)

CC

V

OL

t

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

V

OH

Out-of-Phase

Output

V

OH

− 0.3 V

50% V

CC

50% V

CC

≈0 V

V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.

O

r

f

D. The outputs are measured one at a time, with one input transition per measurement.

E.

F.

G.

t

and t

PLH

are the same as t

.

dis

PLZ

PZL

PHL

PHZ

PZH

are the same as t

.

en

are the same as t .

pd

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,

improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.

Customers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment.

TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s

standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this

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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and

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interface.ti.com

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power.ti.com

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www.ti.com/video

www.ti.com/wireless

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jun-2007

PACKAGING INFORMATION

Orderable Device

SN74LV174AD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV174ADBR

SN74LV174ADBRE4

SN74LV174ADBRG4

SN74LV174ADE4

SN74LV174ADG4

SN74LV174ADGVR

SN74LV174ADGVRE4

SN74LV174ADGVRG4

SN74LV174ADR

SSOP

SOIC

TVSOP

SOIC

SO

DB

D

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

DGV

D

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV174ADRE4

SN74LV174ADRG4

SN74LV174ANSR

SN74LV174ANSRE4

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

NS

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV174ANSRG4

SN74LV174APW

ACTIVE

SO

NS

16

2000

TBD

Call TI

TSSOP

PW

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV174APWE4

SN74LV174APWG4

SN74LV174APWR

SN74LV174APWRE4

SN74LV174APWRG4

SN74LV174APWT

ACTIVE

TSSOP

PW

16

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV174APWTE4

SN74LV174APWTG4

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

1-Jun-2007

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

TAPE AND REEL INFORMATION

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Device

Package Pins

Site

Reel

A0 (mm)

B0 (mm)

K0 (mm)

P1

W

Pin1

Diameter Width

(mm) (mm) Quadrant

(mm)

330

0

(mm)

16

SN74LV174ADBR

SN74LV174ADGVR

SN74LV174ADR

DB

DGV

D

16

MLA

FMX

MLA

8.2

6.8

6.5

8.2

7.0

6.6

4.0

2.5

1.6

12

8

16

12

Q1

12

16

10.3

10.5

5.6

12.1

2.5

2

SN74LV174ANSR

SN74LV174APWR

NS

330

16

12

8

PW

12

1.6

TAPE AND REEL BOX INFORMATION

Device

Package

Pins

Site

Length (mm) Width (mm) Height (mm)

SN74LV174ADBR

SN74LV174ADGVR

SN74LV174ADR

DB

DGV

D

16

MLA

FMX

MLA

342.9

338.1

342.9

338.1

336.6

340.5

336.6

340.5

28.58

20.64

28.58

20.64

SN74LV174ANSR

SN74LV174APWR

NS

PW

Pack Materials-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

19-May-2007

Pack Materials-Page 3

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**)

PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,30

0,19

M

0,10

0,65

14

8

0,15 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

1

7

0°–8°

A

0,75

0,50

Seating Plane

0,10

0,15

0,05

1,20 MAX

PINS **

8

14

16

20

24

28

DIM

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

9,80

9,60

A MAX

A MIN

7,70

4040064/F 01/97

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-153