SN74LV175ANSE4 [TI]
LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOP-16;
| 型号： | SN74LV175ANSE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO16, PLASTIC, SOP-16 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总12页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
SN54LV175A . . . J OR W PACKAGE
SN74LV175A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
CLR
1Q
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Typical V
>2.3 V at V
(Output V
Undershoot)
4Q
4Q
4D
3D
3Q
3Q
CLK
OHV
CC
OH
= 3.3 V, T = 25°C
1Q
1D
A
2-V to 5.5-V V
Operation
CC
2D
2Q
Support Mixed-Mode Voltage Operation on
All Ports
2Q
GND
Contain Four Flip-Flops With Double-Rail
Outputs
Applications Include:
– Buffer/Storage Registers
– Shift Registers
SN54LV175A . . . FK PACKAGE
(TOP VIEW)
– Pattern Generators
Latch-Up Performance Exceeds 250 mA Per
JESD 17
3
2 1 20 19
18 4Q
1Q
1D
NC
2D
2Q
4
5
6
7
8
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
17
4D
NC
3D
3Q
16
15
14
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
9 10 11 12 13
NC – No internal connection
description
The ’LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V V
operation.
CC
These devices have a direct clear (CLR) input and feature complementary outputs from each flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the
positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition time of the
positive-going edge of CLK. When CLK is at either the high or low level, the D input has no effect at the output.
The SN54LV175A is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74LV175A is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
FUNCTION TABLE
(each flip-flop)
INPUTS
CLK
OUTPUTS
CLR
D
X
H
L
Q
L
Q
H
L
L
H
H
H
X
↑
H
L
↑
H
L
X
Q
Q
0
0
†
logic symbol
1
9
R
CLR
CLK
C1
2
3
1Q
1Q
4
1D
2D
3D
4D
1D
7
2Q
2Q
3Q
5
6
10
11
15
14
12
13
3Q
4Q
4Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
1
CLR
9
CLK
4
2
3
1D
C1
1D
1Q
R
1Q
To Three Other Channels
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
O
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
OK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
recommended operating conditions (see Note 4)
SN54LV175A
MIN MAX
SN74LV175A
MIN MAX
UNIT
V
V
Supply voltage
2
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
5.5
V
CC
V
CC
V
CC
× 0.3
× 0.3
× 0.3
5.5
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
V
V
I
Output voltage
0
V
0
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–6
–12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–6
mA
µA
–12
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV175A
SN74LV175A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
V
–0.1
2
V
CC
–0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= –2 mA
= –6 mA
= –12 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
±1
0.1
0.4
0.44
0.55
±1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = V
or GND
or GND,
0 V to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
CC
CC
V = V
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0 V
5
5
I
O
C
V = V
or GND
3.3 V
1.4
1.4
i
I
CC
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V ± 0.2 V
CC
T
= 25°C
SN54LV175A SN74LV175A
A
UNIT
MIN
6
MAX
MIN
6
MAX
MIN
6
MAX
CLR low
t
Pulse duration
ns
w
CLK high or low
Data
6.5
7
7
7
7.5
7.5
1
7.5
7.5
1
t
t
ns
ns
Setup time before CLK↑
su
CLR inactive
7
Hold time, data after CLK↑
0.5
h
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V ± 0.3 V
CC
T
= 25°C
SN54LV175A SN74LV175A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLR low
t
Pulse duration
ns
w
CLK high or low
Data
5
5
5
5
5
5
t
t
ns
ns
Setup time before CLK↑
su
CLR inactive
5
5
5
Hold time, data after CLK↑
1
1
1
h
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54LV175A SN74LV175A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLR low
t
Pulse duration
ns
w
CLK high or low
Data
5
5
5
4
4
4
t
t
ns
ns
Setup time before CLK↑
su
CLR inactive
5
5
5
Hold time, data after CLK↑
1
1
1
h
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
105*
80
SN54LV175A SN74LV175A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
50*
40
MAX
MIN
45*
35
1*
MAX
MIN
45
35
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
t
max
CLR
CLK
CLR
CLK
Any
Any
Any
Any
7.9* 16.6*
9.3* 18.8*
20*
22*
25.5
27
20
22
C
= 15 pF
pd
L
1*
1
10.4
12
21.6
23.3
2
1
1
25.5
27
t
t
C
C
= 50 pF
= 50 pF
ns
ns
pd
L
L
1
1
2
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV175A SN74LV175A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
90*
50
MAX
MIN
75*
45
MAX
MIN
75
45
1
MAX
C
C
= 15 pF
= 50 pF
155*
120
L
L
f
max
pd
CLR
CLK
CLR
CLK
Any
Any
Any
Any
5.5* 10.1*
6.5* 11.5*
1*
12*
12
13.5
15.5
17
t
C
= 15 pF
L
1* 13.5*
1
7.4
8.4
13.6
15
1
1
15.5
17
1
t
t
C
C
= 50 pF
= 50 pF
ns
ns
pd
L
L
1
1.5
1.5
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T = 25°C
A
SN54LV175A SN74LV175A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MHz
ns
MIN
150*
85
TYP
215*
165
3.7*
4.6*
5.3
MAX
MIN
125*
75
1*
MAX
MIN
125
75
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
t
max
CLR
CLK
CLR
CLK
Any
Any
Any
Any
6.4*
7.3*
8.4
9.3
1
7.5*
8.5*
9.5
7.5
8.5
9.5
10.5
1
C
= 15 pF
pd
L
1*
1
1
1
t
t
C
C
= 50 pF
= 50 pF
ns
ns
pd
L
L
6
1
10.5
1
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV175A
PARAMETER
UNIT
MIN
TYP
0.3
–0.3
3
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
13.6
14.5
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV175A, SN74LV175A
QUADRUPLE D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS400C – APRIL 1998 – REVISED MAY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
Timing Input
50% V
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
CC
Input
Input
CC
Data Input
50% V
50% V
CC
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
t
50% V
CC
CC
CC
t
CC
0 V
0 V
t
PZL
t
t
PLH
PHL
PLZ
Output
Waveform 1
V
OH
≈ V
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
– 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
PHZ
t
PHL
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
V
OH
50% V
50% V
50% V
CC
CC
CC
≈ 0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PHL
PHZ
PZH
PLH
.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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PRODUCT SUPPORT: TRAINING
SN74LV175A, Quadruple D-Type Flip-Flops With Clear
DEVICE STATUS: ACTIVE
PARAMETER NAME SN74LV175A
Voltage Nodes (V) 5, 3.3, 2.5
FEATURES
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TM
l EPIC
(Enhanced-Performance Implanted CMOS) Process
l Typical V
(Output Ground Bounce) <0.8 V at V = 3.3 V, T = 25°C
OLP
CC
A
l Typical V
(Output V
Undershoot)
OHV
OH
>2.3 V at V
= 3.3 V, T = 25°C
CC
A
l 2-V to 5.5-V V
Operation
CC
Support Mixed-Mode Voltage Operation on All Ports
l
l Contain Four Flip-Flops With Double-Rail Outputs
l Applications Include:
Buffer/Storage Registers
¡
¡ Shift Registers
¡ Pattern Generators
Latch-Up Performance Exceeds 250 mA Per JESD 17
l
l ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using
Machine Model (C = 200 pF, R = 0)
l Package Options Include Plastic Small-Outline (D, NS), Shrink Small-Outline (DB), Thin
Very Small-Outline (DGV), and Thin Shrink Small-Outline (PW) Packages, Ceramic Flat
(W) Packages, Chip Carriers (FK), and DIPs (J)
EPIC is a trademark of Texas Instruments.
DESCRIPTION
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The 'LV175A devices are quadruple D-type flip-flops designed for 2-V to 5.5-V V
operation.
CC
2 of 3
These devices have a direct clear (CLR\) input and feature complementary outputs from each
flip-flop.
Information at the data (D) inputs meeting the setup time requirements is transferred to the
outputs on the positive-going edge of the clock (CLK) pulse.
Clock triggering occurs at a particular voltage level and is not directly related to the transition
time of the positive-going edge of CLK. When CLK is at either the high or low level, the D input
has no effect at the output.
The SN54LV175A is characterized for operation over the full military temperature range of -
55°C to 125°C.
The SN74LV175A is characterized for operation from -40°C to 85°C.
TECHNICAL DOCUMENTS
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To view the following documents, Acrobat Reader 3.x is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
DATASHEET
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Full datasheet in Acrobat PDF: scls400c.pdf (157 KB) (
)
Updated: 05/22/2000
Full datasheet in Zipped PostScript: scls400c.psz (157 KB)
APPLICATION NOTES
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View Application Reports for Digital Logic
l CMOS Power Consumption and CPD Calculation (SCAA035B -
)
Updated: 06/01/1997
l Implications of Slow or Floating CMOS Inputs (SCBA004C - Updated: 02/01/1998)
Input and Output Characteristics of Digital Integrated Circuits (SDYA010 -
l
Updated:
10/01/1996)
l Live Insertion (SDYA012 - Updated: 10/01/1996)
Understanding Advanced Bus-Interface Products Design Guide (SCAA029, 253 KB -
l
)
Updated: 05/01/1996
RELATED DOCUMENTS
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l Documentation Rules (SAP) And Ordering Information (SZZU001B, 4 KB - Updated:
05/06/1999)
l Logic Selection Guide Second Half 2000 (SDYU001N, 5035 KB - Updated: 04/17/2000)
MicroStar Junior BGA Design Summary (SCET004, 167 KB -
)
l
Updated: 07/28/2000
l More Power In Less Space - Technical Article (SCAU001A, 850 KB -
)
Updated: 03/01/1996
PRICING/AVAILABILITY
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BUDGETARY
ORDERABLE
DEVICE
TEMP
(ºC)
PRICE
US$/UNIT
QTY=1000+
PACK
QTY
PACKAGE PINS
STATUS
PRICING/AVAILABILITY
-40 TO
85
SN74LV175AD
D
16
16
ACTIVE
ACTIVE
0.37
0.37
40
Check stock or order
Check stock or order
-40 TO
85
SN74LV175ADBR
DB
2000
3 of 3
-40 TO
85
SN74LV175ADGVR
DGV
D
16
16
16
ACTIVE
ACTIVE
ACTIVE
0.45
0.37
0.37
2000
2500
2000
Check stock or order
Check stock or order
Check stock or order
-40 TO
85
SN74LV175ADR
-40 TO
85
SN74LV175APWR
PW
MODELS
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l Quadruple D-type Flip-Flop With Clear (SCEM134, 114 KB -
)
Updated: 07/17/2000
Quadruple D-type Flip-Flop With Clear (SCEM134, 16 KB, ZIP -
)
Updated: 07/17/2000
Table Data Updated on: 11/17/2000
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