SN74LV1T32DBVR [TI]
具有逻辑电平转换器的单电源 2 输入正或门 | DBV | 5 | -40 to 125;
| 型号： | SN74LV1T32DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有逻辑电平转换器的单电源 2 输入正或门 | DBV | 5 | -40 to 125 栅 输入元件 光电二极管 逻辑集成电路 触发器 转换器 电平转换器 |
| 文件： | 总25页 (文件大小：1435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV1T32
ZHCSBS7B –NOVEMBER 2013 –REVISED JUNE 2022
SN74LV1T32 单电源2 输入正或门
CMOS 逻辑电平转换器
– 2mm x 2.1mm x 0.65mm（高度1.1mm）
1 特性
• 闩锁性能超过250mA，符合
JESD 17 规范
• 支持标准逻辑引脚排列
• 与AUP1G 和LVC1G 系列兼容的CMOS 输出B1
• VCC 为5V、3.3V、2.5V 和1.8V 的单电源电压转换
器
• 工作电压范围为1.8V 至5.5V
• 升压转换：
– 1.8V VCC 时，1.2V(1) 至1.8V
– 2.5V VCC 时，1.5V(1) 至2.5V
– 3.3V VCC 时，1.8V(1) 至3.3V
– 5.0V VCC 时，3.3V 至5.0V
• 降压转换：
2 应用
• 电信
• 便携式应用
• 服务器
• PC 和笔记本电脑
– 1.8V VCC 时，3.3V 至1.8V
– 2.5V VCC 时，3.3V 至2.5V
– 3.3V VCC 时，5.0 V 至3.3V
• 逻辑输出以VCC 为基准
3 说明
SN74LV1T32 是一款具有较低输入阈值的单路 2 输入
或门，可支持电压转换应用。
器件信息(1)
• 输出驱动：
封装尺寸（标称值）
器件型号
封装
– 电压为5V 时，输出驱动为8mA
– 电压为3.3V 时，输出驱动为7mA
– 电压为1.8V 时，输出驱动为3mA
• VCC 为3.3V 时，频率高达50MHz
• 输入引脚可耐受5V 电压
DBV（SOT-23，5)
DCK（SC70，5）
2.90mm × 1.60mm
2.00mm × 1.25mm
SN74LV1T32
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• –40°C 至125°C 工作温度范围
• 可提供无铅封装：SC-70 (DCK)
VIH = 2.0V
Vcc = 5.0V
VIL = 0.8V
VIH = 0.99V
Vcc = 1.8V
VIL = 0.55V
5.0V, 3.3V
5.0V
3.3V
System
5.0V
System
2.5V, 1.8V
1.5V, 1.2V
System
1.8V
System
LV1Txx Logic
LV1Txx Logic
Vcc = 3.3V
5.0V, 3.3V
2.5V, 1.8V
System
3.3V
System
LV1Txx Logic
VOH min = 2.4V
VIH min = 1.36V
VOL max = 0.4V
VIL min = 0.8V
1.8V 至3.3V 转换的开关阈值
1
请参考较低VCC 条件下的VIH/VIL 和输出驱动。
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS741
SN74LV1T32
ZHCSBS7B –NOVEMBER 2013 –REVISED JUNE 2022
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Table of Contents
9 Detailed Description......................................................10
9.1 Overview...................................................................10
9.2 Functional Block Diagram.........................................10
9.3 Feature Description...................................................10
9.4 Device Functional Modes..........................................12
10 Power Supply Recommendations..............................13
11 Layout...........................................................................13
11.1 Layout Guidelines................................................... 13
12 Device and Documentation Support..........................14
12.1 接收文档更新通知................................................... 14
12.2 支持资源..................................................................14
12.3 Trademarks.............................................................14
12.4 Electrostatic Discharge Caution..............................14
12.5 术语表..................................................................... 14
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Related Products.............................................................3
6 Pin Configuration and Functions...................................4
7 Specifications.................................................................. 5
7.1 Absolute Maximum Ratings........................................ 5
7.2 ESD Ratings............................................................... 5
7.3 Recommended Operating Conditions.........................6
7.4 Thermal Information....................................................6
7.5 Electrical Characteristics.............................................6
7.6 Switching Characteristics............................................7
7.7 Operating Characteristics........................................... 8
7.8 Typical Characteristics................................................8
8 Parameter Measurement Information............................9
Information.................................................................... 14
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (February 2014) to Revision B (June 2022)
Page
• 更新了整个文档中的表格、图和交叉参考的编号格式.........................................................................................1
• Added ESD Ratings table, Thermal Information table, Typical Characteristics section, Pin Configuration and
Functions section, Detailed Description section, Power Supply Recommendations section, Layout section,
Receiving Notification of Documentation Updates section, and Community Resources section....................... 5
• Updated Electrical characteristics table..............................................................................................................6
• Removed Ioh test condition for Voh parameter ................................................................................................... 6
• Removed Ioh = -2.3mA for Vol parameter ...........................................................................................................6
Changes from Revision * (December 2013) to Revision A (February 2014)
Page
• 更新了文档格式...................................................................................................................................................1
• Updated VCC values for VIH parameter in the Electrical Characteristics table....................................................6
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5 Related Products
DEVICE
PACKAGE
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
DCK, DBV
RGY, PW
DESCRIPTION
SN74LV1T00
SN74LV1T02
SN74LV1T04
SN74LV1T08
SN74LV1T17
SN74LV1T14
SN74LV1T32
SN74LV1T34
SN74LV1T86
SN74LV1T125
SN74LV1T126
SN74LV4T125
2-Input Positive-NAND Gate
2-Input Positive-NOR Gate
Inverter Gate
2-Input Positive-AND Gate
Single Schmitt-Trigger Buffer Gate
Single Schmitt-Trigger Inverter Gate
2-Input Positive-OR Gate
Single Buffer Gate
Single 2-Input Exclusive-Or Gate
Single Buffer Gate with 3-state Output
Single Buffer Gate with 3-state Output
Quadruple Bus Buffer Gate With 3-State Outputs
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6 Pin Configuration and Functions
VCC
1
2
3
5
A
B
GND
Y
4
图6-1. DCK or DBV Package, 5-Pin SC70 or SOT-23 (Top View)
表6-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
A
NO.
1
I
Input A
B
2
I
Input B
GND
Y
3
G
O
P
Ground
4
Output Y
Positive supply
VCC
5
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
7.0
7.0
V
V
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Voltage range applied to any output in the high or low state(2)
4.6
V
VO
VCC + 0.5
V
IIK
IOK
IO
Input clamp current
VI < 0
mA
mA
mA
mA
°C
°C
–20
±20
±25
±50
150
150
Output clamp current
Continuous output current
VO < 0 or VO > VCC
Continuous current through VCC or GND
Junction temperature
TJ
Tstg
Storage temperature
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
7.2 ESD Ratings
VALUE
±2000
±200
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Machine Model (MM), per JEDEC specification
V(ESD) Electrostatic discharge
V
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
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7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) (1)
MIN
1.6
0
MAX
UNIT
VCC
VI
Supply voltage
Input voltage
Output voltage
5.5
5.5
VCC
–3
–5
–7
–8
3
V
V
V
VO
0
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5.0 V
VCC = 1.8 V
VCC = 2.5 V
VCC = 3.3 V
VCC = 5.0 V
VCC = 1.8 V
VCC = 3.3 V or 2.5 V
VCC = 5.0 V
IOH
High-level output current
Low-level output current
mA
mA
5
IOL
7
8
20
20
20
125
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
Δt/Δv
TA
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
7.4 Thermal Information
DBV
5 PINS
206
DCK
5 PINS
252
THERMAL METRIC(1)
UNIT
RθJA
Junction-to-ambient thermal resistance
°C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
7.5 Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
TA = –40°C to +125°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN TYP
MAX
MIN
1.0
TYP
MAX
VCC = 1.65 V to 1.8 V
VCC = 2.0 V
0.94
0.99
1.135
1.21
1.35
1.47
2.02
2.1
1.03
1.18
1.23
1.37
1.48
2.03
2.11
VCC = 2.25 V to 2.5 V
VCC = 2.75 V
High-level
input voltage
VIH
V
VCC = 3 V to 3.3 V
VCC = 3.6 V
VCC = 4.5 V to 5.0 V
VCC = 5.5 V
VCC = 1.65 V to 2.0 V
VCC = 2.25 V to 2.75 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
0.58
0.75
0.8
0.55
0.71
0.65
0.8
Low-level
input voltage
VIL
V
0.8
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over recommended operating free-air temperature range (unless otherwise noted)
TA = 25°C
TA = –40°C to +125°C
PARAMETER
TEST CONDITIONS
IOH = –20 µA
VCC
UNIT
MIN
CC –0.1
1.28
1.5
TYP
MAX
MIN
CC –0.1
1.21
1.45
1.93
2.15
2.7
TYP
MAX
1.65 V to 5.5 V
1.65 V
V
V
IOH = –2.0 mA
1.8 V
2.3 V
2
IOH = –3 mA
IOH = –3 mA
IOH = –3.0 mA
IOH = –5.5 mA
IOH = –5.5 mA
IOH = –4 mA
IOH = –8 mA
IOH = –8 mA
IOL = 20 µA
2.5 V
2.25
2.78
2.6
High-level
VOH
output
V
3.0 V
3.3 V
4.5 V
voltage
2.49
2.8
2.9
4.2
4.1
4.1
3.95
4.5
5.0 V
1.65 V to 5.5 V
1.65 V
4.6
0.1
0.2
0.1
0.25
0.2
IOL = 2 mA
IOL = 3 mA
2.3 V
0.15
0.1
Low-level
output
voltage
VOL
IOL = 3 mA
0.15
0.252
0.2
V
3.0 V
4.5 V
IOL = 5.5 mA
IOL = 4 mA
0.2
0.15
0.3
IOL = 8 mA
0.35
Input
leakage
current
0 V, 1.8 V, 2.5 V,
3.3 V, 5.5 V
II
A input; VI = 0 V or VCC
0.1
±1
μA
μA
5.0 V
3.3 V
2.5 V
1.8 V
1
1
1
1
10
10
10
10
Static supply VI = 0 V or VCC
,
ICC
current
IO = 0; open on loading
One input at 0.3 V or 3.4 V,
Other inputs at 0 or VCC
IO = 0
,
5.5 V
1.8 V
1.35
1.5
mA
Additional
static supply
current
ΔICC
One input at 0.3 V or 1.1 V
Other inputs at 0 or VCC
IO = 0
,
10
10
10
10
μA
Input
capacitance
Ci
VI = VCC or GND
VO = VCC or GND
3.3 V
3.3 V
2
2
pF
pF
Output
capacitance
Co
2.5
2.5
7.6 Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Parameter Measurement Information)
TA = 25°C
TA = –65°C to 125°C
FROM
(INPUT) (OUTPUT)
TO
FREQUENCY
(TYP)
PARAMETER
VCC
CL
UNIT
MIN TYP MAX
MIN
TYP
4
MAX
5
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
15 pF
30 pF
4
5.5
4.8
5
5
7.0
5
5.0 V
3.3 V
2.5 V
1.8 V
ns
5.5
5
7.0
5.5
6.5
7.5
8.5
12
DC to 50 MHz
ns
5.5
6.5
7.5
11
5.5
7
tpd
Any In
Y
6
DC to 25 MHz
DC to 15 MHz
ns
6.5
10.5
12
7.5
11
12
ns
13
14
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7.7 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
TYP
UNIT
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5.5 V ± 0.5 V
14
14
14
14
Cpd
Power dissipation capacitance
f = 1 MHz and 10 MHz
pF
7.8 Typical Characteristics
图7-2. Excellent Signal Integrity
(3.3 V to 3.3 V at 3.3-V VCC
)
图7-1. Excellent Signal Integrity
(1.8 V to 3.3 V at 3.3-V VCC
)
图7-3. Excellent Signal Integrity
(3.3 V to 1.8 V at 1.8-V VCC
)
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8 Parameter Measurement Information
From Output
Under Test
V
= 2.5 V
0.2 V
V
= 3.3 V
0.3 V
CC
CC
C
L
(see Note A)
1 MΩ
C
5, 10, 15, 30 pF 5, 10, 15, 30 pF
V /2 V /2
L
V
MI
I
I
V
MO
V /2
CC
V /2
CC
LOAD CIRCUIT
V
I
V
MI
V
MI
Input
0 V
t
t
t
PHL
PLH
V
V
OH
V
V
V
Mo
MO
Output
OL
t
PHL
PLH
V
V
OH
V
Mo
Mo
Output
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, slew rate ≥ 1 V/ns.
C. The outputs are measured one at a time, with one transition per measurement.
O
D.
t
and t are the same as t .
PHL pd
PLH
图8-1. Load Circuit and Voltage Waveforms
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9 Detailed Description
9.1 Overview
The SN74LV1T32 device is a low-voltage CMOS gate logic that operates at a wider voltage range for industrial,
portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able
to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels. The input is designed with a lower threshold circuit to
match 1.8 V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5 V
tolerant input pins enable down translation (that is, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of
1.8 V to 5.5 V allows generation of desired output levels to connect to controllers or processors. The
SN74LV1T32 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and
undershoot caused by high-drive outputs.
9.2 Functional Block Diagram
1
A
4
Y
2
B
图9-1. Logic Diagram
9.3 Feature Description
9.3.1 Clamp Diode Structure
The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have
negative clamping diodes only as depicted in 图9-2.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
+IOK
Input
Output
Logic
-IIK
-IOK
GND
图9-2. Electrical Placement of Clamping Diodes for Each Input and Output
9.3.2 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
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9.3.3 LVxT Enhanced Input Voltage
The SN74LV1T32 belongs to TI's LVxT family of Logic devices with integrated voltage level translation. This
family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs
tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be
referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. To ensure proper
functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or
below the specified VIL(MAX) for a LOW input state. 图9-3 shows the typical VIH and VIL levels for the LVxT family
of devices, as well as the voltage levels for standard CMOS devices for comparison.
The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance
given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage,
given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical
Characteristics, using Ohm's law (R = V ÷ I).
The inputs require that input signals transition between valid logic states quickly, as defined by the input
transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will
result in excessive power consumption and could cause oscillations. More details can be found in the
Implications of Slow or Floating CMOS Inputs application report.
Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a
system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a
valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ
resistor is recommended and will typically meet all requirements.
3.6
3.4
3.3-V CMOS
3.2
VIH
3
VIL
HIGH Input
LOW Input
2.8
2.6
2.4
2.2
2
2.5-V CMOS
2.4 V (VOH
)
2 V (VOH
)
1.8-V CMOS
1.8
1.6
1.4
1.2
1
1.45 V (VOH
)
1.2-V CMOS
1.1 V (VOH
)
0.8
0.6
0.4
0.2
0
0.45 V (VOL
)
0.4 V (VOL
)
0.4 V (VOL
)
0.3 V (VOL
)
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2
5.5
VCC - Supply Voltage (V)
图9-3. LVxT Input Voltage Levels
9.3.3.1 Down Translation
Signals can be translated down using the SN74LV1T32. The voltage applied at the VCC will determine the output
voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and
0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input
signals in the LOW state are lower than VIL(MAX) as shown in 图9-3.
For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to
match 1.8 V CMOS signals when operating from 1.8-V VCC. See 图9-4.
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Down Translation Combinations:
• 1.8-V VCC –Inputs from 2.5 V, 3.3 V, and 5.0 V
• 2.5-V VCC –Inputs from 3.3 V and 5.0 V
• 3.3-V VCC –Inputs from 5.0 V
9.3.3.2 Up Translation
Input signals can be up translated using the SN74LV1T32. The voltage applied at VCC will determine the output
voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC
in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input high-state levels which are much lower than standard
values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V.
For the SN74LV1T32, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a typical
2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower
than VIL(MAX) as shown in 图9-4.
Up Translation Combinations:
• 1.8-V VCC –Inputs from 1.2 V
• 2.5-V VCC –Inputs from 1.8 V
• 3.3-V VCC –Inputs from 1.8 V and 2.5 V
• 5.0-V VCC –Inputs from 2.5 V and 3.3 V
VIH = 2.0 V
VIL = 0.8 V
VIH = 0.99 V
VIL = 0.5 V
Vcc = 5.0 V
Vcc = 1.8 V
5.0 V, 3.3 V
2.5 V, 1.8 V
1.5 V, 1.2 V
System
5.0 V
3.3 V
System
5.0 V
System
1.8 V
System
LV1Txx Logic
LV1Txx Logic
图9-4. LVxT Up and Down Translation Example
9.4 Device Functional Modes
Function Table
INPUT(1)
(LOWER LEVEL INPUT)
OUTPUT(2)
(VCC CMOS)
A
H
X
L
B
Y
H
H
L
X
H
L
SUPPLY VCC = 3.3 V
A
B
Y
VIH(min) = 1.35 V
VIL(max) = 0.08 V
VOH(min) = 2.9 V
VOL(max) = 0.2 V
(1) H = High Voltage Level, L = Low Voltage Level, X = Do not
Care, Z = High Impedance
(2) H = Driving High, L = Driving Low, Z = High Impedance State
Copyright © 2022 Texas Instruments Incorporated
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SN74LV1T32
ZHCSBS7B –NOVEMBER 2013 –REVISED JUNE 2022
www.ti.com.cn
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the
following layout example.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices inputs must not ever be left floating. In many
cases, functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a
triple-input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
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ZHCSBS7B –NOVEMBER 2013 –REVISED JUNE 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.2 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.5 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
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PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV1T32DBVR
ACTIVE
SOT-23
DBV
5
3000 RoHS & Green
NIPDAU | SN
Level-1-260C-UNLIM
-40 to 125
(NEG3, NEGJ, NEGS)
Samples
SN74LV1T32DBVRG4
SN74LV1T32DCKR
SN74LV1T32DCKRG4
ACTIVE
ACTIVE
ACTIVE
SOT-23
SC70
DBV
DCK
DCK
5
5
5
3000 RoHS & Green
3000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU | SN
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 125
-40 to 125
NEG3
Samples
Samples
Samples
(WG3, WGJ, WGS)
WG3
SC70
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
9-Jun-2022
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV1T32DBVR
SN74LV1T32DBVR
SN74LV1T32DBVR
SN74LV1T32DBVRG4
SN74LV1T32DCKR
SN74LV1T32DCKR
SN74LV1T32DCKRG4
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
178.0
180.0
178.0
178.0
178.0
178.0
178.0
9.2
8.4
9.0
9.2
9.2
9.0
9.2
3.3
3.23
3.3
3.3
2.4
2.4
2.4
3.23
3.17
3.2
1.55
1.37
1.4
4.0
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q3
Q3
Q3
3.23
2.4
1.55
1.22
1.2
SC70
2.5
SC70
2.4
1.22
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
22-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV1T32DBVR
SN74LV1T32DBVR
SN74LV1T32DBVR
SN74LV1T32DBVRG4
SN74LV1T32DCKR
SN74LV1T32DCKR
SN74LV1T32DCKRG4
SOT-23
SOT-23
SOT-23
SOT-23
SC70
DBV
DBV
DBV
DBV
DCK
DCK
DCK
5
5
5
5
5
5
5
3000
3000
3000
3000
3000
3000
3000
180.0
202.0
180.0
180.0
180.0
180.0
180.0
180.0
201.0
180.0
180.0
180.0
180.0
180.0
18.0
28.0
18.0
18.0
18.0
18.0
18.0
SC70
SC70
Pack Materials-Page 2
PACKAGE OUTLINE
DBV0005A
SOT-23 - 1.45 mm max height
S
C
A
L
E
4
.
0
0
0
SMALL OUTLINE TRANSISTOR
C
3.0
2.6
0.1 C
1.75
1.45
1.45
0.90
B
A
PIN 1
INDEX AREA
1
2
5
(0.1)
2X 0.95
1.9
3.05
2.75
1.9
(0.15)
4
3
0.5
5X
0.3
0.15
0.00
(1.1)
TYP
0.2
C A B
NOTE 5
0.25
GAGE PLANE
0.22
0.08
TYP
8
0
TYP
0.6
0.3
TYP
SEATING PLANE
4214839/G 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
4. Body dimensions do not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.25 mm per side.
5. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X (0.95)
4
(R0.05) TYP
(2.6)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214839/G 03/2023
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DBV0005A
SOT-23 - 1.45 mm max height
SMALL OUTLINE TRANSISTOR
PKG
5X (1.1)
1
5
5X (0.6)
SYMM
(1.9)
2
3
2X(0.95)
4
(R0.05) TYP
(2.6)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
4214839/G 03/2023
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
www.ti.com
PACKAGE OUTLINE
DCK0005A
SOT - 1.1 max height
S
C
A
L
E
5
.
6
0
0
SMALL OUTLINE TRANSISTOR
C
2.4
1.8
0.1 C
1.4
1.1
B
1.1 MAX
A
PIN 1
INDEX AREA
1
2
5
NOTE 4
(0.15)
(0.1)
2X 0.65
1.3
2.15
1.85
1.3
4
3
0.33
5X
0.23
0.1
0.0
(0.9)
TYP
0.1
C A B
0.15
0.22
0.08
GAGE PLANE
TYP
0.46
0.26
8
0
TYP
TYP
SEATING PLANE
4214834/C 03/2023
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-203.
4. Support pin may differ or may not be present.
www.ti.com
EXAMPLE BOARD LAYOUT
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X (0.65)
4
(R0.05) TYP
(2.2)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:18X
SOLDER MASK
OPENING
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
METAL
EXPOSED METAL
EXPOSED METAL
0.07 MIN
ARROUND
0.07 MAX
ARROUND
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4214834/C 03/2023
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
www.ti.com
EXAMPLE STENCIL DESIGN
DCK0005A
SOT - 1.1 max height
SMALL OUTLINE TRANSISTOR
PKG
5X (0.95)
1
5
5X (0.4)
SYMM
(1.3)
2
3
2X(0.65)
4
(R0.05) TYP
(2.2)
SOLDER PASTE EXAMPLE
BASED ON 0.125 THICK STENCIL
SCALE:18X
4214834/C 03/2023
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
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这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
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邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023，德州仪器 (TI) 公司
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