SN74LV1T34-Q1 [TI]
汽车单电源缓冲门逻辑电平转换器（无使能端）;
| 型号： | SN74LV1T34-Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车单电源缓冲门逻辑电平转换器（无使能端） 转换器 电平转换器 |
| 文件： | 总19页 (文件大小：1049K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
SN74LV1T34-Q1 汽车类单电源单缓冲器逻辑电平转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
SN74LV1T34-Q1 包含支持扩展电压运行的单个缓冲
器，可实现电平转换。缓冲器以正逻辑执行布尔函数Y
= A。输出电平以电源电压 (VCC) 为基准，并且支持
1.8V、2.5V、3.3V 和5V CMOS 电平。
– 器件温度等级1：-40°C 至+125°C
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 1.8V 至5.5V 的宽工作电压范围
• 单电源电压转换器（参阅LVxT 增强输入电压）：
该输入经设计，具有较低阈值电路，支持较低电压
CMOS 输入的上行转换（例如 1.2V 输入转换为 1.8V
输出或 1.8V 输入转换为 3.3V 输出）。此外，5V 容限
输入引脚可实现下行转换（例如 3.3V 至 2.5V 输
出）。
– 上行转换：
• 1.2 V 至1.8 V
• 1.5 V 至2.5 V
• 1.8V 至3.3V
• 3.3 V 至5.0 V
– 下行转换：
封装信息(1)
器件型号
封装
封装尺寸（标称值）
DCK（SC70，
5）
SN74LV1T34-Q1
2.00mm × 1.25mm
• 5.0V、3.3V、2.5V 至1.8V
• 5.0V、3.3V 至2.5V
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 5.0 V 至3.3 V
• 5.5V 容限输入引脚
• 支持标准引脚排列
• 速率高达150 Mbps，具有5V 或3.3V VCC
• 闩锁性能超过250mA，符合
JESD 17 规范
2 应用
• 启用或禁用数字信号
• 控制指示灯LED
• 通信模块和系统控制器之间的转换
A
Y
简化逻辑图
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS903
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
Table of Contents
8.4 Device Functional Modes..........................................11
9 Application and Implementation..................................12
9.1 Application Information............................................. 12
9.2 Typical Application.................................................... 12
9.3 Design Requirements............................................... 12
9.4 Detailed Design Procedure.......................................14
9.5 Application Curves....................................................14
10 Power Supply Recommendations..............................14
11 Layout...........................................................................15
11.1 Layout Guidelines................................................... 15
11.2 Layout Example...................................................... 15
12 Device and Documentation Support..........................16
12.1 Documentation Support.......................................... 16
12.2 接收文档更新通知................................................... 16
12.3 支持资源..................................................................16
12.4 Trademarks.............................................................16
12.5 Electrostatic Discharge Caution..............................16
12.6 术语表..................................................................... 16
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................4
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................5
6.6 Switching Characteristics –1.8-V VCC ..................... 6
6.7 Switching Characteristics –2.5-V VCC ..................... 6
6.8 Switching Characteristics –3.3-V VCC ..................... 6
6.9 Switching Characteristics –5.0-V VCC ..................... 6
6.10 Typical Characteristics..............................................7
7 Parameter Measurement Information............................8
8 Detailed Description........................................................9
8.1 Overview.....................................................................9
8.2 Functional Block Diagram...........................................9
8.3 Feature Description.....................................................9
Information.................................................................... 16
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision * (May 2022) to Revision A (September 2022)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
Copyright © 2022 Texas Instruments Incorporated
2
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
5 Pin Configuration and Functions
N.C.
1
2
3
5
4
VCC
A
GND
Y
图5-1. DCK Package, 5-Pin SC70 (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
N.C.
A
NO.
1
No Connect
—
I
2
Channel 1, Input A
Ground
GND
Y
3
G
O
P
4
Channel 1, Output Y
Positive Supply
VCC
5
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
3
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.5
−0.5
−0.5
−0.5
MAX
UNIT
V
VCC
VI
Supply voltage
7
7
Input voltage range
V
Output voltage range
VCC + 0.5
4.6
V
VO
Voltage range applied to any output in the high-impedance or power-off state
V
IIK
Input clamp current(2)
mA
mA
mA
mA
°C
°C
VI < −0.5 V
−20
±20
±25
±50
150
150
IOK
Output clamp current(2)
VO < −0.5 V or VO > VCC + 0.5 V
Continuous output current
VO = 0 to VCC
IO
Continuous output current through VCC or GND
Junction temperature
TJ
Tstg
Storage temperature
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
±4000
±2000
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
PARAMETER
Supply voltage
Input voltage
CONDITION
MIN
1.6
0
MAX
5.5
UNIT
VCC
VI
V
V
5.5
VO
Output voltage
0
VCC
V
VCC = 1.65 V to 2 V
1.1
1.28
1.45
2.00
V
VCC = 2.25 V to 2.75 V
VCC = 3 V to 3.6 V
V
VIH
High-level input voltage
V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 2 V
VCC = 2.25 V to 2.75 V
VCC = 3 V to 3.6 V
V
0.50
0.65
0.75
0.85
±3
V
V
VIL
Low-Level input voltage
Output current
V
VCC = 4.5 V to 5.5 V
VCC = 1.6 V to 2 V
V
mA
mA
mA
ns/V
C
IO
VCC = 2.25 V to 2.75 V
VCC = 3.3 V to 5.0 V
VCC = 1.6 V to 5.0 V
±7
±15
20
Input transition rise or fall rate
Operating free-air temperature
Δt/Δv
TA
125
−40
Copyright © 2022 Texas Instruments Incorporated
4
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.4 Thermal Information
SN74LV1T34-Q1
THERMAL METRIC (1)
DCK (SC70)
5 PINS
293.4
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
208.8
180.6
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
120.6
ΨJT
179.5
ΨJB
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
−40°C to 125°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
TYP
MAX
MIN
VCC-0.1
1.21
TYP
MAX
IOH = -50 µA
1.65 V to 5.5 V
1.65 V
VCC-0.1
1.28
2
IOH = -2 mA
1.7(1)
2.4(1)
VOH
IOH = -3 mA
2.25 V
1.93
V
IOH = -5.5 mA
IOH = -8 mA
3.0 V
2.6 3.08(1)
4.1 4.65(1)
2.49
4.5 V
3.95
IOH = 50 µA
1.65 V to 5.5 V
1.65 V
0.1
0.2
0.15
0.2
0.3
1
0.1
0.25
0.2
IOH = 2 mA
0.1(1)
0.1(1)
0.2(1)
0.3(1)
VOL
IOH = 3 mA
2.25 V
V
IOH = 5.5 mA
IOH = 8 mA
3.0 V
0.25
0.35
10
4.5 V
ICC
VI = VCC or GND, IO = 0
1.8 V to 5.5 V
µA
One input at 0.3 V or 3.4 V, other
inputs at VCC or GND
5.5 V
1.8 V
1.35
10
1.5 mA
ΔICC
One input at 0.3 V or 1.1 V, other
inputs at VCC or GND
10
µA
II
VI = 0 V to VCC
0 V to 5.5 V
3.3 V
0.12
10
±1
10
µA
pF
pF
pF
Ci
CO
VI = VCC or GND
Vo = VCC or GND
F = 1 Mhz and 10 Mhz
2
2.5
14
2
3.3 V
2.5
(2) (3)
CPD
1.8 V to 5.5 V
(1) Typical value at nearest nominal voltage (1.8 V, 2.5 V, 3.3 V, and 5 V).
(2) CPD is used to determine the dynamic power consumption, per channel.
(3) PD= VCC 2xFIx(CPD+ CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
5
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.6 Switching Characteristics –1.8-V VCC
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
−40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MAX
MIN
MIN
MIN
MIN
MAX
12.7
15.7
MIN
TYP
10.4
12.7
CL = 15 pF
CL = 50 pF
8.8
1
1
14.9
nS
18.3
TPD
A
Y
10.8
6.7 Switching Characteristics –2.5-V VCC
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
−40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MAX
MAX
7.9
MIN
TYP
7.4
CL = 15 pF
CL = 50 pF
6.3
1
1
9.5
nS
11.5
TPD
A
Y
7.4
9.6
8.9
6.8 Switching Characteristics –3.3-V VCC
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
−40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MAX
MAX
5.9
MIN
TYP
6
CL = 15 pF
CL = 50 pF
4.9
1
1
7.3
nS
8.8
TPD
A
Y
5.9
7.2
7.1
6.9 Switching Characteristics –5.0-V VCC
over operating free-air temperature range (unless otherwise noted)
TA = 25°C
TYP
−40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MAX
MAX
4.1
MIN
TYP
4.1
CL = 15 pF
CL = 50 pF
3.4
1
1
4.7
nS
6.3
TPD
A
Y
3.9
5.3
4.9
Copyright © 2022 Texas Instruments Incorporated
6
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
6.10 Typical Characteristics
3.5
3.5
3
Output
Input
3
2.5
2
2.5
2
1.5
1
1.5
1
0.5
0
0.5
0
Output
Input
-0.5
-0.5
0
2
4
6
8
10
Time (ns)
12
14
16
18
20
0
5
10
Time (ns)
15
20
D002
D001
3.3 V to 3.3 V at 3.3-V VCC
1.8 V to 3.3 V at 3.3-V VCC
图6-2. Switching Characteristics at 50 MHz
图6-1. Switching Characteristics at 50 MHz
Excellent Signal Integrity
Excellent Signal Integrity
3.5
3
Output
Input
2.5
2
1.5
1
0.5
0
-0.5
0
12.5
25
37.5
50
62.5
75
87.5
Time (ns)
D003
3.3 V to 1.8 V at 1.8-V VCC
图6-3. Switching Characteristics at 15 MHz
Excellent Signal Integrity
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
7
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tt< 2.5 ns.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
Test
Point
VCC
0 V
VOH
VOL
VOH
VOL
Input
Output
Output
50%
50%
From Output
Under Test
(1)
(1)
tPLH
tPHL
(1)
CL
50%
50%
(1) CL includes probe and test-fixture capacitance.
(1)
(1)
tPHL
tPLH
图7-1. Load Circuit for Push-Pull Outputs
50%
50%
(1) The greater between tPLH and tPHL is the same as tpd
.
图7-2. Voltage Waveforms Propagation Delays
VCC
90%
Input
90%
10%
0 V
10%
tr(1)
tf(1)
VOH
90%
10%
90%
Output
10%
VOL
tr(1)
tf(1)
(1) The greater between tr and tf is the same as tt.
图7-3. Voltage Waveforms, Input and Output Transition Times
Copyright © 2022 Texas Instruments Incorporated
8
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
8 Detailed Description
8.1 Overview
The SN74LV1T34-Q1 contains a single buffer with extended voltage operation to allow for level translation. The
buffer performs the Boolean function Y = A in positive logic. The output level is referenced to the supply voltage
(VCC) and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
8.2 Functional Block Diagram
A
Y
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 Clamp Diode Structure
As 图 8-1 shows, the outputs to this device have both positive and negative clamping diodes, and the inputs to
this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
+IOK
Input
Output
Logic
-IIK
-IOK
GND
图8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.3 LVxT Enhanced Input Voltage
The SN74LV1T34-Q1 belongs to TI's LVxT family of logic devices with integrated voltage level translation. This
family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs
tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be
referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. To ensure proper
functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or
below the specified VIL(MAX) for a LOW input state. 图8-2 shows the typical VIH and VIL levels for the LVxT family
of devices, as well as the voltage levels for standard CMOS devices for comparison.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
9
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance
given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage,
given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical
Characteristics, using Ohm's law (R = V ÷ I).
The inputs require the input signals to transition between valid logic states quickly, as defined by the input
transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will
result in excessive power consumption and can cause oscillations. More details can be found in the Implications
of Slow or Floating CMOS Inputs application report.
Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a
system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a
valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ
resistor is recommended and will typically meet all requirements.
3.6
3.4
3.3-V CMOS
3.2
VIH
3
VIL
HIGH Input
LOW Input
2.8
2.6
2.4
2.2
2
2.5-V CMOS
2.4 V (VOH
)
2 V (VOH
)
1.8-V CMOS
1.8
1.6
1.4
1.2
1
1.45 V (VOH
)
1.2-V CMOS
1.1 V (VOH
)
0.8
0.6
0.4
0.2
0
0.45 V (VOL
)
0.4 V (VOL
)
0.4 V (VOL
)
0.3 V (VOL
)
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2
5.5
VCC - Supply Voltage (V)
图8-2. LVxT Input Voltage Levels
8.3.3.1 Down Translation
Signals can be translated down using the SN74LV1T34-Q1. The voltage applied at the VCC will determine the
output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and
0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input
signals in the LOW state are lower than VIL(MAX) as shown in 图8-2.
For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to
match 1.8 V CMOS signals when operating from 1.8-V VCC. See 图8-3.
Down Translation Combinations are as follows:
• 1.8-V VCC –Inputs from 2.5 V, 3.3 V, and 5.0 V
• 2.5-V VCC –Inputs from 3.3 V and 5.0 V
• 3.3-V VCC –Inputs from 5.0 V
8.3.3.2 Up Translation
Input signals can be up translated using the SN74LV1T34-Q1. The voltage applied at VCC will determine the
output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Copyright © 2022 Texas Instruments Incorporated
10
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC
in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input HIGH state levels which are much lower than standard
values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V.
For the SN74LV1T34-Q1, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a
typical 2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower
than VIL(MAX) as shown in 图8-3.
Up Translation Combinations are as follows:
• 1.8-V VCC –Inputs from 1.2 V
• 2.5-V VCC –Inputs from 1.8 V
• 3.3-V VCC –Inputs from 1.8 V and 2.5 V
• 5.0-V VCC –Inputs from 2.5 V and 3.3 V
VIH = 2.0 V
VIL = 0.8 V
VIH = 0.99 V
VIL = 0.5 V
Vcc = 5.0 V
Vcc = 1.8 V
5.0 V, 3.3 V
2.5 V, 1.8 V
1.5 V, 1.2 V
System
5.0 V
3.3 V
System
5.0 V
System
1.8 V
System
LV1Txx Logic
LV1Txx Logic
图8-3. LVxT Up and Down Translation Example
8.4 Device Functional Modes
表8-1 is the function table for the SN74LV1T34-Q1.
表8-1. Function Table
INPUT
OUTPUT
(LOWER LEVEL INPUT)
(VCC CMOS)
A
H
L
Y
H
L
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
11
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
图 9-1 shows how the SN74LV1T34-Q1 is used to up-translate a 1.8-V signal to 3.3 V to drive an LED in this
application. The SN74LV1T34-Q1 does not limit the output current, so an added output resistor is used to
provide the appropriate current limiting. The resistor value (R) should be determined by the LED's forward
voltage (VD) and the desired forward current through the LED (ID) using this equation: R = (VCC - VD)/ID.
9.2 Typical Application
3.3 V
0.1 F
R
SN74LV1T34
1.8 V
NC
VCC
System
Controller
A
Y
+
VD
ID
GND
-
图9-1. Typical Application Block Diagram
9.3 Design Requirements
9.3.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV1T34-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV1T34-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV1T34-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74LV1T34-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Copyright © 2022 Texas Instruments Incorporated
12
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.3.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV1T34-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74LV1T34-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined
in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.3.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
13
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
9.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LV1T34-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.5 Application Curves
3.3
A
Y
3
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
-0.3
0
2
4
6
8
10
12
14
16
18
20
Time (µs)
图9-2. Application Timing Diagram
10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass caps
to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in parallel. The
bypass capacitor should be installed as close to the power terminal as possible for best results, as shown in the
following layout example.
Copyright © 2022 Texas Instruments Incorporated
14
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused; for example, when only two inputs of a triple-
input AND gate are used or only 3 of the 4 buffer gates are used. Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1
F
NC
A
1
2
5
4
VCC
Avoid 90°
corners for
signal lines
GND
3
Y
图11-1. Example Layout for the SN74LV1T34-Q1
Copyright © 2022 Texas Instruments Incorporated
Submit Document Feedback
15
Product Folder Links: SN74LV1T34-Q1
SN74LV1T34-Q1
ZHCSQH1A –MAY 2022 –REVISED SEPTEMBER 2022
www.ti.com.cn
12 Device and Documentation Support
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs application report
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2022 Texas Instruments Incorporated
16
Submit Document Feedback
Product Folder Links: SN74LV1T34-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2022
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV1T34QDCKRQ1
ACTIVE
SC70
DCK
5
3000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
1M3
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV1T34-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2022
Catalog : SN74LV1T34
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2022，德州仪器 (TI) 公司
相关型号：
SN74LV1T34DBVR
单电源缓冲门逻辑电平转换器（无使能端） | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T34DBVRG4
单电源缓冲门逻辑电平转换器（无使能端） | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T34DCKR
单电源缓冲门逻辑电平转换器（无使能端） | DCK | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T34DCKRG4
单电源缓冲门逻辑电平转换器（无使能端） | DCK | 5Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T34QDCKRQ1
汽车单电源缓冲门逻辑电平转换器（无使能端） | DCK | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T86
单电源 2 输入异或 (XOR) 门逻辑电平转换器Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T86DBVR
单电源 2 输入异或 (XOR) 门逻辑电平转换器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T86DBVRG4
单电源 2 输入异或 (XOR) 门逻辑电平转换器 | DBV | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T86DCKR
单电源 2 输入异或 (XOR) 门逻辑电平转换器 | DCK | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV1T86DCKRG4
单电源 2 输入异或 (XOR) 门逻辑电平转换器 | DCK | 5 | -40 to 125Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV20A
DUAL 4 INPUT POSITIVE NAND GATEWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
SN74LV20AD
DUAL 4 INPUT POSITIVE NAND GATEWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
TI
©2020 ICPDF网 联系我们和版权申明