SN74LV240ANSE4 [TI]
IC LV/LV-A/LVX/H SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20, Bus Driver/Transceiver;
| 型号： | SN74LV240ANSE4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | IC LV/LV-A/LVX/H SERIES, DUAL 4-BIT DRIVER, INVERTED OUTPUT, PDSO20, PLASTIC, SO-20, Bus Driver/Transceiver 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总7页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SCLS193B − FEBRUARY 1993 − REVISED APRIL 1996
SN54LV240 . . . J OR W PACKAGE
SN74LV240 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical V
(Output Ground Bounce)
OLP
< 0.8 V at V , T = 25°C
CC
A
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
Typical V
(Output V
Undershoot)
2OE
1Y1
2A4
1Y2
2A3
1Y3
OHV
OH
> 2 V at V , T = 25°C
CC
A
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
13 2A2
12 1Y4
D
D
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
11
2A1
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SN54LV240 . . . FK PACKAGE
(TOP VIEW)
description
3
2
1
20 19
18
1Y1
2A4
1Y2
2A3
1Y3
1A2
2Y3
1A3
2Y2
1A4
4
5
6
7
8
These octal buffers/drivers are designed for 2.7-V
to 5.5-V V operation.
17
16
15
14
CC
The ’LV240 are designed specifically to improve
both the performance and density of 3-state
memory address drivers, clock drivers, and
bus-oriented receivers and transmitters.
9 10 11 12 13
The ’LV240 are organized as two 4-bit buffers/line
drivers with separate output-enable (OE) inputs.
When OE is low, the device passes data from the
A inputs to the Y outputs. When OE is high, the
outputs are in the high-impedance state.
The SN74LV240 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV240 is characterized for operation over the full military temperature range of −55°C to 125°C. The
SN74LV240 is characterized for operation from −40°C to 85°C.
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
L
H
Z
H
X
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢃ ꢇꢈ ꢀꢁꢉ ꢃ ꢄꢅ ꢆ ꢃꢇ
ꢊꢋ ꢌꢍ ꢄ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢀꢓ ꢔ ꢒꢕ ꢅ ꢑꢒ ꢀ
ꢖꢕ ꢌ ꢗ ꢘ ꢙꢀꢌꢍꢌ ꢑ ꢊꢏꢌ ꢚ ꢏꢌꢀ
SCLS193B − FEBRUARY 1993 − REVISED APRIL 1996
†
logic symbol
logic diagram (positive logic)
1
1
1OE
EN
1OE
18
2
2
4
6
8
18
16
14
12
1Y1
1Y2
1Y3
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1A1
16
14
4
1A2
6
1A3
19
EN
2OE
12
8
1Y4
1A4
11
13
15
17
9
7
5
3
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
19
2OE
9
7
11
2Y1
2Y2
2A1
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
13
Pin numbers shown are for DB, DW, J, PW, and W packages.
2A2
5
3
15
2Y3
2Y4
2A3
17
2A4
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W
A
DW package . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SCLS193B − FEBRUARY 1993 − REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV240
SN74LV240
UNIT
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
High-level input voltage
V
V
IH
3.15
3.15
0.8
0.8
V
IL
Low-level input voltage
1.65
1.65
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
−8
V
CC
−8
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
I
High-level output current
Low-level output current
mA
mA
OH
−16
8
−16
8
I
OL
16
16
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
100
125
0
100
85
ns/V
T
A
−55
−40
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV240
SN74LV240
†
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
= −100 µA
MIN to MAX
3 V
V
− 0.2
V
− 0.2
OH
OH
OH
OL
OL
OL
CC
2.4
3.6
CC
2.4
3.6
= −8 mA
= −16 mA
= 100 µA
= 8 mA
V
V
OH
4.5 V
MIN to MAX
3 V
0.2
0.4
0.55
1
0.2
0.4
0.55
1
V
OL
V
= 16 mA
4.5 V
3.6 V
I
I
I
V = V
or GND
µA
µA
I
I
CC
5.5 V
1
1
3.6 V
5
5
V
= V
or GND
OZ
CC
O
CC
5.5 V
5
5
3.6 V
20
20
20
20
V = V
or GND,
I
= 0
µA
µA
I
CC
O
5.5 V
One input at V
CC
Other inputs at V
− 0.6 V,
or GND
nI
CC
3 V to 3.6 V
500
500
CC
3.3 V
5 V
3
3
8
3
3
8
C
C
V = V
CC
or GND
pF
pF
i
I
3.3 V
V
O
= V or GND
CC
o
5 V
8
8
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
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3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢃ ꢇꢈ ꢀꢁꢉ ꢃ ꢄꢅ ꢆ ꢃꢇ
ꢊꢋ ꢌꢍ ꢄ ꢎ ꢏ ꢐꢐ ꢑꢒ ꢀꢓ ꢔ ꢒꢕ ꢅ ꢑꢒ ꢀ
ꢖꢕ ꢌ ꢗ ꢘ ꢙꢀꢌꢍꢌ ꢑ ꢊꢏꢌ ꢚ ꢏꢌꢀ
SCLS193B − FEBRUARY 1993 − REVISED APRIL 1996
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN54LV240
FROM
(INPUT)
TO
(OUTPUT)
V
CC
MIN
= 5 V 0.5 V
V
CC
MIN
= 3.3 V 0.3 V
V
CC
MIN
= 2.7 V
MAX
18
PARAMETER
UNIT
TYP
7
MAX
TYP
9
MAX
t
t
t
A
Y
Y
Y
13
18
23
16
24
24
ns
ns
ns
pd
en
dis
11
14
14
28
OE
OE
12
25
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN74LV240
FROM
(INPUT)
TO
(OUTPUT)
V
CC
MIN
= 5 V 0.5 V
V
CC
MIN
= 3.3 V 0.3 V
V
CC
MIN
= 2.7 V
MAX
18
PARAMETER
UNIT
TYP
7
MAX
TYP
9
MAX
t
t
t
A
Y
Y
Y
13
18
23
16
24
24
ns
ns
ns
pd
en
dis
11
14
14
28
OE
OE
12
25
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
V
TYP
45
2.5
78
3
UNIT
CC
Outputs enabled
3.3 V
5 V
Outputs disabled
Outputs enabled
Outputs disabled
C
Power dissipation capacitance per buffer/driver
C
= 50 pF,
L
f = 10 MHz
pF
pd
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ
ꢖ ꢕꢌ ꢗ ꢘ ꢙꢀꢌꢍꢌ ꢑ ꢊ ꢏꢌ ꢚ ꢏꢌ
SCLS193B − FEBRUARY 1993 − REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
V
z
TEST
S1
S1
Open
1 kΩ
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
t
V
z
GND
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
1 kΩ
(see Note A)
WAVEFORM
CONDITION
V
= 4.5 V
V
= 2.7 V
CC
to 5.5 V
CC
to 3.6 V
1.5 V
2.7 V
6 V
V
m
0.5 × V
CC
V
i
V
z
V
CC
LOAD CIRCUIT
2 × V
CC
V
i
V
m
Timing Input
0 V
t
w
t
t
su
h
V
i
V
i
V
m
V
m
Input
V
m
V
m
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
i
i
Output
Control
V
V
m
m
Input
V
m
V
m
0 V
0 V
V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
0.5 × V
z
OH
V
V
V
m
V
m
m
Output
Output
V
+ 0.3 V
− 0.3 V
S1 at V
(see Note B)
OL
z
V
OL
V
OL
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
V
V
m
m
m
[ 0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
NOTES: A. includes probe and jig capacitance.
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
are the same as t
en
are the same as t .
pd
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SOIC
SOIC
Drawing
SN74LV240DBLE
SN74LV240DW
OBSOLETE
OBSOLETE
OBSOLETE
DB
20
20
20
20
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DW
SN74LV240DWR
SN74LV240PWLE
DW
OBSOLETE TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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