SN74LV244ATDWG4 [TI]
LV/LV-A/LVX/H SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SOIC-20;
| 型号： | SN74LV244ATDWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LV/LV-A/LVX/H SERIES, DUAL 4-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SOIC-20 驱动 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总20页 (文件大小：685K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES572C–JUNE 2004–REVISED AUGUST 2005
FEATURES
•
•
•
•
Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Typical tpd = 5.4 ns at 5 V
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 5 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
– 1000-V Charged-Device Model (C101)
RGY PACKAGE
(TOP VIEW)
DB, DGV, DW, NS, OR PW PACKAGE
(TOP VIEW)
1OE
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
GND
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
2OE
1Y1
2A4
1
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1A1
2Y4
1A2
2Y3
1A3
2Y2
1A4
2Y1
2OE
1Y1
2A4
1Y2
2A3
1Y3
2A2
1Y4
16 1Y2
15 2A3
14
13
12
11
1Y3
2A2
1Y4
2A1
10
11
DESCRIPTION/ORDERING INFORMATION
This octal buffer/driver is designed specifically to improve both the performance and density of 3-state
memory-address drivers, clock drivers, and bus-oriented receivers and transmitters.
The SN74LV244AT is organized as two 4-bit buffers/line drivers with separate output-enable (OE) inputs. When
OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the
high-impedance state.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LV244ATRGYR
SN74LV244ATDW
TOP-SIDE MARKING
VV244
QFN – RGY
SOIC – DW
Reel of 1000
Tube of 25
LV244AT
Reel of 2000
Reel of 2000
Reel of 2000
Tube of 70
SN74LV244ATDWR
SN74LV244ATNSR
SN74LV244ATDBR
SN74LV244ATPW
SOP – NS
74LV244AT
LV244AT
–40°C to 85°C
SSOP – DB
TSSOP – PW
TVSOP – DGV
Reel of 2000
Reel of 250
Reel of 2000
SN74LV244ATPWR
SN74LV244ATPWT
SN74LV244ATDGVR
LV244AT
LV244AT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES572C–JUNE 2004–REVISED AUGUST 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
To ensure the high-impedance state during power up or power down, OE shall be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(EACH 4-BIT BUFFER/DRIVER)
INPUTS
OUTPUT
Y
OE
L
A
H
L
H
L
L
H
X
Z
LOGIC DIAGRAM (POSITIVE LOGIC)
1
2
19
1OE
1A1
2OE
18
16
14
12
11
13
15
17
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
4
6
8
1A2
1A3
1A4
2
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES572C–JUNE 2004–REVISED AUGUST 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range applied in the high or low state(2)(3)
7
7
7
V
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–20
–50
±35
±70
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
VO = 0 to VCC
DB package(4)
DGV package(4)
DW package(4)
NS package(4)
PW package(4)
RGY package(5)
92
58
θJA
Package thermal impedance
Storage temperature range
°C/W
°C
60
83
37
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
MIN
4.5
2
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
5.5
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
0.8
5.5
VCC
5.5
–16
16
0
0
0
High or low state
3-state
VO
Output voltage
V
IOH
IOL
High-level output current
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
mA
mA
ns/V
°C
Low-level output current
∆t/∆v
TA
Input transition rise or fall rate
Operating free-air temperature
20
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES572C–JUNE 2004–REVISED AUGUST 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C
to 85°C
TA = 25°C
TYP MAX
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
4.4
MIN MAX
IOH = –50 µA
IOH = –16 mA
IOL = 50 µA
IOL = 16 mA
4.5 V
4.5 V
4.5 V
4.5 V
0 to 5.5 V
5.5 V
5.5 V
5.5 V
0
4.5
4.4
3.8
0.1
0.55
±1
VOH
V
V
3.8
0
0.1
0.55
±0.1
±0.25
2
VOL
II
VI = 5.5 V or GND
µA
µA
µA
mA
µA
pF
IOZ
VO = VCC or GND
±2.5
20
ICC
VI = VCC or GND, IO = 0
One input at 3.4 V, Other inputs at VCC or GND
VI or VO = 0 to 5.5 V
(1)
∆ICC
1.35
0.5
1.5
5
Ioff
Ci
VI = VCC or GND
4.5
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC
.
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = 25°C
TYP MAX
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN MAX UNIT
MIN
2.6
2.4
2.2
2.7
2.2
2.5
4
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
tsk(o)
5/4
5.4
7.4
7.4
1
1
1
1
1
1
1
1
1
1
1
1
8.5
8.5
12
12
8
A or B
OE
B or A
A or B
A or B
B or A
A or B
A or B
CL = 15 pF
CL = 15 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
ns
ns
ns
ns
ns
7.7 10.4
7.7 10.4
3.9
3.9
5.9
5.9
7.7
7.7
8.9
8.9
OE
8
9.5
9.5
13
13
13
13
1
A or B
OE
4.7
3.9
4.9
3.3
3.2
8.2 11.4
8.2 11.4
8.8 11.4
8.8 11.4
1
OE
CL = 50 pF
CL = 50 pF
ns
ns
Noise Characteristics(1)
VCC = 5 V, CL = 50 pF
TA = 25°C
PARAMETER
Quiet output, maximum dynamic VOL
UNIT
MIN TYP
MAX
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
0.8
1
V
V
V
V
V
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
–1
4
2
0.8
(1) Characteristics are for surface-mount packages only.
4
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES572C–JUNE 2004–REVISED AUGUST 2005
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
Power dissipation capacitance
TEST CONDITIONS
CL = 50 pF, f = 10 MHz
TYP
UNIT
Cpd
Outputs enabled
8
pF
5
SN74LV244AT
OCTAL BUFFER/DRIVER
WITH 3-STATE OUTPUTS
www.ti.com
SCES572C–JUNE 2004–REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
Open
PLH PHL
C
L
C
L
t
/t
V
CC
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
≈V
V
CC
OH
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
CC
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHL
PHZ
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2011
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV244ATDBRE4
SN74LV244ATDBRG4
SN74LV244ATDGVRE4
SN74LV244ATDGVRG4
SN74LV244ATDW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SSOP
TVSOP
TVSOP
SOIC
DB
DB
20
20
20
20
20
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DGV
DGV
DW
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SN74LV244ATDWE4
SN74LV244ATDWG4
SN74LV244ATDWR
SN74LV244ATDWRE4
SN74LV244ATDWRG4
SN74LV244ATNSR
SN74LV244ATNSRE4
SN74LV244ATNSRG4
SN74LV244ATPW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
SOIC
SO
DW
DW
DW
DW
DW
NS
20
20
20
20
20
20
20
20
20
20
20
20
20
Green (RoHS
& no Sb/Br)
25
Green (RoHS
& no Sb/Br)
2000
2000
2000
2000
2000
2000
70
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SO
NS
Green (RoHS
& no Sb/Br)
SO
NS
Green (RoHS
& no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
PW
PW
PW
PW
PW
Green (RoHS
& no Sb/Br)
SN74LV244ATPWE4
SN74LV244ATPWG4
SN74LV244ATPWR
SN74LV244ATPWRE4
70
Green (RoHS
& no Sb/Br)
70
Green (RoHS
& no Sb/Br)
2000
2000
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2011
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV244ATPWRG4
SN74LV244ATPWT
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
20
20
20
20
20
20
2000
250
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-2-260C-1 YEAR
CU NIPDAU Level-2-260C-1 YEAR
SN74LV244ATPWTE4
SN74LV244ATPWTG4
SN74LV244ATRGYR
SN74LV244ATRGYRG4
PW
250
Green (RoHS
& no Sb/Br)
PW
250
Green (RoHS
& no Sb/Br)
RGY
RGY
3000
3000
Green (RoHS
& no Sb/Br)
VQFN
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
1-Aug-2011
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV244ATDWR
SN74LV244ATNSR
SN74LV244ATPWR
SN74LV244ATPWT
SN74LV244ATRGYR
SOIC
SO
DW
NS
20
20
20
20
20
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
24.4
24.4
16.4
16.4
12.4
10.8
8.2
13.0
13.0
7.1
2.7
2.5
1.6
1.6
1.6
12.0
12.0
8.0
24.0
24.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
TSSOP
TSSOP
VQFN
PW
PW
RGY
6.95
6.95
3.8
7.1
8.0
3000
4.8
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Jul-2011
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV244ATDWR
SN74LV244ATNSR
SN74LV244ATPWR
SN74LV244ATPWT
SN74LV244ATRGYR
SOIC
SO
DW
NS
20
20
20
20
20
2000
2000
2000
250
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
41.0
41.0
33.0
33.0
29.0
TSSOP
TSSOP
VQFN
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements,
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www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
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Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
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Industrial
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www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
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Interface
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interface.ti.com
logic.ti.com
Medical
Security
Logic
Space, Avionics and Defense www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and
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www.ti.com/automotive
Microcontrollers
RFID
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
Wireless
www.ti.com/video
www.ti.com/wireless-apps
RF/IF and ZigBee® Solutions www.ti.com/lprf
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