SN74LV273AQDGSRQ1 [TI]
具有清零功能的汽车级八路 D 型触发器 | DGS | 20 | -40 to 125;
| 型号： | SN74LV273AQDGSRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有清零功能的汽车级八路 D 型触发器 | DGS | 20 | -40 to 125 触发器 |
| 文件： | 总26页 (文件大小：1711K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV273A-Q1
ZHCSQW9B –AUGUST 2022 –REVISED JANUARY 2023
SN74LV273A-Q1 具有清零功能的汽车类八路D 型触发器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
– 器件温度等级1：
SN74LV273A-Q1 器件是一款具有共享直接低电平有效
清零 (CLR) 输入和时钟 (CLK) 的八路上升沿触发 D 型
触发器。
• 40°C 至+ 125°C，TA
– 器件HBM ESD 分类等级2
数据(D) 输入上满足设置时间要求的信息被发送到时钟
(CLK) 脉冲上升沿的 (Q) 输出。时钟触发在一个特定电
压电平下发生，并且不与正向脉冲的转换时间直接相
关。当 CLK 处于高电平或低电平或从高电平转为低电
平时，D 输入对输出没有影响。数据(Q) 输出上的信息
可通过清零(CLR) 引脚利用低电平输入异步清零。
– 器件CDM ESD 分类等级C6
• 采用具有可润湿侧翼的QFN (WRKS) 封装
• 2 V 至5.5 V VCC 运行
• 5V 时tpd 最大值为10.5 ns
• 所有端口上均支持以混合模式电压运行
• Ioff 支持局部断电模式运行
封装信息(1)
• 闩锁性能超过250mA，符合JESD 17 规范
封装尺寸（标称值）
器件型号
封装
2 应用
4.50mm × 2.50mm
WRKS（WQFN、20）
SN74LV273A-Q1
• 将数字信号与时钟同步
• 使用更少的输入来监控信号
• 将开关转换为拨动开关
DGS（VSSOP，20） 5.10mm × 3.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
1D
2D
3D
4D
5D
13
6D
14
7D
17
8D
18
3
4
7
8
11
CLK
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
R
R
R
R
R
R
R
R
1
CLR
2
5
6
9
12
5Q
15
6Q
16
7Q
19
8Q
1Q
2Q
3Q
4Q
逻辑图（正逻辑）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS905
SN74LV273A-Q1
ZHCSQW9B –AUGUST 2022 –REVISED JANUARY 2023
www.ti.com.cn
Table of Contents
7 Parameter Measurement Information............................9
8 Detailed Description......................................................10
8.1 Overview...................................................................10
8.2 Functional Block Diagram.........................................10
8.3 Feature Description...................................................10
8.4 Device Functional Modes..........................................12
9 Application and Implementation..................................13
9.1 Application Information............................................. 13
9.2 Typical Application.................................................... 13
9.3 Power Supply Recommendations.............................15
9.4 Layout....................................................................... 15
10 Device and Documentation Support..........................17
10.1 Related Documentation.......................................... 17
10.2 Receiving Notification of Documentation Updates..17
10.3 支持资源..................................................................17
10.4 Trademarks.............................................................17
10.5 静电放电警告.......................................................... 17
10.6 术语表..................................................................... 17
11 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V.................6
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V.................6
6.8 Timing Requirements, VCC = 5 V ± 0.5 V....................6
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V...........7
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V.........7
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V............7
6.12 Operating Characteristics......................................... 8
6.13 Noise Characteristics................................................8
6.14 Typical Characteristics..............................................8
Information.................................................................... 17
4 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (October 2022) to Revision B (January 2023)
Page
• 向数据表添加了DGS 封装信息.......................................................................................................................... 1
Changes from Revision * (August 2022) to Revision A (October 2022)
Page
• 将数据表的状态从预告信息更改为“量产数据”.............................................................................................. 1
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5 Pin Configuration and Functions
CLR
1
VCC
CLR
1
20
VCC
20
1Q
1D
2D
2Q
3Q
3D
4D
4Q
2
3
4
5
6
7
8
9
19
18
8Q
8D
1Q
1D
2
3
19
18
8Q
8D
2D
2Q
3Q
3D
4
5
6
7
17
16
7D
7Q
6Q
17 7D
16
15
7Q
6Q
15
14
PAD
6D
14 6D
5D
12 5Q
13
12
11
4Q
4D
8
9
5D
5Q
13
GND
10
CLK
10 11
GND
CLK
图5-2. SN74LV273A-Q1 DGS Package, 20-Pin
图5-1. SN74LV273A-Q1 WRKS Package, 20-Pin
VSSOP (Top View)
WQFN (Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
CLR
1Q
NO.
1
I
O
I
Clear for all channels, active low
2
Output for channel 1
Input for channel 1
Input for channel 2
Output for channel 2
Output for channel 3
Input for channel 3
Input for channel 4
Output for channel 4
Ground
1D
3
2D
4
I
2Q
5
O
O
I
3Q
6
3D
7
4D
8
I
4Q
9
O
G
I
GND
CLK
5Q
10
11
12
13
14
15
16
17
18
19
20
Clock for all channels, rising edge triggered
Output for channel 5
Input for channel 5
Input for channel 6
Output for channel 6
Output for channel 7
Input for channel 7
Input for channel 8
Output for channel 8
Positive supply
O
I
5D
6D
I
6Q
O
O
I
7Q
7D
8D
I
8Q
O
P
—
VCC
Thermal pad
Thermal Pad(2)
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power.
(2) WRKS Package Only
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6 Specifications
6.1 Absolute Maximum Ratings
Over operating free-air temperature range (unless otherwise noted)(1)
MIN
MAX
UNIT
V
VCC
VI
Supply voltage
7
–0.5
–0.5
–0.5
–0.5
Input voltage(2)
7
7
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage (2) (3)
V
VCC + 0.5
V
Input clamp current
VI < 0
mA
mA
mA
mA
°C
–20
–50
±25
IOK
IO
Output clamp current
VO < 0
Continuous output current
VO = 0 to VCC
Continuous current through VCC or GND
Storage temperature
±50
Tstg
150
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
6.2 ESD Ratings
VALUE
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
±4000
Electrostatic
discharge
V(ESD)
V
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level
C4B
±2000
(1) AEC Q100-002 indicate that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
MIN
2
MAX
UNIT
VCC
VIH
Supply voltage
5.5
V
VCC = 2 V
1.5
High-level input voltage
V
V
VCC = 2.3 V to 5.5 V
VCC = 2 V
VCC × 0.7
0.5
VCC × 0.3
5.5
VIL
Low-level input voltage
VCC = 2.3 V to 5.5 V
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC
–50
–2
VCC = 2 V
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2 V
IOH
High-level output current
Low-level output current
mA
–6
–12
50
µA
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
2
IOL
6
mA
12
200
100
20
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
Δt/Δv
TA
125
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See Implications of Slow or Floating
CMOS Inputs.
6.4 Thermal Information
SN74LV273A-Q1
THERMAL METRIC(1)
UNIT
WRKS (WQFN)
20 PINS
DGS (VSSOP)
20 PINS
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
75.8
125.5
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
80.3
50.5
16.0
50.4
32.3
80.0
63.8
8.4
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
ψJT
79.9
N/A
ψJB
RθJC(bot)
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.
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6.5 Electrical Characteristics
over operating free-air temperature range (unless otherwise noted).
PARAMETER
VCC
MIN
VCC –0.1
2
TYP
MAX
UNIT
2 V to 5.5 V
2.3 V
IOH = –50 mA
IOH = –2 mA
IOH = –6 mA
IOH = –12 mA
IOL = 50 mA
VOH
High level output voltage
Low level output voltage
V
3 V
2.48
4.5 V
3.8
2 V to 5.5 V
2.3 V
0.1
0.4
IOL = 2 mA
VOL
V
IOL = 6 mA
3 V
0.44
0.55
±1
IOL = 12 mA
4.5 V
II
Input leakage current
Supply current
VI = 5.5 V or GND
0 V to 5.5 V
µA
µA
VI = VCC or GND, IO
= 0
ICC
5.5 V
20
5
Input/Output Power-Off Leakage
Current
Ioff
Ci
VI or VO = 0 to 5.5 V
VI = VCC or GND
0 V
µA
pF
Input Capacitance
3.3 V
2
6.6 Timing Requirements, VCC = 2.5 V ± 0.2 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
25°C
–40°C to 125°C
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
MIN
MAX
CLR low
6.5
7
7.5
9
tw
Pulse duration
ns
CLK high or low
12
4.5
2.5
8.5
4
Data before CLK↑
tsu
th
Setup time
Hold time
ns
ns
CLR inactive before CLK↑
Data after CLK↑
0.5
6.7 Timing Requirements, VCC = 3.3 V ± 0.3 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
25°C
–40°C to 125°C
MIN MAX
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
CLR low
5
5
6.5
7
tw
Pulse duration
ns
CLK high or low
8
5.5
2.5
1
Data before CLK↑
tsu
th
Setup time
Hold time
ns
ns
3
CLR inactive before CLK↑2.5
Data after CLK↑
2.5
6.8 Timing Requirements, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted) (see 图7-1)
25°C
–40°C to 125°C
MIN MAX
PARAMETER
TEST CONDITION
UNIT
MIN
MAX
CLR low
5
5
5.5
5.5
6
tw
Pulse duration
ns
CLK high or low
4.5
2
Data before CLK↑
tsu
th
Setup time
Hold time
ns
ns
2.5
2
CLR inactive before CLK↑
Data after CLK↑
1
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CLR
LE
xD
xQ
图6-1. Typical Clock, Load, and Clear Sequences
6.9 Switching Characteristics, VCC = 2.5 V ± 0.2 V
over operating free-air temperature range (unless otherwise noted), (see 图7-1)
25°C
–40°C to 125°C
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
UNIT
MIN
55
45
TYP
95
MAX
MIN
45
TYP
MAX
CL = 15 pF
CL = 50 pF
fmax
MHz
ns
75
10.4
10.3
12.9
13.1
40
1
CLK
CLR
CLK
CLR
18.3
22.5
tpd
Q
Q
CL = 15 pF
19
22.1
22.8
2
1
23
27
1
tpd
CL = 50 pF
1
27.5
2
ns
tsk(o)
6.10 Switching Characteristics, VCC = 3.3 V ± 0.3 V
over operating free-air temperature range (unless otherwise noted), (see 图7-1)
25°C
–40°C to 125°C
MIN TYP MAX
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
UNIT
MHz
ns
MIN
75
50
TYP
140
MAX
CL = 15 pF
CL = 50 pF
65
45
1
fmax
110
7.1
6.9
9.1
8.7
CLK
CLR
CLK
CLR
13.6
13.6
17.1
17.1
1.5
17.5
17.5
21
tpd
Q
Q
CL = 15 pF
1
1
tpd
CL = 50 pF
1
21
ns
tsk(o)
1.5
6.11 Switching Characteristics, VCC = 5 V ± 0.5 V
over recommended operating free-air temperature range (unless otherwise noted), (see 图7-1)
25°C
–40°C to 125°C
MIN TYP MAX
PARAMETE
R
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAP
UNIT
MHz
ns
MIN
120
80
TYP
205
MAX
CL = 15 pF
CL = 50 pF
100
70
1
fmax
160
4.8
4.7
6.2
6
CLK
CLR
CLK
CLR
9
11.5
11
tpd
Q
Q
CL = 15 pF
8.5
11
1
1
14
tpd
CL = 50 pF
10.5
1
1
13.5
1
ns
tsk(o)
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6.12 Operating Characteristics
TA = 25°C
PARAMETER
TEST CONDITIONS
VCC
3.3 V
5 V
TYP
UNIT
15.9
17.1
Cpd
Power dissipation capacitance
CL = 50 pF
f = 10 MHz
pF
6.13 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C
PARAMETER(1)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
MIN
TYP
0.3
MAX
UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
0.8
V
V
V
V
V
–0.3
3
–0.8
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
2.31
0.99
(1) Characteristics for surface-mount packages only.
6.14 Typical Characteristics
12
8
7
6
5
4
3
2
1
10
8
6
4
2
TPD in ns
5
TPD in ns
0
0
-100
0
1
2
3
VCC
4
6
-50
0
50
100
150
Temperature (èC)
D001
D002
图6-2. TPD vs Vcc at 25°C
图6-3. TPD vs Temperature
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7 Parameter Measurement Information
V
CC
S1
Open
R
= 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
From Output
Under Test
GND
Point
t
t
Open
PLH PHL
C
C
L
(see Note A)
t
/t
PLZ PZL
V
L
(see Note A)
CC
/t
PHZ PZH
GND
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
su
V
CC
V
CC
50% V
50% V
CC
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
Input
CC
CC
CC
CC
0 V
0 V
t
t
t
t
PZL
PLH
PHL
PLZ
Output
V
≈V
OH
CC
In-Phase
Output
Waveform 1
50% V
50% V
CC
50% V
CC
CC
V
V
+ 0.3 V
OL
S1 at V
CC
V
OL
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
50% V
CC
OH
Out-of-Phase
Output
V
− 0.3 V
OH
50% V
50% V
CC
CC
V
OL
≈0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
INVERTING AND NONINVERTING OUTPUTS
A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω, tr ≤3 ns,
and tf ≤3 ns.
D. The outputs are measured one at a time, with one input transition per measurement.
E. tPLZ and tPHZ are the same as tdis
.
F. tPZL and tPZH are the same as ten
.
G. tPHL and tPLH are the same as tpd
.
H. All parameters and waveforms are not applicable to all devices.
图7-1. Load Circuit and Voltage Waveforms
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8 Detailed Description
8.1 Overview
The SN74LV273A-Q1 device is an octal positive-edge triggered D-type flip-flop with shared direct active low
clear (CLR) input and clock (CLK).
Information at the data (D) inputs meeting the setup time requirements is transferred to the (Q) outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
related directly to the transition time of the positive-going pulse. When CLK is at either the high or low level or
transitioning from a high level to a low level, the D input has no effect at the output. Information at the data (Q)
outputs can be asynchronously cleared with a low level input through the clear (CLR) pin.
The SN74LV273A-Q1 is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
8.2 Functional Block Diagram
1D
2D
3D
4D
5D
13
6D
14
7D
17
8D
18
3
4
7
8
11
CLK
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
R
R
R
R
R
R
R
R
1
CLR
2
5
6
9
12
5Q
15
6Q
16
7Q
19
8Q
1Q
2Q
3Q
4Q
图8-1. Logic Diagram (Positive Logic)
8.3 Feature Description
8.3.1 Balanced CMOS Push-Pull Outputs
This device includes balanced CMOS push-pull outputs. The term balanced indicates that the device can sink
and source similar currents. The drive capability of this device may create fast edges into light loads so routing
and load conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable
of driving larger currents than the device can sustain without being damaged. It is important for the output power
of the device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the
Absolute Maximum Ratings must be followed at all times.
Unused push-pull CMOS outputs should be left disconnected.
8.3.2 Latching Logic
This device includes latching logic circuitry. Latching circuits commonly include D-type latches and D-type flip-
flops, but include all logic circuits that act as volatile memory.
When the device is powered on, the state of each latch is unknown. There is no default state for each latch at
start-up.
The output state of each latching logic circuit only remains stable as long as power is applied to the device within
the supply voltage range specified in the Recommended Operating Conditions table.
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8.3.3 Partial Power Down (Ioff
)
This device includes circuitry to disable all outputs when the supply pin is held at 0 V. When disabled, the
outputs will neither source nor sink current, regardless of the input voltages applied. The amount of leakage
current at each output is defined by the Ioff specification in the Electrical Characteristics table.
8.3.4 Wettable Flanks
This device includes wettable flanks for at least one package. See the Features section on the front page of the
data sheet for which packages include this feature.
Package
Package
Solder
Standard Lead
We able Flank Lead
Pad
PCB
图8-2. Simplified Cutaway View of Wettable-Flank QFN Package and Standard QFN Package After
Soldering
Wettable flanks help improve side wetting after soldering, which makes QFN packages easier to inspect with
automatic optical inspection (AOI). As shown in 图 8-2, a wettable flank can be dimpled or step-cut to provide
additional surface area for solder adhesion which assists in reliably creating a side fillet. Please see the
mechanical drawing for additional details.
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8.3.5 Clamp Diode Structure
图8-3 shows the inputs and outputs to this device have negative clamping diodes only.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
VCC
Device
Input
Output
Logic
GND
-IIK
-IOK
图8-3. Electrical Placement of Clamping Diodes for Each Input and Output
8.4 Device Functional Modes
表8-1. Function Table
INPUTS(1)
OUTPUT(2)
CLR
L
CLK
X
D
X
X
L
Q
L
H
Q0
L
L, H, ↓
↑
H
H
H
H
↑
(1) L = input low, H = input high, ↑= input transitioning from low to
high, ↓= input transitioning from high to low, X = do not care
(2) L = output low, H = output high, Q0 = previous state
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, the SN74LV273A-Q1 is used to synchronize incoming data to the system clock on an 8-bit
bus.
9.2 Typical Application
1D
2D
3D
4D
5D
6D
7D
8D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
Input Data Bus
Bus Controller
Output Data Bus
CLK
CLR
图9-1. Typical Application Diagram
9.2.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV273A-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV273A-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any transient
current required for switching. The logic device can only sink as much current that can be sunk into its ground
connection. Be sure to not exceed the maximum total current through GND listed in the Absolute Maximum
Ratings.
The SN74LV273A-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74LV273A-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
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Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV273A-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74LV273A-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined
in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
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9.2.4 Detailed Design Procedure
1. Add a decoupling capacitor from VCC to GND. The capacitor needs to be placed physically close to the
device and electrically close to both the VCC and GND pins. An example layout is shown in the Layout
section.
2. Ensure the capacitive load at the output is ≤50 pF. This is not a hard limit; it will, however, ensure optimal
performance. This can be accomplished by providing short, appropriately sized traces from the
SN74LV273A-Q1 to one or more of the receiving devices.
3. Ensure the resistive load at the output is larger than (VCC / IO(max)) Ω. This will ensure that the maximum
output current from the Absolute Maximum Ratings is not violated. Most CMOS inputs have a resistive load
measured in MΩ; much larger than the minimum calculated previously.
4. Thermal issues are rarely a concern for logic gates; the power consumption and thermal increase, however,
can be calculated using the steps provided in the application report, CMOS Power Consumption and Cpd
Calculation.
9.2.5 Application Curves
CLR
CLK
D1
Q1
图9-2. Application Timing Diagram
9.3 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Absolute Maximum Ratings section. Each VCC terminal must have a good bypass capacitor to prevent power
disturbance. For devices with a single supply, TI recommends a 0.1-μF capacitor; if there are multiple VCC
terminals, then TI recommends a 0.01-μF or 0.022-μF capacitor for each power terminal. Multiple bypass
capacitors can be paralleled to reject different frequencies of noise. Frequencies of 0.1 μF and 1 μF are
commonly used in parallel. The bypass capacitor must be installed as close as possible to the power terminal for
best results.
9.4 Layout
9.4.1 Layout Guidelines
When using multiple bit logic devices, inputs should not float. In many cases, functions or parts of functions of
digital logic devices are unused. Some examples are when only two inputs of a triple-input AND gate are used,
or when only 3 of the 4-buffer gates are used. Such unused input pins must not be left unconnected because the
undefined voltages at the outside connections result in undefined operational states. All unused inputs of digital
logic devices must be connected to a logic high or logic low voltage, as defined by the input voltage
specifications, to prevent them from floating. The logic level that must be applied to any particular unused input
depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever makes more
sense for the logic function or is more convenient.
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9.4.2 Layout Example
VCC
GND
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to the
device
0.1 ꢀF
CLR
VCC
1
20
19
1Q
1D
2D
2Q
3Q
3D
4D
4Q
2
3
4
5
6
7
8
9
8Q
8D
7D
7Q
6Q
6D
5D
18
17
16
15
14
13
Unused input
tied to GND
Unused output
left floating
GND
12
11
5Q
10
Avoid 90°
corners for
signal lines
GND
CLK
图9-3. Layout Example for the SN74LV273A-Q1 in the WRKS Package
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10 Device and Documentation Support
10.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Power-Up Behavior of Clocked Devices application note
• Texas Instruments, Introduction to Logic application note
10.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates—including silicon errata—go to the product folder for your
device on ti.com. In the upper right-hand corner, click the Alert me button. This registers you to receive a weekly
digest of product information that has changed (if any). For change details, check the revision history of any
revised document.
10.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
10.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
10.5 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
10.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PCLV273AQWRKSRQ1
SN74LV273AQDGSRQ1
SN74LV273AQWRKSRQ1
ACTIVE
ACTIVE
ACTIVE
VQFN
VSSOP
VQFN
RKS
DGS
RKS
20
20
20
3000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
-40 to 125
Samples
Samples
Samples
5000 RoHS & Green
3000 RoHS & Green
NIPDAU
NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
L273Q
LV273AQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
16-Apr-2023
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV273A-Q1 :
Catalog : SN74LV273A
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
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TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV273AQDGSRQ1 VSSOP
SN74LV273AQWRKSRQ1 VQFN
DGS
RKS
20
20
5000
3000
330.0
180.0
16.4
12.4
5.4
2.8
5.4
4.8
1.45
1.2
8.0
4.0
16.0
12.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
17-Apr-2023
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV273AQDGSRQ1
SN74LV273AQWRKSRQ1
VSSOP
VQFN
DGS
RKS
20
20
5000
3000
356.0
210.0
356.0
185.0
35.0
35.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
RKS 20
2.5 x 4.5, 0.5 mm pitch
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4226872/A
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PACKAGE OUTLINE
RKS0020B
VQFN - 1 mm max height
S
C
A
L
E
3
.
3
0
0
PLASTIC QUAD FLATPACK - NO LEAD
2.6
2.4
B
A
PIN 1 INDEX AREA
4.6
4.4
(0.1) MIN
(0.13)
SECTION A-A
TYPICAL
1.0
0.8
C
SEATING PLANE
0.08 C
0.05
0.00
1.05
0.95
2X 0.5
(0.2) TYP
EXPOSED
THERMAL PAD
10
11
14X 0.5
9
12
A
A
2X
3.05
2.95
3.5
2
19
0.3
20X
1
20
0.2
PIN 1 ID
(OPTIONAL)
0.1
C A B
0.45
0.35
20X
0.05
4226762/B 06/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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EXAMPLE BOARD LAYOUT
RKS0020B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(1)
2X (0.5)
1
20
20X (0.6)
2
19
20X (0.25)
(1.25)
(3)
SYMM
2X (3.5)
(4.3)
16X (0.5)
(R0.05) TYP
9
12
(
0.2) VIA
TYP
10
11
SYMM
(2.3)
LAND PATTERN EXAMPLE
SCALE:20X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226762/B 06/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown.
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EXAMPLE STENCIL DESIGN
RKS0020B
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.95)
2X (0.5)
1
20
20X (0.6)
2
19
20X (0.25)
2X (1.31)
16X (0.5)
SYMM
2X (3.5) (4.3)
(0.76)
METAL
TYP
9
12
(R0.05) TYP
10
11
SYMM
(2.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
83% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4226762/B 06/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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Copyright © 2023，德州仪器 (TI) 公司
相关型号：
SN74LV273DW
LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SO-20
ROCHESTER
SN74LV273DWR
LV/LV-A/LVX/H SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SO-20
ROCHESTER
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