SN74LV32ADG4 [TI]
Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 125;
| 型号： | SN74LV32ADG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Quadruple 2-Input Positive-OR Gates 14-SOIC -40 to 125 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总21页 (文件大小：1121K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005
D
D
D
D
D
2-V to 5.5-V V Operation
D
D
D
I
Supports Partial-Power-Down Mode
CC
off
Operation
Max t of 6.5 ns at 5 V
pd
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical V
(Output Ground Bounce)
OLP
<0.8 V at V = 3.3 V, T = 25°C
CC
A
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
Typical V
(Output V Undershoot)
OHV
OH
>2.3 V at V = 3.3 V, T = 25°C
CC
A
Support Mixed-Mode Voltage Operation on
All Ports
− 1000-V Charged-Device Model (C101)
SN54LV32A . . . J OR W PACKAGE
SN74LV32A . . . D, DB, DGV, NS,
OR PW PACKAGE
SN74LV32A . . . RGY PACKAGE
(TOP VIEW)
SN54LV32A . . . FK PACKAGE
(TOP VIEW)
(TOP VIEW)
1
14
3
2
1
20 19
18
1A
1B
1Y
2A
2B
VCC
13 4B
1
2
3
4
5
6
7
14
4A
NC
4Y
1Y
NC
2A
NC
2B
4
5
6
7
8
1B
1Y
2A
2B
2Y
13 4B
12 4A
2
3
4
5
6
17
16
12
11
10
9
4A
4Y
3B
3A
3Y
11
10
9
4Y
3B
3A
15 NC
14
9 10 11 12 13
3B
2Y
GND
7
8
8
NC − No internal connection
description/ordering information
These quadruple 2-input positive-OR gates are designed for 2-V to 5.5-V V operation.
CC
The ’LV32A devices perform the Boolean function Y + A ) B or Y + A • B in positive logic.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
QFN − RGY
SOIC − D
Reel of 1000
Tube of 50
SN74LV32ARGYR
SN74LV32AD
LV32A
LV32A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV32ADR
SN74LV32ANSR
SN74LV32ADBR
SN74LV32APW
SN74LV32APWR
SN74LV32APWT
SN74LV32ADGVR
SNJ54LV32AJ
SOP − NS
74LV32A
LV32A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV32A
TVSOP − DGV
CDIP − J
LV32A
SNJ54LV32AJ
SNJ54LV32AW
SNJ54LV32AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV32AW
SNJ54LV32AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright © 2005, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005
description/ordering information (continued)
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
Y
A
B
X
H
L
H
X
L
H
H
L
logic diagram, each gate (positive logic)
A
B
Y
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Voltage range applied to any output in the high-impedance
or power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V + 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
O
O
CC
Continuous current through V or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
(see Note 3): DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 5.5 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
4. The package thermal impedance is calculated in accordance with JESD 51-5.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005
recommended operating conditions (see Note 5)
SN54LV32A
SN74LV32A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
× 0.7
1.5
× 0.7
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
V
V
V
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
CC
CC
CC
CC
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
CC
V
CC
V
CC
× 0.3
× 0.3
× 0.3
5.5
V
CC
V
CC
V
CC
× 0.3
× 0.3
× 0.3
5.5
V
IL
Low-level input voltage
V
V
Input voltage
0
0
0
0
V
V
I
Output voltage
V
CC
V
CC
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
−2
−6
−2
−6
−12
50
2
I
High-level output current
Low-level output current
OH
mA
−12
50
μA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
OL
6
6
mA
12
12
200
100
20
85
200
100
20
Δt/Δv
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
−55
125
−40
°C
A
NOTE 5: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV32A
SN74LV32A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 μA
= −2 mA
= −6 mA
= −12 mA
= 50 μA
= 2 mA
2 V to 5.5 V
2.3 V
V
CC
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
V
V
V
OH
OL
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
= 6 mA
3 V
= 12 mA
4.5 V
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
μA
μA
μA
I
I
V = V or GND,
I = 0
O
20
20
CC
I
CC
I
off
V or V = 0 to 5.5 V
0
5
5
I
O
3.3 V
3.3
3.3
3.3
3.3
C
V = V or GND
pF
i
I
CC
5 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005
switching characteristics over recommended operating free-air temperature range,
VCC = 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
T = 25°C
A
SN54LV32A
SN74LV32A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
TYP
MAX
MIN
1*
MAX
16*
20
MIN
1
MAX
15
C = 15 pF
L
7.1* 12.8*
9.6 16.2
t
pd
A or B
Y
ns
C = 50 pF
L
1
1
19
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
CC = 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
V
T
A
= 25°C
TYP
5*
SN54LV32A
SN74LV32A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
7.9*
MIN
1*
MAX
9.5*
13
MIN
1
MAX
9.5
C = 15 pF
L
t
pd
A or B
Y
ns
C = 50 pF
L
6.9
11.4
1
1
13
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
VCC = 5 V 0.5 V (unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
3.6*
SN54LV32A
SN74LV32A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
5.5*
7.5
MIN
1*
MAX
6.5*
8.5
MIN
1
MAX
6.5
C = 15 pF
L
t
pd
A or B
Y
ns
C = 50 pF
L
4.9
1
1
8.5
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, VCC = 3.3 V, CL = 50 pF, TA = 25°C (see Note 6)
SN74LV32A
PARAMETER
UNIT
MIN
TYP
0.2
MAX
0.8
V
OL(P)
V
OL(V)
V
OH(V)
V
IH(D)
V
IL(D)
Quiet output, maximum dynamic V
V
V
V
V
V
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.1
3.1
−0.8
OL
OH
2.31
0.99
NOTE 6: Characteristics are for surface-mount packages only.
operating characteristics, TA = 25°C
PARAMETER
TEST CONDITIONS
f = 10 MHz
V
TYP
9.5
UNIT
CC
3.3 V
C
Power dissipation capacitance
C = 50 pF,
pF
pd
L
5 V
11.5
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV32A, SN74LV32A
QUADRUPLE 2-INPUT POSITIVE-OR GATES
SCLS385J − SEPTEMBER 1997 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
R
= 1 kΩ
L
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
Open
PLH PHL
t
C
C
L
/t
V
CC
L
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
Input
Input
CC
CC
50% V
50% V
CC
Data Input
0 V
CC
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
CC
CC
CC
CC
0 V
0 V
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
+ 0.3 V
OL
S1 at V
CC
V
OL
V
OL
(see Note B)
t
t
t
PHL
PLH
PHZ
PZH
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
.
PLZ
PZL
PHL
PHZ
dis
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(6)
(3)
(4/5)
SN74LV32AD
ACTIVE
SOIC
D
14
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
-40 to 85
LV32A
SN74LV32ADBLE
SN74LV32ADBR
OBSOLETE
ACTIVE
SSOP
SSOP
DB
DB
14
14
TBD
Call TI
Call TI
-40 to 85
-40 to 85
2000
2000
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
LV32A
LV32A
LV32A
LV32A
LV32A
LV32A
LV32A
LV32A
74LV32A
LV32A
SN74LV32ADBRE4
SN74LV32ADE4
SN74LV32ADG4
SN74LV32ADGVR
SN74LV32ADR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SSOP
SOIC
SOIC
TVSOP
SOIC
SOIC
SOIC
SO
DB
D
14
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
D
50
Green (RoHS
& no Sb/Br)
DGV
D
2000
2500
2500
2500
2000
90
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
SN74LV32ADRE4
SN74LV32ADRG4
SN74LV32ANSR
SN74LV32APW
D
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
NS
PW
Green (RoHS
& no Sb/Br)
TSSOP
Green (RoHS
& no Sb/Br)
SN74LV32APWLE
SN74LV32APWR
OBSOLETE
ACTIVE
TSSOP
TSSOP
PW
PW
14
14
TBD
Call TI
-40 to 85
-40 to 85
2000
2000
250
Green (RoHS CU NIPDAU | CU SN
& no Sb/Br)
Level-1-260C-UNLIM
LV32A
LV32A
LV32A
LV32A
SN74LV32APWRG4
SN74LV32APWT
SN74LV32ARGYR
ACTIVE
ACTIVE
ACTIVE
TSSOP
TSSOP
VQFN
PW
PW
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-2-260C-1 YEAR
-40 to 85
-40 to 85
-40 to 85
Green (RoHS
& no Sb/Br)
RGY
3000
Green (RoHS
& no Sb/Br)
(1) The marketing status values are defined as follows:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
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provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV32A :
Automotive: SN74LV32A-Q1
•
Enhanced Product: SN74LV32A-EP
•
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
10-Jun-2014
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Apr-2014
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV32ADBR
SN74LV32ADGVR
SN74LV32ADR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
14
2000
2000
2500
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
12.4
16.4
12.4
12.4
12.4
12.4
12.4
8.2
6.8
6.5
6.9
6.9
6.9
6.9
3.75
6.6
4.0
9.0
5.6
5.6
5.6
5.6
3.75
2.5
1.6
2.1
1.6
1.6
1.6
1.6
1.15
12.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
12.0
16.0
12.0
12.0
12.0
12.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
SN74LV32APWR
SN74LV32APWR
SN74LV32APWRG4
SN74LV32APWT
SN74LV32ARGYR
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
PW
PW
RGY
3000
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
29-Apr-2014
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV32ADBR
SN74LV32ADGVR
SN74LV32ADR
SSOP
TVSOP
SOIC
DB
DGV
D
14
14
14
14
14
14
14
14
2000
2000
2500
2000
2000
2000
250
367.0
367.0
367.0
367.0
364.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
364.0
367.0
367.0
367.0
38.0
35.0
38.0
35.0
27.0
35.0
35.0
35.0
SN74LV32APWR
SN74LV32APWR
SN74LV32APWRG4
SN74LV32APWT
SN74LV32ARGYR
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
PW
PW
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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