SN74LV367ADGV [TI]
HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS; HEX缓冲器和线路驱动器，具有三态输出
| 型号： | SN74LV367ADGV |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS |
| 文件： | 总8页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
SN54LV367A . . . J OR W PACKAGE
SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Typical V
< 0.8 V at V
(Output Ground Bounce)
OLP
= 3.3 V, T = 25°C
1OE
1A1
1Y1
1A2
1Y2
1A3
1Y3
GND
V
CC
1
2
3
4
5
6
7
8
16
15
14
13
CC
A
2OE
2A2
2Y2
Typical V
> 2 V at V
(Output V
Undershoot)
OHV
CC
OH
= 3.3 V, T = 25°C
A
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
12 2A1
11
10
9
2Y1
1A4
1Y4
ESD Protection Exceeds JESD-22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
SN54LV367A . . . FK PACKAGE
(TOP VIEW)
Package Options Include Plastic
Small-Outline (D, NS), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), and
Thin Shrink Small-Outline (PW) Packages,
Ceramic Flat (W) Packages, Chip Carriers
(FK), and DIPs (J)
3
2
1
20 19
18
2A2
2Y2
NC
1Y1
1A2
NC
4
5
6
7
8
17
16
description
15 2A1
14
9 10 11 12 13
1Y2
1A3
The ’LV367A devices are hex buffers and line
drivers designed for 2-V to 5.5-V V operation.
2Y1
CC
These devices are designed specifically to
improve both the performance and density of
3-state memory address drivers, clock drivers,
and bus-oriented receivers and transmitters.
NC – No internal connection
The ’LV367A devices are organized as dual 4-line and 2-line buffers/drivers with active-low output-enable (1OE
and 2OE) inputs. When OE is low, the device passes noninverted data from the A inputs to the Y outputs. When
OE is high, the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54LV367A is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV367A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each buffer/driver)
INPUTS
OUTPUT
Y
OE
A
H
L
L
L
H
L
H
X
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1999, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
†
logic symbol
1
EN
1OE
2
1A1
4
3
5
7
9
1Y1
1Y2
1Y3
1Y4
1A2
6
1A3
10
1A4
15
EN
2OE
12
2A1
11
13
2Y1
2Y2
14
2A2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
logic diagram (positive logic)
1
15
12
1OE
2OE
2A1
2
3
11
1A1
1Y1
2Y1
To Three Other Channels
To One Other Channel
Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range applied in the high or low state, V (see Notes 1 and 2) . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Output voltage range applied in high-impedance or power-off state, V (see Note 1) . . . . . . . –0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
recommended operating conditions (see Note 4)
SN54LV367A
SN74LV367A
UNIT
MIN
2
MAX
MIN
2
MAX
V
V
Supply voltage
5.5
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
× 0.3
× 0.3
V
V
V
× 0.3
× 0.3
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
V
V
Input voltage
0
0
0
5.5
0
0
0
5.5
V
V
I
High or low state
3-state
V
V
CC
5.5
CC
5.5
Output voltage
O
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
–50
–2
–50
–2
–8
–16
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
–8
mA
µA
–16
50
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
8
8
mA
16
16
200
100
20
85
0
0
0
200
100
20
0
0
0
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
T
–55
125
–40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV367A
SN74LV367A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= –50 µA
2 V to 5.5 V
2.3 V
V
–0.1
2
V
CC
–0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= –2 mA
= –8 mA
= –16 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
±1
0.1
0.4
0.44
0.55
±1
V
OL
= 8 mA
3 V
= 16 mA
4.5 V
I
I
I
I
V = V
or GND
5.5 V
µA
µA
µA
µA
pF
pF
I
I
CC
V
= V
or GND
5.5 V
±5
±5
OZ
CC
off
O
CC
V = V
or GND,
I
O
= 0
5.5 V
20
20
I
CC
V or V = 0 to 5.5 V
0 V
5
5
I
O
C
C
V = V
or GND
or GND
3.3 V
3
3
i
I
CC
CC
V = V
3.3 V
5.2
5.2
o
I
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V ± 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
6.4
SN54LV367A SN74LV367A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
12.7
14.9
14.9
MIN
1
MAX
16
MIN
1
MAX
16
t
t
t
t
t
t
*
*
A
Y
Y
Y
Y
Y
Y
pd
6.9
1
20
1
20
OE
OE
A
C
= 15 pF
ns
en
L
*
6.4
1
20
1
20
dis
pd
en
dis
8.6
9.4
17.5
19.7
19.7
1
1
1
21
25
25
1
1
1
21
25
25
OE
OE
C
C
= 50 pF
= 50 pF
ns
ns
L
L
10.1
t
2
2
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
4.7
SN54LV367A SN74LV367A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
8.3
MIN
1
MAX
10
MIN
1
MAX
10
t
t
t
t
t
t
*
*
A
Y
Y
Y
Y
Y
Y
pd
5.1
10.5
10.5
1
12.5
12.5
1
12.5
12.5
OE
OE
A
C
= 15 pF
ns
en
L
*
4.9
1
1
dis
pd
en
dis
6.2
6.8
7.3
11.8
14
1
1
1
13.5
16
1
1
1
13.5
16
OE
OE
C
C
= 50 pF
= 50 pF
ns
ns
L
L
13.6
15.5
15.5
t
1.5
1.5
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
switching characteristics over recommended operating free-air temperature range,
V
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
3.6
SN54LV367A SN74LV367A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
MAX
5.9
MIN
1
MAX
7
MIN
1
MAX
7
t
t
t
t
t
t
*
*
A
Y
Y
Y
Y
Y
Y
pd
3.8
7.2
1
8.5
8.5
1
8.5
8.5
OE
OE
A
C
= 15 pF
ns
en
L
*
2.6
7.2
1
0
dis
pd
en
dis
4.5
4.9
4.5
7.9
9.2
9.2
1
1
1
9
10.5
10.5
1
1
0
9
10.5
10.5
OE
OE
C
C
= 50 pF
= 50 pF
ns
ns
L
L
t
1
1
sk(o)
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV367A
PARAMETER
UNIT
MIN
TYP
0.5
–0.2
3
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.8
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
14.9
17.4
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV367A, SN74LV367A
HEX BUFFERS AND LINE DRIVERS
WITH 3-STATE OUTPUTS
SCLS398B – APRIL 1998 – REVISED SEPTEMBER 1999
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
GND
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
V
CC
Open Drain
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
Timing Input
CC
0 V
t
w
t
h
t
V
su
CC
V
CC
50% V
50% V
CC
Input
Input
CC
50% V
50% V
CC
Data Input
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
50% V
50% V
50% V
t
CC
CC
t
CC
CC
0 V
0 V
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
– 0.3 V
50% V
50% V
50% V
CC
CC
CC
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PHL
PHZ
PZH
PLH
.
Figure 1. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
相关型号：
©2020 ICPDF网 联系我们和版权申明