SN74LV367APWTG4_技术文档

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ꢋꢌꢍ ꢎꢏꢐ ꢐ ꢌꢑꢀ ꢉꢁꢒ ꢄ ꢓꢁꢌ ꢒ ꢑꢓ ꢅ ꢌꢑ ꢀ

ꢔ ꢓꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗ ꢏꢕ ꢘꢏ ꢕꢀ

SCLS398G − APRIL 1998 − REVISED APRIL 2005

SN54LV367A . . . J OR W PACKAGE

SN74LV367A . . . D, DB, DGV, NS, OR PW PACKAGE

(TOP VIEW)

D

2-V to 5.5-V V

Operation

CC

Max t of 7 ns at 5 V

pd

Typical V

<0.8 V at V

(Output Ground Bounce)

OLP

CC

1OE

1A1

1Y1

1A2

1Y2

1A3

1Y3

GND

V

CC

1

2

3

4

5

6

7

8

16

15

14

13

= 3.3 V, T = 25°C

A

2OE

2A2

2Y2

Typical V

>2.3 V at V

(Output V

Undershoot)

OHV

CC

OH

= 3.3 V, T = 25°C

A

Support Mixed-Mode Voltage Operation on

All Ports

12 2A1

11

10

9

2Y1

1A4

1Y4

Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

ESD Protection Exceeds JESD 22

− 2000-V Human-Body Model (A114-A)

− 200-V Machine Model (A115-A)

SN54LV367A . . . FK PACKAGE

(TOP VIEW)

− 1000-V Charged-Device Model (C101)

description/ordering information

3

2

1

20 19

18

2A2

2Y2

NC

1Y1

1A2

NC

The ’LV367A devices are hex buffers and line

4

5

6

7

8

drivers designed for 2-V to 5.5-V V

operation.

17

16

CC

These devices are designed specifically to

improve both the performance and density of

3-state memory address drivers, clock drivers,

and bus-oriented receivers and transmitters.

15 2A1

14

9 10 11 12 13

1Y2

1A3

2Y1

The ’LV367A devices are organized as dual 4-line

and 2-line buffers/drivers with active-low

output-enable (1OE and 2OE) inputs. When OE is

low, the device passes noninverted data from the

A inputs to the Y outputs. When OE is high, the

outputs are in the high-impedance state.

NC − No internal connection

To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup

CC

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

ORDERING INFORMATION

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

†

PACKAGE

T

A

Tube of 40

SN74LV367AD

SOIC − D

LV367A

Reel of 2500

Reel of 2000

Reel of 250

Reel of 2000

Tube of 25

SN74LV367ADR

SN74LV367ANSR

SN74LV367ADBR

SN74LV367APWR

SN74LV367APWT

SN74LV367ADGVR

SNJ54LV367AJ

SOP − NS

74LV367A

LV36A

SSOP − DB

−40°C to 85°C

TSSOP − PW

LV367A

TVSOP − DGV

CDIP − J

LV367A

SNJ54LV367AJ

SNJ54LV367AW

SNJ54LV367AFK

−55°C to 125°C

CFP − W

Tube of 150

Tube of 55

SNJ54LV367AW

SNJ54LV367AFK

LCCC − FK

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright  2005, Texas Instruments Incorporated

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1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ

ꢋ ꢌꢍ ꢎ ꢏꢐ ꢐ ꢌ ꢑꢀ ꢉꢁ ꢒ ꢄꢓ ꢁ ꢌ ꢒꢑ ꢓ ꢅꢌ ꢑꢀ

ꢔꢓ ꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗꢏꢕ ꢘ ꢏꢕꢀ

SCLS398G − APRIL 1998 − REVISED APRIL 2005

FUNCTION TABLE

(each buffer/driver)

INPUTS

OUTPUT

Y

OE

A

H

L

H

L

H

X

Z

logic diagram (positive logic)

1

15

1OE

2OE

2A1

2

3

12

11

1A1

1Y1

2Y1

To Three Other Channels

Pin numbers shown are for the D, DB, DGV, J, NS, PW, and W packages.

To One Other Channel

†

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, V

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

CC

Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

I

Voltage range applied to any output in the high-impedance or

power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V

O

Output voltage range applied in the high or low state, V (see Notes 1 and 2) . . . . . . −0.5 V to V

+ 0.5 V

O

CC

Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA

IK

I

Output clamp current, I

(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA

OK

O

Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 mA

Continuous current through V

O

CC

or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 mA

Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W

JA

DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W

DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120°C/W

NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64°C/W

PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W

Storage temperature range, T

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C

stg

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and

functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not

implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.

2. This value is limited to 5.5 V maximum.

3. The package thermal impedance is calculated in accordance with JESD 51-7.

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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ꢋꢌ ꢍ ꢎꢏꢐ ꢐ ꢌꢑꢀ ꢉꢁꢒ ꢄ ꢓꢁꢌ ꢒ ꢑꢓ ꢅ ꢌꢑ ꢀ

ꢔ ꢓꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗ ꢏꢕ ꢘ ꢏꢕꢀ

SCLS398G − APRIL 1998 − REVISED APRIL 2005

recommended operating conditions (see Note 4)

SN54LV367A

SN74LV367A

UNIT

MIN

2

MAX

MIN

2

MAX

V

Supply voltage

5.5

V

CC

V

= 2 V

1.5

CC

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2 V

V

× 0.7

V

× 0.7

CC

High-level input voltage

V

IH

× 0.7

0.5

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

V

× 0.3

V

× 0.3

CC

V

IL

Low-level input voltage

V

Input voltage

0

5.5

0

5.5

I

High or low state

3-state

V

CC

5.5

CC

5.5

Output voltage

V

O

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

V

CC

= 2 V

−50

−2

−50

−2

−8

−16

50

2

µA

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2 V

I

High-level output current

Low-level output current

OH

OL

−8

mA

−16

50

µA

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

= 2.3 V to 2.7 V

= 3 V to 3.6 V

= 4.5 V to 5.5 V

2

I

8

mA

16

200

100

20

85

200

100

20

∆t/∆v

Input transition rise or fall rate

Operating free-air temperature

ns/V

T

−55

125

−40

°C

A

NOTE 4: All unused inputs of the device must be held at V

or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

CC

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3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ

ꢋ ꢌꢍ ꢎ ꢏꢐ ꢐ ꢌ ꢑꢀ ꢉꢁ ꢒ ꢄꢓ ꢁ ꢌ ꢒꢑ ꢓ ꢅꢌ ꢑꢀ

ꢔꢓ ꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗꢏꢕ ꢘ ꢏꢕꢀ

SCLS398G − APRIL 1998 − REVISED APRIL 2005

electrical characteristics over recommended operating free-air temperature range (unless

otherwise noted)

SN54LV367A

SN74LV367A

PARAMETER

TEST CONDITIONS

UNIT

V

CC

MIN

TYP

MAX

MIN

TYP

MAX

I

= −50 µA

= −2 mA

= −8 mA

= −16 mA

= 50 µA

= 2 mA

2 V to 5.5 V

2.3 V

V

−0.1

2

V

CC

−0.1

2

OH

OL

CC

V

OH

3 V

2.48

3.8

2.48

3.8

4.5 V

2 V to 5.5 V

2.3 V

0.1

0.4

0.44

0.55

1

0.1

0.4

0.44

0.55

1

V

OL

= 8 mA

3 V

= 16 mA

4.5 V

I

V = 5.5 V or GND

0 to 5.5 V

5.5 V

µA

pF

I

V

= V or GND

O CC

or GND,

5

OZ

CC

off

V = V

CC

I

O

= 0

5.5 V

20

I

V or V = 0 to 5.5 V

0

5

I

O

C

V = V

or GND

3.3 V

3

i

I

CC

V = V

3.3 V

5.2

o

I

CC

switching characteristics over recommended operating free-air temperature range,

V

= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)

CC

T = 25°C

A

SN54LV367A SN74LV367A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MIN

TYP

MAX

MIN

1*

MAX

16*

MIN

1

MAX

16

t

A

Y

6.4* 12.7*

6.9* 14.9*

6.4* 14.9*

pd

en

dis

pd

en

dis

1*

20*

1

20

OE

A

C

= 15 pF

= 50 pF

ns

L

1*

20*

1

20

8.6

9.4

17.5

19.7

1

21

25

1

21

25

OE

ns

10.1

t

2

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

switching characteristics over recommended operating free-air temperature range,

V

= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

SN54LV367A SN74LV367A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MIN

MAX

MIN

MAX

MIN

1

MAX

10

t

A

Y

4.7*

8.3*

1*

10*

pd

en

dis

pd

en

dis

5.1* 10.5*

4.9* 10.5*

1* 12.5*

1

12.5

OE

A

C

= 15 pF

= 50 pF

ns

L

1

6.2

6.8

7.3

11.8

14

1

13.5

16

1

13.5

16

OE

ns

13.6

15.5

t

1.5

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

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4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢈ ꢉꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆꢇ ꢈꢉ

ꢋꢌ ꢍ ꢎꢏꢐ ꢐ ꢌꢑꢀ ꢉꢁꢒ ꢄ ꢓꢁꢌ ꢒ ꢑꢓ ꢅ ꢌꢑ ꢀ

ꢔ ꢓꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗ ꢏꢕ ꢘ ꢏꢕꢀ

SCLS398G − APRIL 1998 − REVISED APRIL 2005

switching characteristics over recommended operating free-air temperature range,

V

= 5 V 0.5 V (unless otherwise noted) (see Figure 1)

CC

T

A

= 25°C

TYP

3.6*

SN54LV367A SN74LV367A

FROM

(INPUT)

TO

(OUTPUT)

LOAD

CAPACITANCE

PARAMETER

UNIT

MIN

MAX

5.9*

7.2*

MIN

1*

MAX

7*

MIN

1

MAX

7

t

A

Y

pd

en

dis

pd

en

dis

3.8*

1*

8.5*

1

8.5

OE

A

C

= 15 pF

= 50 pF

ns

L

2.6*

1*

0

4.5

4.9

4.5

7.9

9.2

1

9

10.5

1

0

9

10.5

OE

ns

t

1

sk(o)

* On products compliant to MIL-PRF-38535, this parameter is not production tested.

noise characteristics, V

= 3.3 V, C = 50 pF, T = 25°C (see Note 5)

CC

L

A

SN74LV367A

PARAMETER

UNIT

MIN

TYP

0.5

−0.2

3

MAX

V

Quiet output, maximum dynamic V

0.8

V

OL(P)

OL(V)

OH(V)

IH(D)

IL(D)

OL

Quiet output, minimum dynamic V

High-level dynamic input voltage

Low-level dynamic input voltage

−0.8

OL

OH

2.31

0.99

NOTE 5: Characteristics are for surface-mount packages only.

operating characteristics, T = 25°C

A

PARAMETER

TEST CONDITIONS

= 50 pF, f = 10 MHz

L

V

TYP

14.9

17.4

UNIT

CC

3.3 V

C

Power dissipation capacitance

C

pF

pd

5 V

ꢘ

ꢑ

ꢗ

ꢒ

ꢏ

ꢥ

ꢕ

ꢘ

ꢑ

ꢌ

ꢅ

ꢓ

ꢌ

ꢔ

ꢛ

ꢣ

ꢦ

ꢞ

ꢧ

ꢡ

ꢤ

ꢙ

ꢛ

ꢞ

ꢣ

ꢟ

ꢞ

ꢣ

ꢟ

ꢢ

ꢧ

ꢣ

ꢜ

ꢨ

ꢧ

ꢞ

ꢝ

ꢠ

ꢝꢢ ꢜ ꢛ ꢯꢣ ꢨꢚ ꢤ ꢜ ꢢ ꢞꢦ ꢝꢢ ꢰ ꢢ ꢪꢞ ꢨꢡꢢ ꢣꢙꢫ ꢥ ꢚꢤ ꢧꢤ ꢟꢙ ꢢꢧ ꢛꢜ ꢙꢛ ꢟ ꢝꢤ ꢙꢤ ꢤꢣ ꢝ ꢞꢙ ꢚꢢꢧ

ꢟ

ꢙ

ꢜ

ꢛ

ꢣ

ꢙ

ꢚ

ꢢ

ꢦ

ꢞ

ꢧ

ꢡ

ꢤ

ꢙ

ꢛ

ꢰ

ꢢ

ꢞ

ꢧ

ꢜ

ꢨ

ꢢ

ꢟ

ꢛ

ꢦ

ꢛ

ꢟ

ꢤ

ꢙ

ꢛ

ꢞ

ꢣ

ꢜ

ꢤ

ꢧ

ꢢ

ꢝ

ꢢ

ꢜ

ꢛ

ꢯ

ꢣ

ꢯ

ꢞ

ꢤ

ꢪ

ꢜ

ꢫ

ꢕ

ꢢ

ꢬ

ꢤ

ꢜ

ꢓ

ꢣ

ꢜ

ꢙ

ꢧ

ꢠ

ꢡ

ꢢ

ꢣ

ꢟ ꢚꢤ ꢣ ꢯꢢ ꢞꢧ ꢝꢛ ꢜ ꢟ ꢞꢣ ꢙꢛ ꢣꢠꢢ ꢙ ꢚꢢ ꢜ ꢢ ꢨꢧ ꢞꢝ ꢠꢟꢙ ꢜ ꢭ ꢛꢙꢚ ꢞꢠꢙ ꢣꢞꢙ ꢛꢟꢢ ꢫ

ꢙ

ꢜ

ꢧ

ꢢ

ꢜ

ꢢ

ꢧ

ꢰ

ꢢ

ꢜ

ꢙ

ꢚ

ꢢ

ꢧ

ꢛ

ꢯ

ꢚ

ꢙ

ꢞ

5

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢀꢁ ꢈꢃ ꢄꢅ ꢆ ꢇꢈ ꢉ

ꢋ ꢌꢍ ꢎ ꢏꢐ ꢐ ꢌ ꢑꢀ ꢉꢁ ꢒ ꢄꢓ ꢁ ꢌ ꢒꢑ ꢓ ꢅꢌ ꢑꢀ

ꢔꢓ ꢕ ꢋ ꢆ ꢖꢀꢕꢉꢕ ꢌ ꢗꢏꢕ ꢘ ꢏꢕꢀ

SCLS398G − APRIL 1998 − REVISED APRIL 2005

PARAMETER MEASUREMENT INFORMATION

V

CC

Open

GND

S1

R

= 1 kΩ

L

TEST

S1

From Output

Under Test

Test

Point

From Output

Under Test

t

/t

Open

PLH PHL

/t

C

L

t

V

CC

L

PLZ PZL

/t

(see Note A)

GND

PHZ PZH

Open Drain

V

CC

LOAD CIRCUIT FOR

TOTEM-POLE OUTPUTS

3-STATE AND OPEN-DRAIN OUTPUTS

V

CC

50% V

CC

Timing Input

0 V

t

w

t

h

t

su

V

CC

V

CC

50% V

CC

50% V

CC

Input

50% V

CC

50% V

CC

Data Input

0 V

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

SETUP AND HOLD TIMES

V

CC

V

CC

Output

Control

50% V

CC

50% V

CC

50% V

CC

50% V

CC

0 V

t

PZL

PLZ

t

PHL

PLH

Output

Waveform 1

V

≈V

OH

CC

In-Phase

Output

50% V

CC

50% V

CC

V

S1 at V

(see Note B)

CC

V

+ 0.3 V

OL

V

OL

t

PHL

PLH

PZH

PHZ

Output

Waveform 2

S1 at GND

V

OH

V

OH

Out-of-Phase

Output

− 0.3 V

OH

50% V

CC

50% V

CC

≈0 V

V

OL

(see Note B)

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

INVERTING AND NONINVERTING OUTPUTS

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

LOW- AND HIGH-LEVEL ENABLING

NOTES: A. includes probe and jig capacitance.

C

L

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.

O

r

f

D. The outputs are measured one at a time, with one input transition per measurement.

E.

F.

G.

t

and t

PLH

are the same as t

.

dis

PLZ

PZL

PHL

PHZ

PZH

are the same as t

.

en

are the same as t .

pd

H. All parameters and waveforms are not applicable to all devices.

Figure 1. Load Circuit and Voltage Waveforms

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

PACKAGING INFORMATION

Orderable Device

SN74LV367AD

Status ⁽¹⁾

ACTIVE

Package Package

Pins Package Eco Plan ⁽²⁾Lead/Ball Finish MSL Peak Temp ⁽³⁾

Qty

Type

Drawing

SOIC

D

16

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV367ADBR

SN74LV367ADBRE4

SN74LV367ADBRG4

SN74LV367ADE4

SSOP

SOIC

DB

D

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV367ADG4

SOIC

D

40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV367ADGVR

SN74LV367ADGVRE4

SN74LV367ADGVRG4

SN74LV367ADR

TVSOP

SOIC

DGV

D

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SN74LV367ADRE4

SN74LV367ADRG4

SN74LV367ANSR

SN74LV367ANSRE4

SN74LV367ANSRG4

SN74LV367APWR

SN74LV367APWRE4

SN74LV367APWRG4

SN74LV367APWT

SN74LV367APWTE4

SN74LV367APWTG4

SN74LV367AQPWRQ1

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SOIC

D

2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

NS

PW

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

SO

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

TSSOP

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM

no Sb/Br)

OBSOLETE TSSOP

TBD

Call TI

⁽¹⁾The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

18-Sep-2008

(2)

Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check

http://www.ti.com/productcontent for the latest availability information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered

at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and

package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS

compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame

retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is

provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the

accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take

reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on

incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited

information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI

to Customer on an annual basis.

Addendum-Page 2

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device

Package Package Pins

Type Drawing

SPQ

Reel

A0

B0

K0

P1

W

Pin1

Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant

(mm) W1 (mm)

SN74LV367ADBR

SN74LV367ADGVR

SN74LV367ADR

SSOP

TVSOP

SOIC

DB

DGV

D

16

2000

2500

2000

250

330.0

16.4

12.4

16.4

12.4

8.2

6.8

6.5

8.2

6.9

6.6

4.0

2.5

1.6

2.1

2.5

1.6

12.0

8.0

16.0

12.0

16.0

12.0

Q1

10.3

10.5

5.6

8.0

SN74LV367ANSR

SN74LV367APWR

SN74LV367APWT

SO

NS

12.0

8.0

TSSOP

PW

5.6

8.0

Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION

www.ti.com

14-Jul-2012

*All dimensions are nominal

Device

Package Type Package Drawing Pins

SPQ

Length (mm) Width (mm) Height (mm)

SN74LV367ADBR

SN74LV367ADGVR

SN74LV367ADR

SSOP

TVSOP

SOIC

DB

DGV

D

16

2000

2500

2000

250

367.0

333.2

367.0

345.9

367.0

38.0

35.0

28.6

38.0

35.0

SN74LV367ANSR

SN74LV367APWR

SN74LV367APWT

SO

NS

TSSOP

PW

Pack Materials-Page 2

MECHANICAL DATA

MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000

DGV (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

24 PINS SHOWN

0,23

0,13

M

0,07

0,40

24

13

0,16 NOM

4,50

4,30

6,60

6,20

Gage Plane

0,25

0°–ā8°

0,75

1

12

0,50

A

Seating Plane

0,08

0,15

0,05

1,20 MAX

PINS **

14

16

20

24

38

48

56

DIM

A MAX

A MIN

3,70

3,50

3,70

3,50

5,10

4,90

5,10

4,90

7,90

7,70

9,80

9,60

11,40

11,20

4073251/E 08/00

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.

D. Falls within JEDEC: 24/48 Pins – MO-153

14/16/20/56 Pins – MO-194

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**)

PLASTIC SMALL-OUTLINE

28 PINS SHOWN

0,38

0,22

0,65

28

M

0,15

15

0,25

0,09

5,60

5,00

8,20

7,40

Gage Plane

1

14

0,25

A

0°–ā8°

0,95

0,55

Seating Plane

0,10

2,00 MAX

0,05 MIN

PINS **

14

16

20

24

28

30

38

DIM

6,50

5,90

6,50

5,90

7,50

8,50

7,90

10,50

9,90

10,50 12,90

A MAX

A MIN

6,90

9,90

12,30

4040065 /E 12/01

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.

D. Falls within JEDEC MO-150

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

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TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

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TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265


型号：	SN74LV367APWTG4
厂家：	TEXAS INSTRUMENTS
描述：	HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS HEX缓冲器和线路驱动器，具有三态输出驱动器输出元件
文件：	总18页 (文件大小：734K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SN74LV367APWTG4 [TI]

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