SN74LV373ATPWG4 [TI]
OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS; 八路透明D类锁存器与三态输出
| 型号： | SN74LV373ATPWG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | OCTAL TRANSPARENT D-TYPE LATCH WITH 3-STATE OUTPUTS |
| 文件： | 总20页 (文件大小：877K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV373AT
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES630B–JULY 2005–REVISED AUGUST 2005
FEATURES
•
•
•
•
Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Typical tpd of 5.1 ns at 5 V
•
•
•
Ioff Supports Partial-Power-Down Mode
Operation
Latch-Up Performance Exceeds 250 mA Per
JESD 17
Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 5 V, TA = 25°C
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
•
•
Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 5 V, TA = 25°C
Supports Mixed-Mode Voltage Operation on
All Ports
– 1000-V Charged-Device Model (C101)
xxxxxxx
DB, DW, NS, OR PW PACKAGE
(TOP VIEW)
RGY PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
8Q
8D
7D
7Q
6Q
1
20
19
18
17
16
15
14
13
12
2
3
4
5
6
7
8
9
1Q
1D
2D
2Q
3Q
3D
4D
4Q
8Q
8D
7D
7Q
6Q
6D
5D
5Q
14 6D
13 5D
12 5Q
11 LE
GND 10
10
11
DESCRIPTION/ORDERING INFORMATION
The SN74LV373AT is an octal transparent D-type latch. While the latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D
inputs.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
SN74LV373ATRGYR
SN74LV373ATDW
TOP-SIDE MARKING
VV373
QFN – RGY
SOIC – DW
Reel of 1000
Tube of 25
LV373AT
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 70
SN74LV373ATDWR
SN74LV373ATNSR
SN74LV373ATDBR
SN74LV373ATPW
SOP – NS
74LV373AT
LV373AT
–40°C to 125°C
SSOP – DB
TSSOP – PW
Reel of 2000
Reel of 250
SN74LV373ATPWR
SN74LV373ATPWT
LV373AT
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV373AT
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES630B–JULY 2005–REVISED AUGUST 2005
DESCRIPTION/ORDERING INFORMATION (CONTINUED)
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or
low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without need
for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
(EACH LATCH)
INPUTS
OUTPUT
Q
OE
l
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q0
Z
H
X
LOGIC DIAGRAM (POSITIVE LOGIC)
1
OE
LE
11
3
C1
1D
2
1Q
1D
To Seven Other Channels
2
SN74LV373AT
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES630B–JULY 2005–REVISED AUGUST 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
Output voltage range(2)(3)
7
7
7
V
VO
VO
IIK
V
–0.5 VCC + 0.5
V
Input clamp current
VI < 0
–20
±50
±35
±70
70
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0 or VO > VCC
VO = 0 to VCC
Continuous output current
Continuous current through VCC or GND
DB package(4)
DW package(4)
NS package(4)
PW package(4)
RGY package(5)
58
θJA
Package thermal impedance
Storage temperature range
60
°C/W
°C
83
37
Tstg
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) This value is limited to 5.5 V maximum.
(4) The package thermal impedance is calculated in accordance with JESD 51-7.
(5) The package thermal impedance is calculated in accordance with JESD 51-5.
Recommended Operating Conditions(1)
MIN
4.5
2
MAX UNIT
VCC
VIH
VIL
VI
Supply voltage
5.5
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
0.8
5.5
VCC
5.5
–16
16
0
0
0
High or low state
3-state
VO
Output voltage
V
IOH
IOL
High-level output current
Low-level output current
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
VCC = 4.5 V to 5.5 V
mA
mA
ns/V
°C
∆t/∆v Input transition rise or fall rate
TA Operating free-air temperature
20
–40
125
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LV373AT
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES630B–JULY 2005–REVISED AUGUST 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
TA = –40°C TA = –40°C
to 85°C to 125°C
TA = 25°C
PARAMETER
TEST CONDITIONS
IOH = –50 µA
VCC
UNIT
MIN TYP
MAX MIN MAX MIN MAX
4.5 V
4.5 V
4.4
3.8
4.5
4.4
3.8
4.4
3.8
VOH
V
V
IOH = –16 mA
IOL = 100 µA
4.5 V
0
0.1
0.55
±0.1
±0.25
2
0.1
0.55
±1
0.1
0.55
±1
VOL
IOL = 16 mA
4.5 V
II
VI = 5.5 or GND
VO = VCC or GND
VI = VCC or GND,
One input at 3.4 V,
0 to 5.5 V
5.5 V
µA
µA
µA
IOZ
ICC
±2.5
20
±2.5
20
IO = 0
5.5 V
(1)
∆ICC
5.5 V
0
40
50
50
µA
Other inputs at VCC or GND
VI or VO = 0 to 5.5 V
VI = VCC or GND
Ioff
Ci
0.5
10
5
5
µA
pF
pF
4
10
10
Co
VO = VCC or GND
7.5
(1) This is the increase in supply current for each input at one of the specified TTL voltage levels, rather than 0 V or VCC
.
Timing Requirements
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = –40°C
to 85°C
TA = –40°C
to 125°C
TA = 25°C
UNIT
MIN
6.5
1.5
3.5
MAX
MIN
8.5
1.5
3.5
MAX
MIN MAX
tw
tsu
th
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
8.5
1.5
3.5
ns
ns
ns
High or low
High or low
Switching Characteristics
over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
TA = –40°C TA = –40°C
TA = 25°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
to 85°C
to 125°C
PARAMETER
UNIT
MIN TYP MAX MIN MAX MIN
MAX
10
14
13
9
D
Q
Q
Q
Q
Q
Q
Q
Q
2.9
3.5
3.5
1.7
4.4
4.8
5
5.1
8.5
1
1
1
1
1
1
1
1
9.5
13.5
12.5
8.5
1
1
1
1
1
1
1
1
tpd
LE
OE
OE
D
7.7 12.3
6.3 10.9
CL = 15 pF
ns
ten
tdis
3.3
5.9
7.2
9.5
10.5
14.5
13.5
12
11
15
14
12.5
1
tpd
LE
OE
OE
8.5 13.3
7.1 11.9
8.8 11.2
ten
tdis
CL = 50 pF
ns
3
tsk(o)
1
4
SN74LV373AT
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES630B–JULY 2005–REVISED AUGUST 2005
Noise Characteristics(1)
VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
MIN
TYP
0.8
MAX UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(D)I
VIL(D)
1
V
V
V
V
V
–0.6
2.9
–0.8
Quiet output, minimum dynamic VOH
High-level dymanic input voltage
Low-level dynamic input voltage
2.31
0.99
(1) Characteristics are for surface-mount packages only.
Operating Characteristics
VCC = 5 V, TA = 25°C
PARAMETER
TEST CONDITIONS
TYP
15.5
UNIT
Cpd
Power dissipation capacitance
Outputs enabled
CL = 50 pF,
f = 10 MHz
pF
5
SN74LV373AT
OCTAL TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
www.ti.com
SCES630B–JULY 2005–REVISED AUGUST 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
S1
Open
GND
R
L
= 1 kΩ
TEST
/t
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
Open
PLH PHL
C
L
C
L
t
/t
V
CC
PLZ PZL
(see Note A)
(see Note A)
/t
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
0 V
1.5 V
Timing Input
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
0 V
t
t
PZL
PLZ
t
t
t
PHL
PLH
Output
Waveform 1
≈V
V
CC
OH
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
CC
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
t
t
PZH
PHZ
PHL
PLH
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
− 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PHL
PHZ
are the same as t
PZH
en
are the same as t .
PLH pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuits and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
PACKAGING INFORMATION
Orderable Device
SN74LV373ATDB
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SSOP
DB
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
20
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV373ATDBE4
SN74LV373ATDBG4
SN74LV373ATDBR
SN74LV373ATDBRE4
SN74LV373ATDBRG4
SN74LV373ATDW
SSOP
SSOP
SSOP
SSOP
SSOP
SOIC
DB
DB
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DB
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DW
DW
DW
DW
NS
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV373ATDWG4
SN74LV373ATDWR
SN74LV373ATDWRG4
SN74LV373ATNSR
SN74LV373ATNSRG4
SN74LV373ATPW
SOIC
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
VQFN
VQFN
PW
PW
PW
PW
PW
PW
PW
PW
PW
RGY
RGY
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV373ATPWE4
SN74LV373ATPWG4
SN74LV373ATPWR
SN74LV373ATPWRE4
SN74LV373ATPWRG4
SN74LV373ATPWT
SN74LV373ATPWTE4
SN74LV373ATPWTG4
SN74LV373ATRGYR
SN74LV373ATRGYRG4
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
70 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
8-Dec-2009
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV373ATDBR
SN74LV373ATDWR
SN74LV373ATNSR
SN74LV373ATPWR
SN74LV373ATPWT
SN74LV373ATRGYR
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
20
2000
2000
2000
2000
250
330.0
330.0
330.0
330.0
330.0
330.0
16.4
24.4
24.4
16.4
16.4
12.4
8.2
10.8
8.2
7.5
13.0
13.0
7.1
2.5
2.7
2.5
1.6
1.6
1.6
12.0
12.0
12.0
8.0
16.0
24.0
24.0
16.0
16.0
12.0
Q1
Q1
Q1
Q1
Q1
Q1
SO
TSSOP
TSSOP
VQFN
PW
PW
RGY
6.95
6.95
3.8
7.1
8.0
3000
4.8
8.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LV373ATDBR
SN74LV373ATDWR
SN74LV373ATNSR
SN74LV373ATPWR
SN74LV373ATPWT
SN74LV373ATRGYR
SSOP
SOIC
DB
DW
NS
20
20
20
20
20
20
2000
2000
2000
2000
250
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
45.0
45.0
38.0
38.0
35.0
SO
TSSOP
TSSOP
VQFN
PW
PW
RGY
3000
Pack Materials-Page 2
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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Audio
Applications
www.ti.com/audio
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dataconverter.ti.com
www.dlp.com
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Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
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microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
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