SN74LV374DWR [TI]
Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs 20-SOIC -40 to 85;
| 型号： | SN74LV374DWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Octal Edge-Triggered D-Type Flip-Flop With 3-State Outputs 20-SOIC -40 to 85 驱动 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总11页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54LV374, SN74LV374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS197B – FEBRUARY 1993 – REVISED APRIL 1996
SN54LV374 . . . J OR W PACKAGE
SN74LV374 . . . DB, DW, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) 2-µ Process
Typical V
< 0.8 V at V , T = 25°C
(Output Ground Bounce)
OLP
CC
A
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
8Q
8D
1
2
3
4
5
6
7
8
9
20
19
18
Typical V
> 2 V at V , T = 25°C
(Output V
Undershoot)
OHV
CC
OH
A
17 7D
16 7Q
15 6Q
14 6D
13 5D
12 5Q
11 CLK
ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model
(C = 200 pF, R = 0)
Latch-Up Performance Exceeds 250 mA
Per JEDEC Standard JESD-17
GND 10
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Shrink Small-Outline (PW),
Ceramic Flat (W) Packages, Chip Carriers
(FK), and (J) 300-mil DIPs
SN54LV374 . . . FK PACKAGE
(TOP VIEW)
description
3
2
1
20 19
18
8D
7D
7Q
2D
2Q
3Q
3D
4D
4
5
6
7
8
These octal edge-triggered D-type flip-flops are
designed for 2.7-V to 5.5-V V operation.
17
16
CC
15 6Q
14
9 10 11 12 13
The ’LV374 feature 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. These devices
are particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
6D
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data
(D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either as normal logic state (high
or low logic levels) or high-impedance state. In the high-impedance state, the outputs neither load nor drive the
buslinessignificantly. Thehigh-impedancestateandtheincreaseddriveprovidethecapabilitytodrivebuslines
without need for interface or pullup components.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN74LV374 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LV374 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74LV374 is characterized for operation from –40°C to 85°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1996, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV374, SN74LV374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS197B – FEBRUARY 1993 – REVISED APRIL 1996
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
L
X
X
X
Q
0
H
Z
†
logic symbol
logic diagram (positive logic)
1
1
OE
OE
EN
C1
11
11
CLK
CLK
C1
2
1Q
3
3
1D
4
2
5
1D
1D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
2D
7
6
3D
8
9
4D
13
12
15
16
19
5D
14
To Seven Other Channels
6D
17
7D
18
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
Pin numbers shown are for DB, DW, J, PW, and W packages.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 3): DB package . . . . . . . . . . . . . . . . . . . 0.6 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
A
DW package . . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . . . 0.7 W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV374, SN74LV374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS197B – FEBRUARY 1993 – REVISED APRIL 1996
recommended operating conditions (see Note 4)
SN54LV374
SN74LV374
UNIT
V
MIN
2.7
2
MAX
MIN
2.7
2
MAX
V
V
Supply voltage
5.5
5.5
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
High-level input voltage
V
IH
3.15
3.15
0.8
0.8
V
IL
Low-level input voltage
V
1.65
1.65
V
V
Input voltage
0
0
V
0
0
V
V
V
I
CC
CC
Output voltage
V
CC
–8
V
CC
–8
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
= 2.7 V to 3.6 V
= 4.5 V to 5.5 V
I
High-level output current
Low-level output current
mA
mA
OH
OL
–16
8
–16
8
I
16
16
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
100
125
0
100
85
ns/V
T
A
–55
–40
°C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV374
SN54LV374
†
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
–0.2
TYP
MAX
MIN
–0.2
TYP
MAX
I
I
I
I
I
I
= –100 µA
MIN to MAX
3 V
V
V
OH
OH
OH
OL
OL
OL
CC
2.4
3.6
CC
2.4
3.6
V
V
= – 8 mA
= – 16 mA
= 100 µA
= 8 mA
V
OH
4.5 V
MIN to MAX
3 V
0.2
0.4
0.55
±1
0.2
0.4
0.55
±1
V
OL
= 16 mA
4.5 V
3.6 V
I
I
I
V = V
or GND
µA
µA
I
I
CC
5.5 V
±1
±1
3.6 V
±5
±5
V
= V
or GND
OZ
CC
O
CC
5.5 V
±5
±5
3.6 V
20
20
V = V
or GND,
I
O
= 0
µA
µA
pF
I
CC
5.5 V
20
20
One input at V
CC
– 0.6 V,
or GND
I
i
3 V to 3.6 V
500
500
CC
Other inputs at V
CC
3.3 V
5 V
2.5
3
2.5
3
C
C
V = V
or GND
CC
I
3.3 V
5 V
7
7
V
= V or GND
CC
pF
o
O
8
8
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV374, SN74LV374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS197B – FEBRUARY 1993 – REVISED APRIL 1996
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN54LV374
V = 5 V
CC
± 0.5 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
45
40
35
MHz
ns
clock
Pulse duration, CLK high or low
Setup time before CLK↑
Hold time, data after CLK↑
9
10
10
2
13
11
2
w
High or low
7
ns
su
h
3
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
SN74LV374
V = 5 V
CC
± 0.5 V
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
45
40
35
MHz
ns
clock
Pulse duration, CLK high or low
Setup time before CLK↑
Hold time, data after CLK↑
9
10
10
2
13
11
2
w
High or low
7
ns
su
h
3
ns
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1))
SN54LV374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 5 V ± 0.5 V
V
CC
= 3.3 V ± 0.3 V
V
CC
= 2.7 V
MAX
UNIT
CC
MIN
TYP
80
MAX
MIN
TYP
70
MAX
MIN
f
t
45
40
35
MHz
ns
max
CLK
OE
11
19
20
21
15
24
24
24
29
28
29
Q
Q
Q
pd
t
t
10
8
13
12
ns
ns
en
OE
dis
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
SN74LV374
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
= 5 V ± 0.5 V
V
CC
= 3.3 V ± 0.3 V
V
CC
= 2.7 V
MAX
UNIT
CC
MIN
TYP
80
MAX
MIN
TYP
70
MAX
MIN
f
t
45
40
35
MHz
ns
max
CLK
OE
11
19
20
21
15
24
24
24
29
28
29
Q
Q
Q
pd
t
en
10
8
13
12
ns
ns
t
OE
dis
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV374, SN74LV374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS197B – FEBRUARY 1993 – REVISED APRIL 1996
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
V
TYP
52
UNIT
CC
Outputs enabled
Outputs disabled
Outputs enabled
Outputs disabled
3.3 V
5 V
34
C
Power dissipation capacitance per flip-flop
C
= 50 pF,
L
f = 10 MHz
pF
pd
60
35
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54LV374, SN74LV374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS197B – FEBRUARY 1993 – REVISED APRIL 1996
PARAMETER MEASUREMENT INFORMATION
V
z
TEST
S1
S1
Open
1 kΩ
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
t
V
z
GND
GND
PLZ PZL
/t
PHZ PZH
C
= 50 pF
L
1 kΩ
(see Note A)
WAVEFORM
CONDITION
V
= 4.5 V
V
= 2.7 V
CC
to 5.5 V
CC
to 3.6 V
1.5 V
2.7 V
6 V
V
m
0.5 × V
CC
V
i
V
z
V
CC
LOAD CIRCUIT
2 × V
CC
V
i
V
m
Timing Input
0 V
t
w
t
t
su
h
V
i
V
i
V
m
V
m
Input
V
m
V
m
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
i
i
Output
Control
V
V
m
m
Input
V
m
V
m
0 V
0 V
V
t
PZL
t
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
0.5 × V
z
OH
V
V
V
m
V
m
m
Output
Output
V
+ 0.3 V
– 0.3 V
S1 at V
(see Note B)
OL
z
V
OL
V
OL
t
PHZ
t
PLH
t
PZH
PHL
Output
Waveform 2
S1 at GND
V
V
V
OH
OH
V
OH
V
V
m
m
m
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
SSOP
SOIC
SOIC
Drawing
SN74LV374DBLE
SN74LV374DW
OBSOLETE
OBSOLETE
OBSOLETE
DB
20
20
20
20
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
DW
SN74LV374DWR
SN74LV374PWLE
DW
OBSOLETE TSSOP
PW
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74LV393ADBE4
LV/LV-A/LVX/H SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, GREEN, PLASTIC, SSOP-14
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