SN74LV393ADGVRG4 [TI]
DUAL 4-BIT BINARY COUNTERS; 双4位二进制计数器
| 型号： | SN74LV393ADGVRG4 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | DUAL 4-BIT BINARY COUNTERS |
| 文件： | 总18页 (文件大小：525K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁꢊ ꢃꢄꢅ ꢆꢇ ꢆꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢏ ꢐ ꢎꢏ ꢁꢈꢑꢒ ꢓ ꢔꢌ ꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
SN54LV393A . . . J OR W PACKAGE
SN74LV393A . . . D, DB, DGV, NS, OR PW PACKAGE
(TOP VIEW)
D
D
D
D
D
D
2-V to 5.5-V V
Operation
CC
Max t of 10 ns at 5 V
pd
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
1CLK
1CLR
V
CC
2CLK
2CLR
1
2
3
4
5
6
7
14
13
12
11
A
Typical V
>2.3 V at V
(Output V
Undershoot)
OHV
CC
OH
1Q
A
= 3.3 V, T = 25°C
A
1Q
B
2Q
A
I
Supports Partial-Power-Down-Mode
off
1Q
1Q
10 2Q
C
B
C
D
Operation
9
8
2Q
2Q
D
Dual 4-Bit Binary Counters With Individual
Clocks
GND
D
Direct Clear for Each 4-Bit Counter
D
Can Significantly Improve System
Densities by Reducing Counter Package
Count by 50 Percent
SN54LV393A . . . FK PACKAGE
(TOP VIEW)
D
D
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
3
2
1 20 19
18
2CLR
NC
1Q
4
5
6
7
8
A
NC
17
16
2Q
A
1Q
B
− 1000-V Charged-Device Model (C101)
15 NC
14
9 10 11 12 13
NC
2Q
1Q
description/ordering information
B
C
The ’LV393A devices contain eight flip-flops and
additional gating to implement two individual 4-bit
counters in a single package. These devices are
NC − No internal connection
designed for 2-V to 5.5-V V
operation.
CC
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
Tube of 50
SN74LV393AD
SOIC − D
LV393A
Reel of 2500
Reel of 2000
Reel of 2000
Tube of 90
SN74LV393ADR
SN74LV393ANSR
SN74LV393ADBR
SN74LV393APW
SN74LV393APWR
SN74LV393APWT
SN74LV393ADGVR
SNJ54LV393AJ
SOP − NS
74LV393A
LV393A
SSOP − DB
−40°C to 85°C
Reel of 2000
Reel of 250
Reel of 2000
Tube of 25
TSSOP − PW
LV393A
TVSOP − DGV
CDIP − J
LV393A
SNJ54LV393AJ
SNJ54LV393AW
SNJ54LV393AFK
−55°C to 125°C
CFP − W
Tube of 150
Tube of 55
SNJ54LV393AW
SNJ54LV393AFK
LCCC − FK
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2005, Texas Instruments Incorporated
ꢌ ꢁ ꢄꢕꢀꢀ ꢔ ꢐꢖ ꢕꢑꢗ ꢏꢀ ꢕ ꢁ ꢔꢐꢕꢋ ꢘꢙ ꢚꢛ ꢜꢝꢞ ꢟꢠꢡ ꢢꢘ ꢞꢝ ꢢꢘꢣ ꢚꢢꢛ ꢤꢑ ꢔ ꢋ ꢌ ꢓꢐ ꢏꢔ ꢁ
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢋ ꢌꢈꢄ ꢃ ꢍꢎ ꢏ ꢐ ꢎ ꢏ ꢁ ꢈꢑꢒ ꢓꢔ ꢌꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
description/ordering informaton (continued)
These devices comprise two independent 4-bit binary counters, each having a clear (CLR) and a clock (CLK)
input. These devices change state on the negative-going transition of the CLK pulse. N-bit binary counters can
be implemented with each package, providing the capability of divide by 256. The ’LV393A devices have parallel
outputs from each counter stage so that any submultiple of the input count frequency is available for system
timing signals.
These devices are fully specified for partial-power-down applications using I . The I circuitry disables the
off
off
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
FUNCTION
CLK
↑
CLR
L
No change
Advance to next stage
All outputs L
↓
L
X
H
logic diagram, each counter (positive logic)
R
CLR
CLK
Q
Q
A
T
R
Q
Q
Q
Q
B
C
D
T
R
Q
T
R
Q
T
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢏ ꢐ ꢎꢏ ꢁꢈꢑꢒ ꢓ ꢔꢌ ꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
timing diagram
CLK
CLR
Q
Q
A
B
Outputs
Q
Q
C
D
Count Up
Clear
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
Output voltage range applied in high or low state, V (see Notes 1 and 2) . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Output voltage range applied in power-off state, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
Continuous current through V
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W
JA
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127°C/W
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. This value is limited to 7 V maximum.
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢋ ꢌꢈꢄ ꢃ ꢍꢎ ꢏ ꢐ ꢎ ꢏ ꢁ ꢈꢑꢒ ꢓꢔ ꢌꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
recommended operating conditions (see Note 4)
SN54LV393A
MIN MAX
SN74LV393A
MIN MAX
UNIT
V
V
Supply voltage
2
5.5
2
5.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
1.5
1.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
V
V
V
× 0.7
V
V
V
× 0.7
CC
CC
CC
CC
CC
CC
High-level input voltage
V
V
IH
× 0.7
× 0.7
× 0.7
× 0.7
0.5
0.5
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
V
V
V
× 0.3
V
V
V
× 0.3
CC
CC
CC
CC
CC
CC
V
IL
Low-level input voltage
× 0.3
× 0.3
× 0.3
× 0.3
V
V
Input voltage
0
0
5.5
0
0
5.5
V
V
I
Output voltage
V
V
CC
O
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
−50
−2
−50
−2
−6
−12
50
2
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2 V
I
High-level output current
Low-level output current
OH
OL
−6
mA
−12
50
µA
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
= 4.5 V to 5.5 V
2
I
6
6
mA
12
12
200
100
20
85
200
100
20
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−55
125
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54LV393A
SN74LV393A
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
TYP
MAX
MIN
TYP
MAX
I
I
I
I
I
I
I
I
= −50 µA
2 V to 5.5 V
2.3 V
V
−0.1
2
V
CC
−0.1
2
OH
OH
OH
OH
OL
OL
OL
OL
CC
= −2 mA
= −6 mA
= −12 mA
= 50 µA
= 2 mA
V
V
V
OH
3 V
2.48
3.8
2.48
3.8
4.5 V
2 V to 5.5 V
2.3 V
0.1
0.4
0.44
0.55
1
0.1
0.4
0.44
0.55
1
V
OL
= 6 mA
3 V
= 12 mA
4.5 V
I
I
I
V = 5.5 V or GND
0 to 5.5 V
5.5 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
20
20
CC
off
I
V or V = 0 to 5.5 V
0
5
5
I
O
C
V = V
or GND
3.3 V
1.8
1.8
i
I
CC
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ꢜ ꢡ ꢛ ꢚ ꢮ ꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢯ ꢡ ꢩ ꢝꢧ ꢠꢡ ꢢ ꢘꢪ ꢓ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
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4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢏ ꢐ ꢎꢏ ꢁꢈꢑꢒ ꢓ ꢔꢌ ꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 2.5 V 0.2 V
CC
T
= 25°C
SN54LV393A SN74LV393A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
CLR inactive before CLK↓
6
6
6
su
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 3.3 V 0.3 V
CC
T
= 25°C
SN54LV393A SN74LV393A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
CLR inactive before CLK↓
5
5
5
su
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V 0.5 V
CC
T
= 25°C
SN54LV393A SN74LV393A
A
UNIT
MIN
5
MAX
MIN
5
MAX
MIN
5
MAX
CLK high or low
CLR high
t
t
Pulse duration
Setup time
ns
ns
w
5
5
5
CLR inactive before CLK↓
4
4
4
su
switching characteristics over recommended operating free-air temperature range,
V
= 2.5 V 0.2 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
90*
SN54LV393A SN74LV393A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
50*
30
MAX
MIN
40*
25
MAX
MIN
40
25
1
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
70
7.1* 17.7*
8.5* 20.3*
10* 22.5*
11.1* 24.2*
6.7* 14.8*
1* 20.5*
1* 23.5*
20.5
23.5
26
Q
A
Q
B
Q
C
Q
D
1
1
1
1
1
1
1
1
1
t
t
CLK
CLR
pd
1*
1*
1*
1
26*
28*
17*
24.5
27.5
30
C
C
= 15 pF
ns
ns
L
L
28
17
Q
PHL
n
A
B
C
D
9.3
10.9
12.3
13.4
9.1
21.3
23.9
26.1
27.8
17.4
24.5
27.5
30
Q
Q
Q
Q
1
t
t
CLK
CLR
pd
= 50 pF
1
1
32
32
1
20
20
Q
PHL
n
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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ꢜꢡ ꢛ ꢚ ꢮꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢯ ꢡ ꢩꢝ ꢧꢠꢡ ꢢꢘꢪ ꢓ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
ꢞ
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ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢯ
ꢡ
ꢝ
ꢦ
ꢛ
ꢧ
ꢡ
ꢞ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢛ
ꢣ
ꢦ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢮ
ꢢ
ꢮ
ꢝ
ꢣ
ꢩ
ꢛ
ꢪ
ꢐ
ꢡ
ꢫ
ꢣ
ꢛ
ꢏ
ꢢ
ꢛ
ꢘ
ꢦ
ꢟ
ꢠ
ꢡ
ꢢ
ꢞ ꢙꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝꢜ ꢟꢞꢘ ꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢯ
ꢡꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢋ ꢌꢈꢄ ꢃ ꢍꢎ ꢏ ꢐ ꢎ ꢏ ꢁ ꢈꢑꢒ ꢓꢔ ꢌꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
switching characteristics over recommended operation free-air temperature range,
V
= 3.3 V 0.3 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
SN54LV393A SN74LV393A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
75*
45
MAX
MIN
65*
35
MAX
MIN
65
35
1
MAX
C
C
= 15 pF
= 50 pF
130*
105
L
L
f
MHz
max
5.1* 13.2*
6* 15.8*
1* 15.5*
1* 18.5*
15.5
18.5
21
Q
A
Q
B
Q
C
Q
D
1
1
1
1
1
1
1
1
1
t
t
CLK
CLR
pd
7*
18*
1*
1*
21*
23*
C
C
= 15 pF
ns
ns
L
L
7.7* 19.7*
5.1* 12.3*
23
1* 14.5*
14.5
19
Q
PHL
n
A
B
C
D
6.7
7.8
8.7
9.5
6.8
16.7
19.3
21.5
23.2
15.8
1
1
1
1
1
19
22
Q
Q
Q
Q
22
t
t
CLK
CLR
pd
= 50 pF
24.5
26.5
18
24.5
26.5
18
Q
PHL
n
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
switching characteristics over recommended operating free-air temperature range,
V
= 5 V 0.5 V (unless otherwise noted) (see Figure 1)
CC
T
A
= 25°C
TYP
185*
150
SN54LV393A SN74LV393A
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
MIN
125*
85
MAX
MIN
105*
75
MAX
MIN
105
75
MAX
C
C
= 15 pF
= 50 pF
L
L
f
MHz
max
3.7*
8.5*
9.8*
1*
10*
1
10
11.5
13
Q
Q
Q
Q
A
B
C
D
4.3*
1* 11.5*
1* 13*
1* 14.5*
1
1
1
1
1
1
1
1
1
t
t
CLK
CLR
pd
4.9* 11.2*
5.3* 12.5*
C
C
= 15 pF
ns
ns
L
L
14.5
9.5
3.9*
4.9
5.6
6.2
6.6
5.2
8.1*
10.5
11.8
13.2
14.5
10.1
1*
1
9.5*
12
Q
PHL
n
A
B
C
D
12
Q
Q
Q
Q
1
13.5
15
13.5
15
t
t
CLK
CLR
pd
= 50 pF
1
1
16.5
11.5
16.5
11.5
1
Q
PHL
n
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
ꢤ
ꢑ
ꢔ
ꢋ
ꢌ
ꢓ
ꢐ
ꢤ
ꢑ
ꢕ
ꢅ
ꢏ
ꢕ
ꢗ
ꢚ
ꢢ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢞ
ꢝ
ꢢ
ꢞ
ꢡ
ꢦ
ꢢ
ꢛ
ꢧ
ꢦ
ꢝ
ꢜ
ꢟ
ꢜ ꢡ ꢛ ꢚ ꢮ ꢢ ꢧꢙ ꢣ ꢛ ꢡ ꢝꢥ ꢜꢡ ꢯ ꢡ ꢩ ꢝꢧ ꢠꢡ ꢢ ꢘꢪ ꢓ ꢙꢣ ꢦꢣ ꢞꢘ ꢡꢦ ꢚꢛ ꢘꢚ ꢞ ꢜꢣ ꢘꢣ ꢣꢢ ꢜ ꢝꢘ ꢙꢡꢦ
ꢞ
ꢘ
ꢛ
ꢚ
ꢢ
ꢘ
ꢙ
ꢡ
ꢥ
ꢝ
ꢦ
ꢠ
ꢣ
ꢘ
ꢚ
ꢯ
ꢡ
ꢝ
ꢦ
ꢛ
ꢧ
ꢡ
ꢞ
ꢚ
ꢥ
ꢚ
ꢞ
ꢣ
ꢘ
ꢚ
ꢝ
ꢢ
ꢛ
ꢣ
ꢦ
ꢡ
ꢜ
ꢡ
ꢛ
ꢚ
ꢮ
ꢢ
ꢮ
ꢝ
ꢣ
ꢩ
ꢛ
ꢪ
ꢐ
ꢡ
ꢫ
ꢣ
ꢛ
ꢏ
ꢢ
ꢛ
ꢘ
ꢦ
ꢟ
ꢠ
ꢡ
ꢢ
ꢞ ꢙ ꢣ ꢢ ꢮꢡ ꢝꢦ ꢜꢚ ꢛ ꢞ ꢝꢢ ꢘꢚ ꢢꢟ ꢡ ꢘ ꢙꢡ ꢛ ꢡ ꢧꢦ ꢝ ꢜꢟꢞ ꢘꢛ ꢬ ꢚꢘꢙ ꢝꢟꢘ ꢢꢝꢘ ꢚꢞꢡ ꢪ
ꢘ
ꢛ
ꢦ
ꢡ
ꢛ
ꢡ
ꢦ
ꢯ
ꢡꢛ
ꢘ
ꢙ
ꢡ
ꢦ
ꢚ
ꢮ
ꢙ
ꢘ
ꢘ
ꢝ
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀꢁ ꢂꢃ ꢄꢅꢆ ꢇ ꢆ ꢈꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆꢇ ꢆꢈ
ꢋꢌꢈ ꢄ ꢃ ꢍꢎꢏ ꢐ ꢎꢏ ꢁꢈꢑꢒ ꢓ ꢔꢌ ꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
noise characteristics, V
= 3.3 V, C = 50 pF, T = 25°C (see Note 5)
CC
L
A
SN74LV393A
UNIT
PARAMETER
MIN
TYP
0.3
MAX
0.8
V
V
V
V
V
Quiet output, maximum dynamic V
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
−0.2
2.8
−0.8
OL
OH
2.31
0.99
NOTE 5: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
V
TYP
15.2
17.3
UNIT
CC
3.3 V
C
Power dissipation capacitance
C
pF
pd
5 V
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢆꢈ ꢉ ꢀꢁ ꢊꢃ ꢄꢅ ꢆ ꢇꢆ ꢈ
ꢋ ꢌꢈꢄ ꢃ ꢍꢎ ꢏ ꢐ ꢎ ꢏ ꢁ ꢈꢑꢒ ꢓꢔ ꢌꢁ ꢐꢕ ꢑꢀ
SCLS457D − FEBRUARY 2001 − REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
V
CC
50% V
CC
Timing Input
0 V
t
w
t
h
t
V
CC
su
V
CC
50% V
CC
50% V
CC
Input
Input
50% V
CC
50% V
CC
Data Input
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
CC
CC
Output
Control
50% V
CC
50% V
50% V
CC
50% V
CC
CC
0 V
0 V
t
t
PLZ
PZL
t
t
t
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
OL
+ 0.3 V
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC
50% V
50% V
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
PACKAGING INFORMATION
Orderable Device
SN74LV393AD
Status (1)
ACTIVE
PREVIEW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
14
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV393ADB
SSOP
SSOP
SSOP
SSOP
SOIC
DB
DB
DB
DB
D
80 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV393ADBR
SN74LV393ADBRE4
SN74LV393ADBRG4
SN74LV393ADE4
SN74LV393ADG4
SN74LV393ADGVR
SN74LV393ADGVRE4
SN74LV393ADGVRG4
SN74LV393ADR
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TVSOP
TVSOP
TVSOP
SOIC
DGV
DGV
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV393ADRE4
SN74LV393ADRG4
SN74LV393ANSR
SN74LV393ANSRE4
SN74LV393ANSRG4
SN74LV393APW
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOIC
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
NS
NS
NS
PW
PW
PW
PW
PW
PW
PW
PW
PW
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV393APWE4
SN74LV393APWG4
SN74LV393APWR
SN74LV393APWRE4
SN74LV393APWRG4
SN74LV393APWT
SN74LV393APWTE4
SN74LV393APWTG4
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
4-Jun-2007
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
TAPE AND REEL BOX INFORMATION
Device
Package Pins
Site
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) (mm) Quadrant
(mm)
330
330
330
330
330
(mm)
16
SN74LV393ADBR
SN74LV393ADGVR
SN74LV393ADR
DB
DGV
D
14
14
14
14
14
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
8.2
6.8
6.5
8.2
7.0
6.6
4.0
2.5
1.6
2.1
2.5
1.6
12
8
16
16
16
16
12
Q1
Q1
Q1
Q1
Q1
12
16
9.0
8
SN74LV393ANSR
SN74LV393APWR
NS
16
10.5
5.6
12
8
PW
12
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
4-Oct-2007
Device
Package
Pins
Site
Length (mm) Width (mm) Height (mm)
SN74LV393ADBR
SN74LV393ADGVR
SN74LV393ADR
DB
DGV
D
14
14
14
14
14
SITE 41
SITE 41
SITE 41
SITE 41
SITE 41
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
346.0
33.0
29.0
33.0
33.0
29.0
SN74LV393ANSR
SN74LV393APWR
NS
PW
Pack Materials-Page 2
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001
DB (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
28 PINS SHOWN
0,38
0,22
0,65
28
M
0,15
15
0,25
0,09
5,60
5,00
8,20
7,40
Gage Plane
1
14
0,25
A
0°–ā8°
0,95
0,55
Seating Plane
0,10
2,00 MAX
0,05 MIN
PINS **
14
16
20
24
28
30
38
DIM
6,50
5,90
6,50
5,90
7,50
8,50
7,90
10,50
9,90
10,50 12,90
A MAX
A MIN
6,90
9,90
12,30
4040065 /E 12/01
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-150
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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