SN74LV4040ADR [TI]
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO; 高速CMOS逻辑锁相环与VCO
| 型号： | SN74LV4040ADR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP WITH VCO |
| 文件： | 总12页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
www.ti.com
SCES656A–FEBRUARY 2006–REVISED FEBRUARY 2006
FEATURES
•
Choice of Three Phase Comparators
– Exclusive OR
D, DGV, NS, OR PW PACKAGE
(TOP VIEW)
– Edge-Triggered J-K Flip-Flop
– Edge-Triggered RS Flip-Flop
Excellent VCO Frequency Linearity
V
PCP
PC1
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CC
OUT
PC3
SIG
OUT
OUT
OUT
•
•
COMP
VCO
IN
IN
VCO-Inhibit Control for ON/OFF Keying and
for Low Standby Power Consumption
PC2
OUT
R
INH
2
R
•
•
•
•
Optimized Power-Supply Voltage Range From
3 V to 5.5 V
C1
1
A
DEM
VCO
C1
OUT
B
GND
Wide Operating Temperature Range . . . –40°C
to 125°C
IN
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION
The SN74LV4046A is a high-speed silicon-gate CMOS device that is pin compatible with the CD4046B and the
CD74HC4046. The device is specified in compliance with JEDEC Std 7.
The SN74LV4046A is a phase-locked-loop circuit that contains a linear voltage-controlled oscillator (VCO) and
three different phase comparators (PC1, PC2, and PC3). A signal input and a comparator input are common to
each comparator.
The signal input can be directly coupled to large voltage signals, or indirectly coupled (with a series capacitor) to
small voltage signals. A self-bias input circuit keeps small voltage signals within the linear region of the input
amplifiers. With a passive low-pass filter, the SN74LV4046A forms a second-order loop PLL. The excellent VCO
linearity is achieved by the use of linear operational amplifier techniques.
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE PART NUMBER
SN74LV4040ANS
TOP-SIDE MARKING
74LV4046A
SOP – NS
SOIC – D
SN74LV4040ANSR
SN74LV4040AD
LV4046A
–40°C to 125°C
SN74LV4040ADR
SN74LV4040APW
SN74LV4040APWR
SN74LV4040ADGVR
TSSOP – PW
TVSOP – DGV
LW046A
LW046A
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
www.ti.com
SCES656A–FEBRUARY 2006–REVISED FEBRUARY 2006
PIN DESCRIPTION
PIN NO.
SYMBOL
PCPOUT
PC1OUT
COMPIN
VCOOUT
INH
NAME AND FUNCTION
Phase comparator pulse output
Phase comparator 1 output
Comparator input
1
2
3
4
VCO output
5
Inhibit input
6
C1A
Capacitor C1 connection A
Capacitor C1 connection B
Ground (0 V)
7
C1B
8
GND
9
VCOIN
DEMOUT
R1
VCO input
10
11
12
13
14
15
16
Demodulator output
Resistor R1 connection
Resistor R2 connection
Phase comparator 2 output
Signal input
R2
PC2OUT
SIGIN
PC3OUT
VCC
Phase comparator 3 output
Positive supply voltage
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
DC supply voltage range
Input voltage range
7
VCC + 0.5
VCC + 0.5
–20
V
VO
IIK
Output voltage range
Input clamp current
V
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
Continuous output curent
DC VCC or ground current
VO < 0
–50
VO = 0 to VCC
±35
ICC
±70
D package
73
DGV package
NS package
PW package
120
θJA
Package thermal impedance(2)
°C/W
°C
64
108
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions
PARAMETER
MIN
–40
3
MAX UNIT
TA
Operating free-air temperature
Supply voltage
125
5.5
°C
V
VCC
VI, VO
DC input or output voltage
0
VCC
V
2
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SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
www.ti.com
SCES656A–FEBRUARY 2006–REVISED FEBRUARY 2006
Electrical Specifications
TEST CONDITIONS
PARAMETER
VCC (V)
MIN TYP
MAX UNIT
VI (V)
IO (mA)
VCO
3 to 3.6
4.5 to 5.5
3 to 5.5
V
CC × 0.7
CC × 0.7
VIH
VIL
High-level input voltage INH
Low-level input voltage INH
V
V
V
CC × 0.3
V
V
4.5 to 5.5
3 to 3.6
VCC × 0.3
VCC – 0.1
VCC – 0.1
3.8
CMOS
TTL
–0.05
–12
High-level
output voltage
VOH
VCOOUT
VIL or VIH
4.5 to 5.5
4.5 to 5.5
3 to 3.6
0.1
0.1
CMOS
TTL
0.05
VCOOUT
4.5 to 5.5
4.5 to 5.5
Low-level
VOL
VIL or VIH
V
12
12
0.55
output voltage
C1A, C1B
(test purposes only)
4.5 to 5.5
0.65
II
Input leakage current
R1 range(1)
R2 range(1)
INH, VCOIN
VCC or GND
5.5
±1
50
50
µA
kΩ
kΩ
3 to 5.5
3 to 4.5
3 to 3.6
4.5 to 5.5
3 to 3.6
4.5 to 5.5
3
3
40
40
1.1
1.1
C1 capacitance range
No Limit
pF
V
1.9
3.2
Operating voltage
range
Over the range specified
for R1 for linearity(2)
VCOIN
Phase Comparator
3 to 3.6
4.5 to 5.5
3 to 3.6
V
CC × 0.7
CC × 0.7
DC-coupled high-level
input voltage
SIGIN
COMPIN
,
VIH
VIL
V
V
CC × 0.3
SIGIN
,
DC-coupled low-level input voltage
V
V
COMPIN
4.5 to 5.5
3 to 5.5
VCC × 0.3
–0.05
VCC – 0.1
2.48
CMOS
TTL
High-level
output voltage
PCPOUT
PCNOUT
,
VOH
VIL or VIH
–6
3 to 3.6
–12
4.5 to 5.5
3 to 3.6
3.8
0.1
0.1
0.02
4
CMOS
Low-level
output voltage
PCPOUT
PCNOUT
,
4.5 to 5.5
VOL
VIL or VIH
V
4.5 to 5.5
0.4
TTL
3 to 3.6
4.5 to 5.5
3 to 5.5
3
±11
±29
±5
SIGIN
COMPIN
,
II
Input leakage current
3-state off-state current
Input resistance
VCC or GND
VIL or VIH
µA
µA
kΩ
IOZ
RI
PC2OUT
800
250
SIGIN
,
VI at self-bias operating
point, VI = 0.5 V
COMPIN
4.5
Demodulator
RS > 300 kΩ, Leakage
current can influence
VDEMOUT
3 to 3.6
4.5 to 5.5
3 to 3.6
50
50
300
300
RS
Resistor range
kΩ
mV
µA
VI = VVCOIN = VCC/2
,
±30
±20
VOFF
Offset voltage VCOIN to VDEM
Values taken over RS
range
4.5 to 5.5
Pins 3, 5, and 14 at VCC
Pin 9 at GND, II at pins 3
and 14 to be excluded
,
ICC
Quiescent device current
5.5
50
(1) The value for R1 and R2 in parallel should exceed 2.7 kΩ.
(2) The maximum operating voltage can be as high as VCC – 0.9 V; however, this may result in an increased offset voltage.
3
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SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
www.ti.com
SCES656A–FEBRUARY 2006–REVISED FEBRUARY 2006
Switching Specifications
CL = 50 pF, Input tr, tf = 6 ns
VCC
(V)
PARAMETER
TEST CONDITIONS
MIN TYP
MAX UNIT
Phase Comparator
3 to 3.6
4.5 to 5.5
3 to 3.6
135
ns
SIGIN, COMPIN to
PC1OUT
tPLH, tPHL
tPLH, tPHL
tPLH, tPHL
tTHL, tTLH
tPZH, tPZL
tPHZ, tPLZ
Propagation delay
50
300
ns
SIGIN, COMPIN to
PCPOUT
Propagation delay
4.5 to 5.5
3 to 3.6
60
200
ns
SIGIN, COMPIN to
PC3OUT
Propagation delay
4.5 to 5.5
3 to 3.6
50
75
ns
15
Output transition time
4.5 to 5.5
3 to 3.6
270
ns
SIGIN, COMPIN to
PC2OUT
3-state output enable time
3-state output disable time
AC-coupled input sensitivity
4.5 to 5.5
3 to 3.6
54
320
ns
SIGIN, COMPIN to
PC2OUT
4.5 to 5.5
3 to 3.6
65
11
15
(P-P) at SIGIN or
COMPIN
VI(P-P)
mV
4.5 to 5.5
VCO
VI = VCOIN = 1/2 VCC
R1 = 100 kΩ,
R2 = ∞,
,
3 to 3.6
0.11
0.11
∆f/∆T
Frequency stability with temperature change
Maximum frequency
%/°C
4.5 to 5.5
C1 = 100 pF
C1 = 50 pF,
R1 = 3.5 kΩ,
R2 = ∞
3 to 3.6
4.5 to 5.5
3 to 3.6
24
24
38
38
fMAX
MHz
MHz
C1 = 0 pF,
R1 = 9.1 kΩ,
R2 = ∞
4.5 to 5.5
3 to 3.6
C1 = 40 pF,
R1 = 3 kΩ,
R2 = ∞,
7
10
17
Center frequency (duty 50%)
4.5 to 5.5
12
VCOIN = VCC/2
C1 = 100 pF,
R1 = 100 kΩ,
R2 = ∞
3 to 3.6
0.4
0.4
∆fVCO
Frequency linearity
Offset frequency
%
4.5 to 5.5
3 to 3.6
400
400
C1 = 1 nF,
R2 = 220 kΩ
kHz
4.5 to 5.5
Demodulator
C1 = 100 pF,
C2 = 100 pF,
R1 = 100 kΩ,
R2 = ∞,
3
8
VOUT vs fIN
mV/kHz
4.5
330
R3 = 100 kΩ
4
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SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
www.ti.com
SCES656A–FEBRUARY 2006–REVISED FEBRUARY 2006
APPLICATION INFORMATION
AVERAGE OUTPUT VOLTAGE
vs
INPUT PHASE DIFFERENCE
AVERAGE OUTPUT VOLTAGE
vs
INPUT PHASE DIFFERENCE
V
CC
V
CC
V
V
DEMOUT (AV)
DEMOUT (AV)
1/2 V
CC
1/2 V
CC
0
0
φ
–3605
05
DEMOUT
3605
φ
05
905
1805
DEMOUT
Figure 1. Phase Comparator 1:
Figure 2. Phase Comparator 2:
VDEMOUT = VPC1OUT = (VCC/π) (SIGIN – COMPIN);
DEMOUT = (SIGIN – COMPIN
VDEMOUT = VPC2OUT = (VCC/4) (SIGIN – COMPIN);
)
DEMOUT = (SIGIN – COMPIN)
SIG
SIG
IN
IN
COMP
IN
VCO
OUT
COMP
IN
V
CC
GND
VCO
OUT
PC2
OUT
PC1
High-Impedance Off State
OUT
VCO
IN
V
CC
VCO
IN
GND
PCP
OUT
Figure 3. Typical Waveforms for PLL Using
Phase Comparator 1, Loop Locked at fo
Figure 4. Typical Waveforms for PLL Using
Phase Comparator 2, Loop Locked at fo
AVERAGE OUTPUT VOLTAGE
vs
INPUT PHASE DIFFERENCE
V
CC
SIG
IN
V
COMP
DEMOUT(AV)
IN
VCO
OUT
1/2 V
CC
PC3
OUT
V
CC
VCO
IN
GND
0
f
05
1805
DEMOUT
3605
Figure 5. Phase Comparator 3:
VDEMOUT = VPC3OUT = (VCC/2π) (SIGIN – COMPIN);
DEMOUT = (SIGIN – COMPIN
Figure 6. Typical Waveforms for PLL Using
Phase Comparator 3, Loop Locked at fo
)
5
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SN74LV4046A
HIGH-SPEED CMOS LOGIC PHASE-LOCKED LOOP
WITH VCO
www.ti.com
SCES656A–FEBRUARY 2006–REVISED FEBRUARY 2006
APPLICATION INFORMATION (continued)
SIG
IN
SIG , COMP
V
S
IN
IN
V
S
Inputs
Inputs
t
t
PLH
PHL
COMP
IN
V
PHZ
Inputs
S
PCP
, PC1
OUT,
OUT
t
V
S
PC3
OUT
t
PLZ
t
PZL
t
Outputs
PZH
90%
PC2
OUT
t
t
TLH
THL
V
S
Output
10%
Figure 7. Input-to-Output Propagation Delays and
Output Transition Times
Figure 8. 3-State Enable and Disable Times for PC2OUT
(1)
CPD
CHIP SECTION
Comparator 1
VCO
CPD
UNIT
120
120
pF
(1) R1 between 3 kΩ and 50 kΩ
R2 between 3 kΩ and 50 kΩ
R1 + R2 parallel value > 2.7 kΩ
C1 > 40 pF
6
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PACKAGE OPTION ADDENDUM
www.ti.com
13-Feb-2006
PACKAGING INFORMATION
Orderable Device
SN74LV4046AD
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
D
16
16
16
16
16
16
16
40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LV4046ADGVR
SN74LV4046ADR
SN74LV4046ANS
SN74LV4046ANSR
SN74LV4046APW
SN74LV4046APWR
TVSOP
SOIC
SO
DGV
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
NS
NS
PW
PW
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SO
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
TSSOP
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS006C – FEBRUARY 1996 – REVISED AUGUST 2000
DGV (R-PDSO-G**)
PLASTIC SMALL-OUTLINE
24 PINS SHOWN
0,23
0,13
M
0,07
0,40
24
13
0,16 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
0°–ā8°
0,75
1
12
0,50
A
Seating Plane
0,08
0,15
0,05
1,20 MAX
PINS **
14
16
20
24
38
48
56
DIM
A MAX
A MIN
3,70
3,50
3,70
3,50
5,10
4,90
5,10
4,90
7,90
7,70
9,80
9,60
11,40
11,20
4073251/E 08/00
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side.
D. Falls within JEDEC: 24/48 Pins – MO-153
14/16/20/56 Pins – MO-194
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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