SN74LV4T125QPWRQ1 [TI]
具有三态输出电平转换器的汽车类单电源四路缓冲门 | PW | 14 | -40 to 125;
| 型号： | SN74LV4T125QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有三态输出电平转换器的汽车类单电源四路缓冲门 | PW | 14 | -40 to 125 转换器 电平转换器 |
| 文件： | 总24页 (文件大小：1342K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LV4T125-Q1
ZHCSOT8A –MARCH 2022 –REVISED JUNE 2022
具有三态输出的SN74LV4T125-Q1 汽车类四路缓冲器转换器
1 特性
3 说明
• 符合面向汽车应用的AEC-Q100 标准：
SN74LV4T125-Q1 包含四个具有三态输出的独立缓冲
器且支持扩展电压运行，可实现电平转换。每个缓冲器
以正逻辑执行布尔函数 Y = A。通过对 OE 引脚施加高
电平，可以将输出置于高阻态 (Hi-Z)。输出电平以电源
电压 (VCC) 为基准，并且支持 1.8V、2.5V、3.3V 和
5V CMOS 电平。
– 器件温度等级1：-40°C 至+125°C
– 器件HBM ESD 分类等级2
– 器件CDM ESD 分类等级C4B
• 1.8V 至5.5V 的宽工作电压范围
• 单电源电压转换器（参阅LVxT 增强输入电压）：
该输入经设计，具有较低阈值电路，支持较低电压
CMOS 输入的上行转换（例如 1.2V 输入转换为 1.8V
输出或 1.8V 输入转换为 3.3V 输出）。此外，5V 容限
输入引脚可实现下行转换（例如 3.3V 至 2.5V 输
出）。
– 上行转换：
• 1.2 V 至1.8 V
• 1.5 V 至2.5 V
• 1.8V 至3.3V
• 3.3 V 至5.0 V
– 下行转换：
器件信息(1)
器件型号
封装
封装尺寸（标称值）
• 5.0V、3.3V、2.5V 至1.8V
• 5.0V、3.3V 至2.5V
• 5.0 V 至3.3 V
SN74LV4T125-Q1
TSSOP (14)
5.00mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附
录。
• 5.5V 容限输入引脚
• 支持标准引脚排列
• 速率高达150 Mbps，具有5V 或3.3V VCC
• 闩锁性能超过250 mA，符合JESD 17 规范
2 应用
• 启用或禁用数字信号
• 控制指示灯LED
• 通信模块和系统控制器之间的转换
xOE
xA
xY
简化逻辑图（正逻辑）
本文档旨在为方便起见，提供有关TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问
www.ti.com，其内容始终优先。TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。
English Data Sheet: SCLS874
SN74LV4T125-Q1
ZHCSOT8A –MARCH 2022 –REVISED JUNE 2022
www.ti.com.cn
Table of Contents
8.2 Functional Block Diagram......................................... 11
8.3 Feature Description...................................................11
8.4 Device Functional Modes..........................................13
9 Application and Implementation..................................14
9.1 Application Information............................................. 14
9.2 Typical Application.................................................... 14
10 Power Supply Recommendations..............................16
11 Layout...........................................................................16
11.1 Layout Guidelines................................................... 16
11.2 Layout Example...................................................... 16
12 Device and Documentation Support..........................17
12.1 Documentation Support.......................................... 17
12.2 接收文档更新通知................................................... 17
12.3 支持资源..................................................................17
12.4 Trademarks.............................................................17
12.5 Electrostatic Discharge Caution..............................17
12.6 术语表..................................................................... 17
13 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 4
6.1 Absolute Maximum Ratings........................................ 4
6.2 ESD Ratings............................................................... 4
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................5
6.5 Electrical Characteristics.............................................6
6.6 Switching Characteristics 1.8-V VCC ..........................6
6.7 Switching Characteristics 2.5-V VCC ..........................7
6.8 Switching Characteristics 3.3-V VCC ..........................7
6.9 Switching Characteristics 5.0-V VCC ..........................7
6.10 Noise Characteristics................................................7
6.11 Typical Characteristics.............................................. 8
7 Parameter Measurement Information..........................10
8 Detailed Description......................................................11
8.1 Overview................................................................... 11
Information.................................................................... 17
4 Revision History
Changes from Revision * (March 2022) to Revision A (June 2022)
Page
• 将数据表的状态从预告信息更改为量产数据..................................................................................................... 1
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5 Pin Configuration and Functions
1
2
14
13
VCC
1OE
1A
4OE
4A
3
4
12
11
1Y
4Y
2OE
2A
5
10
3OE
3A
6
7
9
8
2Y
GND
3Y
图5-1. PW Package,
14-Pin TSSOP
(Top View)
表5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1OE
1
I
I
Channel 1, output enable, active low
Channel 1, input A
1A
2
3
1Y
O
I
Channel 1, output Y
2OE
2A
4
Channel 2, output enable, active low
Channel 2, input A
5
I
2Y
6
O
G
I
Channel 2, output Y
GND
3Y
7
Ground
8
Channel 3, output Y
3A
9
I
Channel 3, input A
3OE
4Y
10
11
12
13
14
I
Channel 3, output enable, active low
Channel 4, output Y
O
I
4A
Channel 4, input A
4OE
VCC
I
Channel 4, output enable, active low
Positive supply
P
(1) I = input, O = output, I/O = input or output, G = ground, P = power.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
–0.5
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
7
7
Input voltage range
V
VO
VO
IIK
Voltage range applied to any output in the high-impedance or power-off state (2)
Voltage range applied to any output in the HIGH or LOW state (2)
4.6
V
VCC + 0.5
-20
V
Input clamp current
mA
mA
mA
mA
°C
VI < –0.5 V
IOK
IO
Output clamp current
Continuous output current
±50
VO < –0.5 V or VO > VCC + 0.5 V
VO = 0 to VCC
±35
Continuous output current through VCC or GND
Storage temperature
±70
Tstg
-65
150
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute maximum ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
briefly operating outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not
sustain damage, but it may not be fully functional. Operating the device in this manner may affect device reliability, functionality,
performance, and shorten the device lifetime.
(2) The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
6.2 ESD Ratings
VALUE
±4000
±2000
UNIT
Human body model (HBM), per AEC Q100-002 HBM ESD Classification Level 2(1)
Charged device model (CDM), per AEC Q100-011 CDM ESD Classification Level C4B
Electrostatic
discharge
V(ESD)
V
(1) AEC Q100-002 indicate that HBM stressing shall be in accordrance with the ANSI/ESDA/JEDEC JS-001 specification.
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6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER
Supply voltage
Input Voltage
CONDITION
MIN
1.6
0
MAX
5.5
UNIT
VCC
VI
V
V
V
V
5.5
3-state (Hi-Z)
0
VCC
VCC
VO
Output Voltage
HIGH or LOW state
VCC = 1.65 V to 2 V
VCC = 2.25 V to 2.75 V
VCC = 3 V to 3.6 V
0
1.1
1.28
1.45
2.00
VIH
High-level input voltage
V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 2 V
VCC = 2.25 V to 2.75 V
VCC = 3 V to 3.6 V
0.51
0.65
0.75
0.8
VIL
Low-Level input voltage
Output Current
V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 2.0 V
VCC = 2.25 V to 2.75 V
VCC = 3.3 V to 5.0 V
VCC = 1.6 V to 5.0 V
±8
IO
±15
±25
20
mA
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
Δt/Δv
TA
125
–40
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or FLoating CMOS Inputs.
6.4 Thermal Information
SN74LV4T125-Q1
THERMAL METRIC(1)
PW (TSSOP)
14 PINS
151.0
80.0
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
RθJC(top)
RθJB
94.2
Junction-to-top characterization parameter
Junction-to-board characterization parameter
Junction-to-case (bottom) thermal resistance
28.0
ΨJT
YJB
93.6
RθJC(bot)
N/A
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics
over operating free-air temperature range; typical values measured at TA = 25°C (unless otherwise noted). See Parameter
Measurement Information.
TA = 25°C
-40°C to 125°C
PARAMETER
TEST CONDITIONS
VCC
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
VCC –
VCC –
1.65 V to 5.5 V
IOH= –50 μA
0.1
0.1
1.65 V
2.3 V
1.4
1.7(1)
2.4(1)
1.35
2
IOH= –2 mA
IOH= –3 mA
IOH= –5 mA
IOH = –16 mA
IOL= 50 μA
IOL= 2 mA
VOH
V
2.05
3 V
2.7 3.08(1)
3.7 4.65(1)
2.6
3.6
4.5 V
1.65 V to 5.5 V
1.65 V
2.3 V
0.1
0.2
0.1
0.3
0.3
0.4
0.55
±1
0.1(1)
0.1(1)
0.2(1)
0.3(1)
VOL
V
IOL= 3 mA
0.2
IOL = 5 mA
3 V
0.35
0.55
±0.1
IOL= 16 mA
VI = 0 V or VCC
4.5 V
II
0 V to 5.5 V
µA
µA
VI = 0 V or VCC, IO = 0; open on
loading
ICC
1.8 V to 5.5 V
5.5 V
2
1.35
10
20
One input at 0.3 V or 3.4 V, other
inputs at 0 or VCC, IO = 0
1.5 mA
ΔICC
One input at 0.3 V or 1.1 V, other
inputs at 0 or VCC, IO = 0
1.8 V
10
µA
IOZ
IOFF
CI
VO = VCC or GND
5.5 V
0 V
±0.25
0.5
±2.5
5
µA
µA
pF
pF
pF
VO or VI = 0 V to 5.5 V
VI = VCC or GND
3.3 V
3.3 V
5 V
1.6
4.8
16
1.6
4.8
CO
VO = VCC or GND
(2) (3)
CPD
CL = 50 pF, F = 10 Mhz
(1) Typical value at nearest nominal voltage (1.8 V, 2.5 V, 3.3 V, and 5 V)
(2) CPD is used to determine the dynamic power consumption, per channel.
(3) PD= VCC 2xFIx(CPD+ CL) where FI= input frequency, CL= output load capacitance, VCC= supply voltage.
6.6 Switching Characteristics 1.8-V VCC
over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
TA = 25°C
TYP
9.1
-40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
nS
MIN
MAX
13.1
17.9
16.2
21
MIN TYP
MAX
20.2
25
CL = 15 pF
tpd
tdis
ten
A
Y
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
12.6
7.6
23.8
23.8
17.9
22.6
1
OE
OE
Y
Y
nS
14.5
8.6
15.2
18
nS
nS
12.1
tsk(o)
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6.7 Switching Characteristics 2.5-V VCC
over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
TA = 25°C
TYP
6.9
-40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
nS
MIN
MAX
9.9
MIN TYP
MAX
15.3
19
CL = 15 pF
tpd
tdis
ten
A
Y
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
9.6
13.5
12.3
15.9
9.2
5.8
18.1
18.1
13.5
17.1
1
OE
OE
Y
Y
nS
11
6.5
nS
nS
9.2
12.8
tsk(o)
6.8 Switching Characteristics 3.3-V VCC
over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
TA = 25°C
TYP
5.5
-40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
nS
MIN
MAX
7.9
MIN TYP
MAX
12.2
15.1
14.4
14.4
10.8
13.7
1
CL = 15 pF
tpd
tdis
ten
A
Y
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
7.6
10.8
9.8
4.6
OE
OE
Y
Y
nS
8.8
12.7
7.3
5.2
nS
nS
7.3
10.2
tsk(o)
6.9 Switching Characteristics 5.0-V VCC
over operating free-air temperature range (unless otherwise noted). See Parameter Measurement Information.
TA = 25°C
TYP
3.8
-40°C to 125°C
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
UNIT
nS
MIN
MAX
5.5
7.5
6.8
8.8
5.1
7.1
MIN TYP
MAX
8.5
10.5
10
CL = 15 pF
tpd
tdis
ten
A
Y
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 15 pF
CL = 50 pF
CL = 50 pF
5.3
3.2
OE
OE
Y
Y
nS
6.1
10
3.6
7.5
9.5
1
nS
nS
5.1
tsk(o)
6.10 Noise Characteristics
VCC = 3.3 V, CL = 50 pF, TA = 25°C (1)
PARAMETER
DESCRIPTION
MIN
TYP
0.4
-0.3
3
MAX
UNIT
VOL(P)
VOL(V)
VOH(V)
VIH(D)
VIL(D)
Quiet output, maximum dynamic VOL
Quiet output, minimum dynamic VOL
Quiet output, minimum dynamic VOH
High-level dynamic input voltage
Low-level dynamic input voltage
0.8
V
V
V
V
V
-0.8
2.31
0.99
(1) Characteristics are for surface-mount packages only
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6.11 Typical Characteristics
TA = 25°C (unless otherwise noted)
60
54
48
42
36
30
24
18
12
6
800
720
640
560
480
400
320
240
160
80
1.8 V
2.5 V
3.3 V
5.0 V
0
0
0
0.25 0.5 0.75
1
1.25 1.5 1.75
2
2.25 2.5
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VIN - Input Voltage (V)
VIN - Input Voltage (V)
图6-1. Supply Current Across Input Voltage 1.8-V and 2.5-V
图6-2. Supply Current Across Input Voltage 3.3-V and 5.0-V
Supply
Supply
5
4.5
4
0.55
0.5
0.45
0.4
3.5
3
0.35
0.3
0.25
0.2
2.5
0.15
2
1.5
1
1.8 V
2.5 V
3.3 V
5.0 V
1.8 V
2.5 V
3.3 V
5.0 V
0.1
0.05
0
0
-2.5 -5 -7.5 -10 -12.5 -15 -17.5 -20 -22.5 -25
IOH (mA)
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOL (mA)
图6-3. Output Voltage vs Current in HIGH State
图6-4. Output Voltage vs Current in LOW State
5
4.95
4.9
0.5
0.45
0.4
4.85
4.8
0.35
0.3
4.75
4.7
4.65
4.6
0.25
0.2
4.55
4.5
0.15
4.45
0.1
-40°C
25°C
125°C
-40°C
25°C
125°C
4.4
0.05
0
4.35
4.3
-25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5
IOH (mA)
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOL (mA)
图6-5. Output Voltage vs Current in HIGH State; 5-V Supply
图6-6. Output Voltage vs Current in LOW State; 5-V Supply
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6.11 Typical Characteristics (continued)
TA = 25°C (unless otherwise noted)
3.3
3.25
3.2
3.15
3.1
3.05
3
2.95
2.9
0.6
0.55
0.5
0.45
0.4
0.35
0.3
2.85
2.8
2.75
2.7
2.65
2.6
2.55
0.25
0.2
0.15
0.1
-40°C
25°C
125°C
-40°C
25°C
125°C
0.05
0
2.5
-25 -22.5 -20 -17.5 -15 -12.5 -10 -7.5 -5 -2.5
IOH (mA)
0
0
2.5
5
7.5 10 12.5 15 17.5 20 22.5 25
IOL (mA)
图6-7. Output Voltage vs Current in HIGH State; 3.3-V Supply
图6-8. Output Voltage vs Current in LOW State; 3.3-V Supply
2.5
2.45
2.4
0.4
0.35
0.3
2.35
2.3
0.25
0.2
2.25
2.2
2.15
2.1
0.15
2.05
0.1
-40°C
25°C
125°C
-40°C
25°C
125°C
2
0.05
0
1.95
1.9
-16
-14
-12
-10
-8
-6
-4
-2
0
0
2
4
6
8
10
12
14
16
IOH (mA)
IOL (mA)
图6-9. Output Voltage vs Current in HIGH State; 2.5-V Supply
图6-10. Output Voltage vs Current in LOW State; 2.5-V Supply
1.8
1.775
1.75
1.725
1.7
1.675
1.65
1.625
1.6
1.575
1.55
1.525
1.5
1.475
1.45
1.425
1.4
0.28
0.26
0.24
0.22
0.2
0.18
0.16
0.14
0.12
0.1
0.08
0.06
-40°C
25°C
125°C
-40°C
25°C
125°C
0.04
0.02
0
-8
-7
-6
-5
-4
-3
-2
-1
0.5
1.5
2.5
3.5
4.5
5.5
6.5
7.5
IOH (mA)
IOL (mA)
图6-11. Output Voltage vs Current in HIGH State; 1.8-V Supply
图6-12. Output Voltage vs Current in LOW State; 1.8-V Supply
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7 Parameter Measurement Information
Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators
having the following characteristics: PRR ≤1 MHz, ZO = 50 Ω.
For clock inputs, fmax is measured when the input duty cycle is 50%.
The outputs are measured one at a time with one input transition per measurement.
VCC
VCC
0 V
VOH
VOL
VOH
VOL
Test
Point
Input
Output
Output
50%
50%
S1
S2
RL
(1)
(1)
From Output
Under Test
tPLH
tPHL
(1)
CL
50%
50%
(1)
(1)
(1) CL includes probe and test-fixture capacitance.
tPHL
tPLH
图7-1. Load Circuit for 3-State Outputs
50%
50%
(1) The greater between tPLH and tPHL is the same as tpd
.
图7-2. Voltage Waveforms Propagation Delays
VCC
VCC
90%
10%
90%
Output
Control
50%
50%
Input
10%
tf(1)
0 V
0 V
VOH
VOL
tr(1)
(3)
(4)
tPZL
tPLZ
≈ VCC
90%
10%
90%
Output
Waveform 1
(1)
S1 at VLOAD
50%
Output
10%
10%
tf(1)
VOL
tr(1)
(3)
(4)
tPZH
tPHZ
(1) The greater between tr and tf is the same as tt.
VOH
Output
Waveform 2
S1 at GND(2)
图7-4. Voltage Waveforms, Input and Output
90%
50%
Transition Times
≈ 0 V
(1) S1 = CLOSED, S2 = OPEN.
(2) S1 = OPEN, S2 = CLOSED.
(3) The greater between tPZL and tPZH is the same as ten
.
(4) The greater between tPLZ and tPHZ is the same as tdis
.
图7-3. Voltage Waveforms Propagation Delays
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8 Detailed Description
8.1 Overview
The SN74LV4T125-Q1 contains four independent buffers with 3-state outputs and extended voltage operation to
allow for level translation. Each buffer performs the Boolean function Y = A in positive logic. The outputs can be
put into a Hi-Z state by applying a High on the OE pin. The output level is referenced to the supply voltage (VCC
)
and supports 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.
8.2 Functional Block Diagram
xOE
xA
xY
8.3 Feature Description
8.3.1 Balanced CMOS 3-State Outputs
This device includes balanced CMOS 3-state outputs. Driving high, driving low, and high impedance are the
three states that these outputs can be in. The term balanced indicates that the device can sink and source
similar currents. The drive capability of this device may create fast edges into light loads, so routing and load
conditions should be considered to prevent ringing. Additionally, the outputs of this device are capable of driving
larger currents than the device can sustain without being damaged. It is important for the output power of the
device to be limited to avoid damage due to overcurrent. The electrical and thermal limits defined in the Absolute
Maximum Ratings must be followed at all times.
When placed into the high-impedance mode, the output will neither source nor sink current, with the exception of
minor leakage current as defined in the Electrical Characteristics table. In the high-impedance state, the output
voltage is not controlled by the device and is dependent on external factors. If no other drivers are connected to
the node, then this is known as a floating node and the voltage is unknown. A pull-up or pull-down resistor can
be connected to the output to provide a known voltage at the output while it is in the high-impedance state. The
value of the resistor will depend on multiple factors, including parasitic capacitance and power consumption
limitations. Typically, a 10-kΩresistor can be used to meet these requirements.
Unused 3-state CMOS outputs should be left disconnected.
8.3.2 Clamp Diode Structure
The outputs to this device have both positive and negative clamping diodes, and the inputs to this device have
negative clamping diodes only as depicted in 图8-1.
CAUTION
Voltages beyond the values specified in the Absolute Maximum Ratings table can cause damage to
the device. The input and output voltage ratings may be exceeded if the input and output clamp-
current ratings are observed.
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VCC
Device
+IOK
Input
Output
Logic
GND
-IIK
-IOK
图8-1. Electrical Placement of Clamping Diodes for Each Input and Output
8.3.3 LVxT Enhanced Input Voltage
The SN74LV4T125-Q1 belongs to TI's LVxT family of logic devices with integrated voltage level translation. This
family of devices was designed with reduced input voltage thresholds to support up-translation, and inputs
tolerant of signals with up to 5.5 V levels to support down-translation. The output voltage will always be
referenced to the supply voltage (VCC), as described in the Electrical Characteristics table. To ensure proper
functionality, input signals must remain at or below the specified VIH(MIN) level for a HIGH input state, and at or
below the specified VIL(MAX) for a LOW input state. 图8-2 shows the typical VIH and VIL levels for the LVxT family
of devices, as well as the voltage levels for standard CMOS devices for comparison.
The inputs are high impedance and are typically modeled as a resistor in parallel with the input capacitance
given in the Electrical Characteristics. The worst case resistance is calculated with the maximum input voltage,
given in the Absolute Maximum Ratings, and the maximum input leakage current, given in the Electrical
Characteristics, using Ohm's law (R = V ÷ I).
The inputs require that input signals transition between valid logic states quickly, as defined by the input
transition time or rate in the Recommended Operating Conditions table. Failing to meet this specification will
result in excessive power consumption and could cause oscillations. More details can be found in the
Implications of Slow or Floating CMOS Inputs application report.
Do not leave inputs floating at any time during operation. Unused inputs must be terminated at VCC or GND. If a
system will not be actively driving an input at all times, a pull-up or pull-down resistor can be added to provide a
valid input voltage during these times. The resistor value will depend on multiple factors; however, a 10-kΩ
resistor is recommended and will typically meet all requirements.
3.6
3.4
3.3-V CMOS
3.2
VIH
3
VIL
HIGH Input
LOW Input
2.8
2.6
2.4
2.2
2
2.5-V CMOS
2.4 V (VOH
)
2 V (VOH
)
1.8-V CMOS
1.8
1.6
1.4
1.2
1
1.45 V (VOH
)
1.2-V CMOS
1.1 V (VOH
)
0.8
0.6
0.4
0.2
0
0.45 V (VOL
)
0.4 V (VOL
)
0.4 V (VOL
)
0.3 V (VOL
)
1.6 1.8
2
2.2 2.4 2.6 2.8
3
3.2 3.4 3.6 3.8
4
4.2 4.4 4.6 4.8
5
5.2
5.5
VCC - Supply Voltage (V)
图8-2. LVxT Input Voltage Levels
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8.3.3.1 Down Translation
Signals can be translated down using the SN74LV4T125-Q1. The voltage applied at the VCC will determine the
output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables.
When connected to a high-impedance input, the output voltage will be approximately VCC in the HIGH state, and
0 V in the LOW state. Ensure that the input signals in the HIGH state are between VIH(MIN) and 5.5 V, and input
signals in the LOW state are lower than VIL(MAX) as shown in 图8-2.
For example, standard CMOS inputs for devices operating at 5.0 V, 3.3 V or 2.5 V can be down-translated to
match 1.8 V CMOS signals when operating from 1.8-V VCC. See 图8-3.
Down Translation Combinations are as follows:
• 1.8-V VCC –Inputs from 2.5 V, 3.3 V, and 5.0 V
• 2.5-V VCC –Inputs from 3.3 V and 5.0 V
• 3.3-V VCC –Inputs from 5.0 V
8.3.3.2 Up Translation
Input signals can be up translated using the SN74LV4T125-Q1. The voltage applied at VCC will determine the
output voltage and the input thresholds as described in the Recommended Operating Conditions and Electrical
Characteristics tables. When connected to a high-impedance input, the output voltage will be approximately VCC
in the HIGH state, and 0 V in the LOW state.
The inputs have reduced thresholds that allow for input HIGH state levels which are much lower than standard
values. For example, standard CMOS inputs for a device operating at a 5-V supply will have a VIH(MIN) of 3.5 V.
For the SN74LV4T125-Q1, VIH(MIN) with a 5-V supply is only 2 V, which would allow for up-translation from a
typical 2.5-V to 5-V signals.
Ensure that the input signals in the HIGH state are above VIH(MIN) and input signals in the LOW state are lower
than VIL(MAX) as shown in 图8-3.
Up Translation Combinations are as follows:
• 1.8-V VCC –Inputs from 1.2 V
• 2.5-V VCC –Inputs from 1.8 V
• 3.3-V VCC –Inputs from 1.8 V and 2.5 V
• 5.0-V VCC –Inputs from 2.5 V and 3.3 V
VIH = 2.0 V
VIL = 0.8 V
VIH = 0.99 V
VIL = 0.5 V
Vcc = 5.0 V
Vcc = 1.8 V
5.0 V, 3.3 V
2.5 V, 1.8 V
1.5 V, 1.2 V
System
5.0 V
3.3 V
System
5.0 V
System
1.8 V
System
LV1Txx Logic
LV1Txx Logic
图8-3. LVxT Up and Down Translation Example
8.4 Device Functional Modes
Function Table lists the functional modes of the SN74LV4T125-Q1.
表8-1. Function Table
INPUTS(1)
OUTPUT
OE
L
A
H
L
Y
H
L
L
H
X
Z
(1) H = high voltage level, L = low voltage level, X = do not care, Z = high impedance
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9 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
9.1 Application Information
In this application, a buffer with a 3-state output is used to disable a data signal as shown in 图 9-1. The
remaining three buffers can be used for signal conditioning in other places in the system, or the inputs can be
grounded and the channels left unused.
9.2 Typical Application
System
Controller
OE
A
Y
Data
Output
图9-1. Typical Application Block Diagram
9.2.1 Design Requirements
9.2.1.1 Power Considerations
Ensure the desired supply voltage is within the range specified in the Recommended Operating Conditions. The
supply voltage sets the device's electrical characteristics as described in the Electrical Characteristics section.
The positive voltage supply must be capable of sourcing current equal to the total current to be sourced by all
outputs of the SN74LV4T125-Q1 plus the maximum static supply current, ICC, listed in the Electrical
Characteristics, and any transient current required for switching. The logic device can only source as much
current that is provided by the positive supply source. Be sure to not exceed the maximum total current through
VCC listed in the Absolute Maximum Ratings.
The ground must be capable of sinking current equal to the total current to be sunk by all outputs of the
SN74LV4T125-Q1 plus the maximum supply current, ICC, listed in the Electrical Characteristics, and any
transient current required for switching. The logic device can only sink as much current that can be sunk into its
ground connection. Be sure to not exceed the maximum total current through GND listed in the Absolute
Maximum Ratings.
The SN74LV4T125-Q1 can drive a load with a total capacitance less than or equal to 50 pF while still meeting all
of the data sheet specifications. Larger capacitive loads can be applied; however, it is not recommended to
exceed 50 pF.
The SN74LV4T125-Q1 can drive a load with total resistance described by RL ≥ VO / IO, with the output voltage
and current defined in the Electrical Characteristics table with VOH and VOL. When outputting in the HIGH state,
the output voltage in the equation is defined as the difference between the measured output voltage and the
supply voltage at the VCC pin.
Total power consumption can be calculated using the information provided in CMOS Power Consumption and
Cpd Calculation.
Thermal increase can be calculated using the information provided in Thermal Characteristics of Standard Linear
and Logic (SLL) Packages and Devices.
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CAUTION
The maximum junction temperature, TJ(max) listed in the Absolute Maximum Ratings, is an additional
limitation to prevent damage to the device. Do not violate any values listed in the Absolute Maximum
Ratings. These limits are provided to prevent damage to the device.
9.2.1.2 Input Considerations
Input signals must cross VIL(max) to be considered a logic LOW, and VIH(min) to be considered a logic HIGH. Do
not exceed the maximum input voltage range found in the Absolute Maximum Ratings.
Unused inputs must be terminated to either VCC or ground. The unused inputs can be directly terminated if the
input is completely unused, or they can be connected with a pull-up or pull-down resistor if the input will be used
sometimes, but not always. A pull-up resistor is used for a default state of HIGH, and a pull-down resistor is used
for a default state of LOW. The drive current of the controller, leakage current into the SN74LV4T125-Q1 (as
specified in the Electrical Characteristics), and the desired input transition rate limits the resistor size. A 10-kΩ
resistor value is often used due to these factors.
The SN74LV4T125-Q1 has CMOS inputs and thus requires fast input transitions to operate correctly, as defined
in the Recommended Operating Conditions table. Slow input transitions can cause oscillations, additional power
consumption, and reduction in device reliability.
Refer to the Feature Description section for additional information regarding the inputs for this device.
9.2.1.3 Output Considerations
The positive supply voltage is used to produce the output HIGH voltage. Drawing current from the output will
decrease the output voltage as specified by the VOH specification in the Electrical Characteristics. The ground
voltage is used to produce the output LOW voltage. Sinking current into the output will increase the output
voltage as specified by the VOL specification in the Electrical Characteristics.
Push-pull outputs that could be in opposite states, even for a very short time period, should never be connected
directly together. This can cause excessive current and damage to the device.
Two channels within the same device with the same input signals can be connected in parallel for additional
output drive strength.
Unused outputs can be left floating. Do not connect outputs directly to VCC or ground.
Refer to the Feature Description section for additional information regarding the outputs for this device.
9.2.2 Application Curves
OE
Data
Output
图9-2. Application Timing Diagram
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10 Power Supply Recommendations
The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Recommended Operating Conditions. Each VCC terminal should have a good bypass capacitor to prevent power
disturbance. A 0.1-μF capacitor is recommended for this device. It is acceptable to parallel multiple bypass
capacitors to reject different frequencies of noise. The 0.1-μF and 1-μF capacitors are commonly used in
parallel. The bypass capacitor should be installed as close to the power terminal as possible for best results, as
shown in the following layout example.
11 Layout
11.1 Layout Guidelines
When using multiple-input and multiple-channel logic devices, inputs must never be left floating. In many cases,
functions or parts of functions of digital logic devices are unused (for example, when only two inputs of a triple-
input AND gate are used or only 3 of the 4 buffer gates are used). Such unused input pins must not be left
unconnected because the undefined voltages at the outside connections result in undefined operational states.
All unused inputs of digital logic devices must be connected to a logic high or logic low voltage, as defined by the
input voltage specifications, to prevent them from floating. The logic level that must be applied to any particular
unused input depends on the function of the device. Generally, the inputs are tied to GND or VCC, whichever
makes more sense for the logic function or is more convenient.
11.2 Layout Example
GND VCC
Recommend GND flood fill for
improved signal isolation, noise
reduction, and thermal dissipation
Bypass capacitor
placed close to
the device
0.1 ꢀF
Unused inputs
tied to VCC
1OE
1
14
VCC
1A
1Y
2
3
4
5
6
7
13
12
11
10
9
4OE
4A
Unused output
left floating
2OE
2A
4Y
3OE
3A
2Y
Avoid 90°
corners for
signal lines
GND
8
3Y
图11-1. Example Layout for the SN74LV4T125-Q1
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12 Device and Documentation Support
TI offers an extensive line of development tools. Tools and software to evaluate the performance of the device,
generate code, and develop solutions are listed below.
12.1 Documentation Support
12.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, CMOS Power Consumption and Cpd Calculation application report
• Texas Instruments, Designing With Logic application report
• Texas Instruments, HCMOS Design Considerations data sheet
12.2 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击订阅更新 进行注册，即可每周接收产品信息更
改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
12.3 支持资源
TI E2E™ 支持论坛是工程师的重要参考资料，可直接从专家获得快速、经过验证的解答和设计帮助。搜索现有解
答或提出自己的问题可获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的《使用条款》。
12.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
所有商标均为其各自所有者的财产。
12.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
12.6 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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14-Jun-2023
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
SN74LV4T125QPWRQ1
ACTIVE
TSSOP
PW
14
2000 RoHS & Green
NIPDAU
Level-1-260C-UNLIM
-40 to 125
LV4125Q
Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV4T125-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
14-Jun-2023
Catalog : SN74LV4T125
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LV4T125QPWRQ1 TSSOP
PW
14
2000
330.0
12.4
6.9
5.6
1.6
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
9-Aug-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
TSSOP PW 14
SPQ
Length (mm) Width (mm) Height (mm)
356.0 356.0 35.0
SN74LV4T125QPWRQ1
2000
Pack Materials-Page 2
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