SN74LV8153QPWRQ1 [TI]
汽车类串行至并行接口 | PW | 20 | -40 to 125;
| 型号： | SN74LV8153QPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类串行至并行接口 | PW | 20 | -40 to 125 驱动 光电二极管 接口集成电路 |
| 文件： | 总14页 (文件大小：194K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋꢇ
ꢀꢌ ꢍꢎꢏ ꢄꢊꢐꢑ ꢊꢒꢏꢍꢏ ꢄꢄ ꢌꢄ ꢎꢁ ꢐꢌ ꢍꢓꢏ ꢔꢌ
www.ti.com
SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
DESCRIPTION
FEATURES
D
D
D
D
Qualified for Automotive Applications
The SN74LV8153 is a serial-to-parallel data converter. It
accepts serial input data and outputs 8-bit parallel data.
Single-Wire Serial Data Input
Compatible With UART Serial-Data Format
The automatic data-rate detection feature of the
SN74LV8153 eliminates the need for an external oscillator
and helps with cost and board real-estate savings.
Up to Eight Devices (64-Bit Parallel) Can
Share the Same Bus by Using Different
Combinations of A0, A1, A2
The OUTSEL pin is used to choose between open
collector and push-pull outputs. The open-collector option
is suitable when this device is used in applications such as
LED interface, where high drive current is required. SOUT
is the output that acknowledges reception of the serial
data.
D
D
D
D
D
D
Up to 40 mA Current Drive in Open-Collector
Mode for Driving LEDs
Outputs Can be Configured as
Open-Collector or Push-Pull
Internal Oscillator and Counter for
Automatic Data-Rate Detection
To ensure the high-impedance state during power up or
Output Levels Are Referenced to V
and
CC2
power down, OE should be tied to V
through a pullup
CC1
Can Be Configured From 3 V to 12 V
resistor; the minimum value of the resistor is determined
by the current-sinking capability of the driver.
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 1000-V Charged-Device Model (C101)
PW PACKAGE
(TOP VIEW)
V
1
2
3
4
5
6
7
8
9
10
20
19 Y0
18
V
SUMMARY OF RECOMMENDED
OPERATING CONDITIONS
CC1
A0
CC2
A1
A2
D
Y1
PARAMETER
17 Y2
16 Y3
15 Y4
14 Y5
V
3 V to 5.5 V
CC1
CC2
OUTSEL
RESET
OE
V
3 V to 13.2 V
40 mA @ V
CC2
= 4.5 V
I
I
OL
(open-collector mode)
13
12
11
Y6
Y7
GND
SOUT
GND
−24 mA @ V = 12 V
CC2
OH
(push-pull mode)
Maximum Data Rate
24 Kbps
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
ꢒꢍ ꢑ ꢕꢖ ꢔ ꢐꢎ ꢑꢁ ꢕ ꢏꢐꢏ ꢗꢘ ꢙꢚ ꢛ ꢜꢝ ꢞꢗꢚꢘ ꢗꢟ ꢠꢡ ꢛ ꢛ ꢢꢘꢞ ꢝꢟ ꢚꢙ ꢣꢡꢤ ꢥꢗꢠ ꢝꢞꢗ ꢚꢘ ꢦꢝ ꢞꢢꢧ ꢒꢛ ꢚꢦꢡ ꢠꢞꢟ
ꢠ ꢚꢘ ꢙꢚꢛ ꢜ ꢞꢚ ꢟ ꢣꢢ ꢠ ꢗ ꢙꢗ ꢠ ꢝ ꢞꢗ ꢚꢘꢟ ꢣ ꢢꢛ ꢞꢨꢢ ꢞꢢ ꢛ ꢜꢟ ꢚꢙ ꢐꢢꢩ ꢝꢟ ꢎꢘꢟ ꢞꢛ ꢡꢜ ꢢꢘꢞ ꢟ ꢟꢞ ꢝꢘꢦ ꢝꢛ ꢦ ꢪ ꢝꢛ ꢛ ꢝ ꢘꢞꢫꢧ
ꢒꢛ ꢚ ꢦꢡꢠ ꢞ ꢗꢚ ꢘ ꢣꢛ ꢚ ꢠ ꢢ ꢟ ꢟ ꢗꢘ ꢬ ꢦꢚ ꢢ ꢟ ꢘꢚꢞ ꢘꢢ ꢠꢢ ꢟꢟ ꢝꢛ ꢗꢥ ꢫ ꢗꢘꢠ ꢥꢡꢦ ꢢ ꢞꢢ ꢟꢞꢗ ꢘꢬ ꢚꢙ ꢝꢥ ꢥ ꢣꢝ ꢛ ꢝꢜ ꢢꢞꢢ ꢛ ꢟꢧ
Copyright 2008, Texas Instruments Incorporated
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
FUNCTION TABLE
(each buffer)
INPUTS
OUTPUT
OUTPUT
Yn
STRUCTURE
OUTSEL RESET
OE
L
Dn
H
L
L
L
H
H
X
L
L
H
H
H
H
L
L
Open collector
Push-pull
L
H
X
L
X
X
H
L
L
H
H
H
H
H
H
X
L
L
H
L
X
X
Z
L
In the open-collector mode (OUTSEL = L), the outputs are inverted,
e.g., Y1 = l, when D1 = H
{
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
}
T
A
PACKAGE
−40°C to 125°C
TSSOP − PW
Tape and reel
SN74LV8153QPWRQ1
LV8153Q
†
‡
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or
see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
PIN DESCRIPTION
PIN #
PIN NAME
I/O
PIN FUNCTION
1
V
CC1
Power-supply pin (all inputs and outputs except for Y0-Y7)
The address pins are used to program the address of the device and allow up to eight
devices to share the same bus.
2-4
A0, A1, A2
In
5
D
In
In
Serial data input
6
7
OUTSEL
RESET
OE
Choose between open-collector and push-pull type outputs (Y0-Y7).
Initialize register status
In
8
In
Force Y0-Y7 to Hi-Z
9
SOUT
Y0-Y7
Out
Out
Outputs a pulse when latch data is changed. Supplied by V .
CC1
12-19
20
Push-pull or open collector parallel data outputs. Supplied by V .
CC2
V
CC2
Power-supply pin for outputs (Y0-Y7). V can range from 3 V to 13.2 V.
CC2
2
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
data transmission protocol
− The serial data should be sent as 2START-3ADDRESS-4DATA-1STOP. Two consecutive serial-data
frames transmit 8 bits of data. The first frame includes the lower four bits of data (D0-D3), and the
second frame includes the upper four bits (D4-D7).
− The three address bits (in the consecutive frame) must be the same as those in the first frame;
otherwise, the data will be dropped.
− The order of the two start bits must be 0, then 1 in any frame; otherwise, the data rate will not be
detected correctly. The period between the falling edge of the first start bit (ST0) and the rising edge of
the second start bit (ST1) is measured to generate an internal-clock synchronized data stream.
1st Frame
2nd Frame
ST0
ST0
ST0
A0 A1 A2 D0 D1 D2 D3
A0 A1 A2 D4 D5 D6 D7
ST1
ST1
SP
ST1
SP
SP
Example of Serial-Data Format
ST0
A0 A1 A2 D0 D1 D2 D3
A0 A1 A2 D4 D5 D6
D7
DATA
SP
ST1
Internal Clock
Y0−Y7
SOUT
Timing Chart
(1)
(1)
Internal clock cannot be observed.
D0 is LSB and D7 is MSB. The data stream should be LSB first.
3
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
logic diagram
Power
On
Data
8-Bit S/R
Reset
OC
CLK
4 Data
Timing
and
Address
Y0
Y7
Timing
Control
4
Verification
OC
4
3
OSC
3-Bit
Register
3
Address Data
SOUT
A0
A1
A2
RESET
OUTSEL
OE
(1)
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 14.5 V
CC1
CC2
(2)
Input voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
I
(2)(3)
Voltage range applied to any output in the high or low state, V (SOUT)
. . . . −0.5 V to V
+ 0.5 V
CC1
O
Voltage range applied to any output in the high-impedance
(2)
or power-off state, V (SOUT)
Voltage range, applied to any output in the high or low state, V (Y0-Y7)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V
(2)(3)
O
. . . . −0.5 V to V
+ 0.5 V
CC2
O
Voltage range applied to any output in the high-impedance
(2)
or power-off state, V (Y0-Y7)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 14.5 V
O
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −20 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 mA
O
O
CC
Continuous current, I (OUTSEL = L, Y0-Y7 = L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
O
(4)
Package thermal impedance, θ
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
JA
stg
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2)
(3)
(4)
The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
The value of V
is provided in the recommended operating condition table.
The package thermal impedance is calculated in accordance with JESD 51-7.
CC
4
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
(1)
recommended operating conditions
V
CC1
V
CC2
MIN
3
MAX
5.5
UNIT
V
V
V
Supply voltage
Supply voltage
CC1
3
13.2
V
CC2
3 V
3 V
V
V
× 0.7
CC
V
High-level input voltage
V
IH
4.5 V
3 V
4.5 V
3 V
× 0.7
CC
V
V
× 0.3
CC
V
V
Low-level input voltage
Input voltage
V
V
IL
4.5 V
4.5 V
× 0.3
5.5
CC
0
0
0
I
4.5 V
4.5 V
12 V
3 V
5.5
V
O
Output voltage
V
13.2
3 V
−2
−8
4.5 V
4.5 V
3 V
4.5 V
12 V
3 V
Yn
OUTSEL = H
mA
mA
−24
−4
−8
2
I
High-level output current
OH
SOUT
Yn
4.5 V
3 V
4.5 V
3 V
OUTSEL = H
OUTSEL = L
4.5 V
3 V
4.5 V
3 V
8
20
40
4
I
Low-level output current
mA
OL
4.5 V
3 V
4.5 V
3 V
SOUT
4.5 V
4.5 V
8
T
A
Operating free-air temperature
−40
125
°C
(1)
All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report, Implications
of Slow or Floating CMOS Inputs, literature number SCBA004.
CC
5
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.31
3.5
UNIT
V
V
CC2
CC1
V
T+
3.3 V
5 V
3.3 V
5 V
Positive-going input threshold
voltage
All inputs
All inputs
All inputs
V
V
T−
3.3 V
5 V
3.3 V
5 V
0.99
1.5
Negative-going input threshold
voltage
V
V
∆V
3.3 V
5 V
3.3 V
5 V
0.33
0.5
1.32
2
T
Hysteresis
(V − V
)
T+ T−
I
I
I
I
I
I
I
I
I
I
= −2 mA
3 V
4.5 V
4.5 V
3 V
3 V
4.5 V
12 V
3 V
2.38
3.8
OH
OH
OH
OH
OH
OL
OL
OL
OL
OL
= −8 mA
Yn
= −24 mA
11
V
V
V
OH
= −4 mA
2.38
3.8
SOUT
Yn
= −8 mA
4.5 V
3 V
4.5 V
3 V
= 2 mA (OUTSEL = H)
= 8 mA (OUTSEL = H)
= 40 mA (OUTSEL = L)
= 4 mA
0.44
0.44
0.5
0.44
0.44
1
4.5 V
4.5 V
3 V
4.5 V
4.5 V
3 V
V
OL
SOUT
= 8 mA
4.5 V
0 to 5.5 V
5.5 V
5.5 V
4.5 V
I
I
I
V = 5.5 V or GND
µA
µA
µA
I
I
V
= V
or GND (OUTSEL = H)
= 12 V (OUTSEL = L)
5.5 V
5.5 V
5
OZ
OH
O
O
CC
V
5
OUTSEL = H
OUTSEL = L
5
I
V = V
I CC
or GND, I = 0
5.5 V
5.5 V
mA
CC
O
20
I
off
(except SOUT)
V or V = 0 to 5.5 V, V
= 0
0
0
50
µA
I
O
CC
C
i
V = V
or GND
5 V
5 V
5
pF
I
CC
switching characteristics over recommended operating free-air temperature range,
= V = 3.3 V 0.3 V (unless otherwise noted) (see Figures 1 and 2)
V
CC1
CC2
T
A
= 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN MAX
UNIT
MIN
MAX
(1)
D7
D7
Y
SOUT
Y
Pw/2
Pw/2
(1)
t
ns
pd
RESET
220
220
(2)
(3)
(3)
OE
OE
OE
Y
C
L
= 50 pF
t
en
Y
Y
220
220
ns
ns
t
dis
(4)
t
w
SOUT
Pw
ns
Data rate
2
24
Kbps
(1)
The t is dependent on the data pulse width (Pw), and Y outputs are changed after one-half of Pw, because the internal clock is synchronized
pd
at the middle of the data pulse. Not tested, but specified by design.
(2)
(3)
(4)
When outputs are open collector (OUTSEL = L)
When outputs are push-pull (OUTSEL = H)
SOUT goes low when the data is received correctly and maintains a low level for one data-pulse period. Not tested, but specified by design.
6
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
switching characteristics over recommended operating free-air temperature range,
= V = 5 V 0.5 V (unless otherwise noted) (see Figures 1 and 2)
V
CC1
CC2
T
A
= 25°C
TYP
FROM
(INPUT)
TO
(OUTPUT)
LOAD
CAPACITANCE
PARAMETER
MIN MAX
UNIT
MIN
MAX
(1)
D7
D7
Y
SOUT
Y
Pw/2
Pw/2
(1)
t
ns
pd
RESET
200
200
(2)
(3)
(3)
OE
OE
OE
Y
C
L
= 50 pF
t
en
Y
Y
200
200
ns
ns
t
dis
(4)
t
w
SOUT
Pw
ns
Data rate
2
24
Kbps
(1)
The t is dependent on the data pulse width (Pw), and Y outputs are changed after one-half of Pw, because the internal clock is synchronized
pd
at the middle of the data pulse. Not tested, but specified by design.
(2)
(3)
(4)
When outputs are open collector (OUTSEL = L)
When outputs are push-pull (OUTSEL = H)
SOUT goes low when the data is received correctly and maintains a low level for one data-pulse period. Not tested, but specified by design.
7
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SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
(PUSH-PULL OUTPUT)
V
CC1
Open
GND
S1
R
L
= 1 kΩ
From Output
Under Test
TEST
/t
PLH PHL
S1
t
t
Open
C
L
= 50 pF
t
/t
V
(see Note A)
PLZ PZL
/t
CC1
GND
PHZ PZH
50% V
CC1
LOAD CIRCUIT
V
V
CC1
CC1
Output
Control
50% V
CC1
50% V
CC1
50% V
CC1
50% V
CC1
Input
0 V
0 V
t
t
PLZ
t
t
t
PZL
PLH
PHL
Output
Waveform 1
≈V
V
CC1
OH
In-Phase
Output
50% V
CC1
50%V
CC1
50% V
CC1
V
V
OL
+ 0.3 V
S1 at V
(see Note B)
CC
V
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
Output
Waveform 2
S1 at GND
V
V
OH
OH
Out-of-Phase
Output
V
OH
− 0.3 V
50% V
CC1
50% V
CC1
50% V
CC1
≈0 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time, with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PLH
are the same as t
.
dis
PLZ
PZL
PHL
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
8
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋꢇ
ꢀꢌ ꢍꢎꢏ ꢄꢊꢐꢑ ꢊꢒꢏꢍꢏ ꢄꢄ ꢌꢄ ꢎꢁꢐ ꢌꢍ ꢓꢏ ꢔꢌ
www.ti.com
SCLS591A − SEPTEMBER 2004 − REVISED APRIL 2008
PARAMETER MEASUREMENT INFORMATION
(OPEN-COLLECTOR OUTPUT)
V
CC1
V
CC1
R
L
= 500 Ω
50%V
CC1
50% V
CC1
Input
0 V
From Output
Under Test
Test
Point
t
t
PHL
PLH
≈V
C
CC1
L
50%V
CC1
(see Note A)
Output
V
OL
+ 0.3 V
V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
LOAD CIRCUIT FOR
OPEN-COLLECTOR OUTPUTS
NOTES: A.
C
L
includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
C. The outputs are measured one at a time, with one input transition per measurement.
D. and t are the same as t
t
.
PHL
PLH pd
Figure 2. Load Circuit and Voltage Waveforms
9
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2010
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LV8153QPWRG4Q1
SN74LV8153QPWRQ1
ACTIVE
ACTIVE
TSSOP
TSSOP
PW
PW
20
20
2000
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Request Free Samples
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Purchase Samples
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LV8153-Q1 :
Catalog: SN74LV8153
•
NOTE: Qualified Version Definitions:
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Jun-2010
Catalog - TI's standard catalog product
•
Addendum-Page 2
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相关型号：
SN74LV8154MPWREP
Enhanced Product Dual 16-Bit Binary Counter With 3-State Output Registers 20-TSSOP -55 to 125
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