SN74LVC00AMPWREPG4 [TI]

QUADRUPLE 2-INPUT POSITIVE-NAND GATE;
SN74LVC00AMPWREPG4
型号: SN74LVC00AMPWREPG4
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

QUADRUPLE 2-INPUT POSITIVE-NAND GATE

输入元件
文件: 总22页 (文件大小:908K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
FEATURES  
Operate From 1.65 V to 3.6 V  
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
Specified From –40°C to 85°C, –40°C to 125°C,  
and –55°C to 125°C  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
Inputs Accept Voltages to 5.5 V  
Max tpd of 4.3 ns at 3.3 V  
Typical VOLP (Output Ground Bounce)  
– 1000-V Charged-Device Model (C101)  
<0.8 V at VCC = 3.3 V, TA = 25°C  
xxxxxx  
xxxxxx  
Typical VOHV (Output VOH Undershoot)  
>2 V at VCC = 3.3 V, TA = 25°C  
SN54LVC00A . . . J OR W PACKAGE  
SN74LVC00A . . . D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
SN74LVC00A . . . RGY PACKAGE  
(TOP VIEW)  
SN54LVC00A . . . FK PACKAGE  
(TOP VIEW)  
1
2
3
4
5
6
7
1A  
1B  
V
CC  
14  
13  
1
14  
3
2
1
20 19  
18  
4B  
4A  
NC  
4Y  
NC  
3B  
1Y  
NC  
2A  
4
5
6
7
8
1B  
1Y  
2A  
2B  
2Y  
13 4B  
2
3
4
5
6
1Y  
2A  
2B  
2Y  
12 4A  
17  
16  
15  
14  
12  
11  
10  
9
4A  
4Y  
3B  
3A  
4Y  
3B  
3A  
3Y  
11  
10  
9
NC  
2B  
GND  
8
9 10 11 12 13  
7
8
NC - No internal connection  
DESCRIPTION/ORDERING INFORMATION  
The SN54LVC00A quadruple 2-input positive-NAND gate is designed for 2.7-V to 3.6-V VCC operation, and the  
SN74LVC00A quadruple 2-input positive-NAND gate is designed for 1.65-V to 3.6-V VCC operation.  
The 'LVC00A devices perform the Boolean function Y = A B or Y = A + B in positive logic.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators  
in a mixed 3.3-V/5-V system environment.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas  
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 1993–2005, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
On products compliant to MIL-PRF-38535, all parameters are  
Instruments standard warranty. Production processing does not  
tested unless otherwise noted. On all other products, production  
necessarily include testing of all parameters.  
processing does not necessarily include testing of all parameters.  
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
ORDERING INFORMATION  
TA  
PACKAGE(1)  
ORDERABLE PART NUMBER  
TOP-SIDE MARKING  
–40°C to 85°C  
QFN – RGY  
SOIC – D  
Reel of 1000  
Tube of 50  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Reel of 250  
Tube of 25  
Tube of 150  
Tube of 55  
SN74LVC00ARGYR  
SN74LVC00AD  
LC00A  
SN74LVC00ADR  
SN74LVC00ADT  
SN74LVC00ANSR  
SN74LVC00ADBR  
SN74LVC00APW  
SN74LVC00APWR  
SN74LVC00APWT  
SNJ54LVC00AJ  
LVC00A  
SOP – NS  
LVC00A  
LC00A  
–40°C to 125°C  
SSOP – DB  
TSSOP – PW  
LC00A  
CDIP – J  
CFP – W  
LCCC – FK  
SNJ54LVC00AJ  
SNJ54LVC00AW  
SNJ54LVC00AFK  
–55°C to 125°C  
SNJ54LVC00AW  
SNJ54LVC00AFK  
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
FUNCTION TABLE  
(EACH GATE)  
INPUTS  
OUTPUT  
Y
A
H
L
B
H
X
L
L
H
H
X
LOGIC DIAGRAM, EACH GATE (POSITIVE LOGIC)  
A
Y
B
2
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
Absolute Maximum Ratings(1)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
–0.5  
–0.5  
MAX  
6.5  
UNIT  
V
VCC  
VI  
Supply voltage range  
Input voltage range(2)  
6.5  
V
VO  
IIK  
Output voltage range(2)(3)  
–0.5 VCC + 0.5  
V
Input clamp current  
VI < 0  
–50  
–50  
±50  
±100  
86  
mA  
mA  
mA  
mA  
IOK  
IO  
Output clamp current  
VO < 0  
Continuous output current  
Continuous current through GND  
VCC  
D package(4)  
DB package(4)  
NS package(4)  
PW package(4)  
RGY package(5)  
96  
θJA  
Package thermal impedance  
76  
°C/W  
113  
47  
Tstg  
Ptot  
Storage temperature range  
Power dissipation(6)(7)  
–65  
150  
500  
°C  
TA = –40°C to 125°C  
mW  
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings  
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating  
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
(3) The value of VCC is provided in the recommended operating conditions table.  
(4) The package thermal impedance is calculated in accordance with JESD 51-7.  
(5) The package thermal impedance is calculated in accordance with JESD 51-5.  
(6) For the D package: above 70°C, the value of Ptot derates linearly with 8 mW/K.  
(7) For the DB, NS, and PW packages: above 60°C, the value of Ptot derates linearly with 5.5 mW/K.  
3
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
Recommended Operating Conditions(1)  
SN54LVC00A  
–55°C to 125°C  
UNIT  
MIN  
2
MAX  
Operating  
3.6  
VCC Supply voltage  
V
Data retention only  
VCC = 2.7 V to 3.6 V  
VCC = 2.7 V to 3.6 V  
1.5  
2
VIH  
VIL  
VI  
High-level input voltage  
V
V
V
V
Low-level input voltage  
Input voltage  
0.8  
5.5  
VCC  
–12  
–24  
12  
0
0
VO  
Output voltage  
VCC = 2.7 V  
VCC = 3 V  
VCC = 2.7 V  
VCC = 3 V  
IOH  
High-level output current  
Low-level output current  
mA  
mA  
IOL  
24  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
Recommended Operating Conditions(1)  
SN74LVC00A  
TA = 25°C  
MIN  
–40°C to 85°C  
–40°C to 125°C  
UNIT  
V
MAX  
MIN  
MAX  
MIN  
MAX  
Operating  
1.65  
3.6  
1.65  
3.6  
1.65  
3.6  
VCC  
Supply voltage  
Data retention only  
1.5  
1.5  
1.5  
VCC = 1.65 V to 1.95 V 0.65 × VCC  
0.65 × VCC  
0.65 × VCC  
High-level  
input voltage  
VIH  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
VCC = 1.65 V to 1.95 V  
VCC = 2.3 V to 2.7 V  
VCC = 2.7 V to 3.6 V  
1.7  
2
1.7  
2
1.7  
2
V
0.35 × VCC  
0.35 × VCC  
0.35 × VCC  
Low-level  
input voltage  
VIL  
0.7  
0.8  
5.5  
VCC  
–4  
0.7  
0.8  
5.5  
VCC  
–4  
0.7  
0.8  
5.5  
VCC  
–4  
V
VI  
Input voltage  
0
0
0
0
0
0
V
V
VO  
Output voltage  
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
–8  
–8  
–8  
High-level  
output current  
IOH  
mA  
mA  
–12  
–24  
4
–12  
–24  
4
–12  
–24  
4
VCC = 1.65 V  
VCC = 2.3 V  
VCC = 2.7 V  
VCC = 3 V  
8
8
8
Low-level  
output current  
IOL  
12  
12  
12  
24  
24  
24  
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
4
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
SN54LVC00A  
PARAMETER  
TEST CONDITIONS  
VCC  
–55°C to 125°C  
UNIT  
V
MIN MAX  
IOH = –100 µA  
2.7 V to 3.6 V  
2.7 V  
VCC – 0.2  
2.2  
VOH  
IOH = –12 mA  
3 V  
2.4  
IOH = –24 mA  
3 V  
2.2  
IOL = 100 µA  
2.7 V to 3.6 V  
2.7 V  
0.2  
VOL  
IOL = 12 mA  
0.4  
V
IOL = 24 mA  
3 V  
0.55  
±5  
II  
VI = 5.5 V or GND  
VI = VCC or GND, IO = 0  
3.6 V  
µA  
µA  
µA  
ICC  
3.6 V  
10  
ICC  
One input at VCC – 0.6 V, Other inputs at VCC or GND  
2.7 V to 3.6 V  
500  
Electrical Characteristics  
over recommended operating free-air temperature range (unless otherwise noted)  
SN74LVC00A  
–40°C to 85°C  
PARAMETER  
TEST CONDITIONS  
VCC  
TA = 25°C  
–40°C to 125°C  
UNIT  
MIN  
TYP  
MAX  
MIN  
VCC – 0.2  
1.2  
MAX  
MIN  
VCC – 0.3  
1.05  
MAX  
IOH = –100 µA  
IOH = –4 mA  
IOH = –8 mA  
1.65 V to 3.6 V VCC – 0.2  
1.65 V  
2.3 V  
1.29  
1.9  
2.2  
2.4  
2.3  
1.7  
1.55  
VOH  
V
2.7 V  
2.2  
2.05  
IOH = –12 mA  
3 V  
2.4  
2.25  
IOH = –24 mA  
IOL = 100 µA  
IOL = 4 mA  
3 V  
2.2  
2
1.65 V to 3.6 V  
1.65 V  
2.3 V  
0.1  
0.24  
0.3  
0.2  
0.45  
0.7  
0.3  
0.6  
VOL  
IOL = 8 mA  
0.85  
0.6  
V
IOL = 12 mA  
IOL = 24 mA  
VI = 5.5 V or GND  
2.7 V  
0.4  
0.4  
3 V  
0.55  
±1  
0.55  
±5  
0.8  
II  
3.6 V  
±20  
µA  
µA  
VI = VCC or GND,  
IO = 0  
ICC  
3.6 V  
1
10  
40  
One input at  
VCC – 0.6 V,  
Other inputs at  
VCC or GND  
ICC  
2.7 V to 3.6 V  
3.3 V  
500  
500  
5000  
µA  
Ci  
VI = VCC or GND  
5
pF  
5
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
Switching Characteristics  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
SN54LVC00A  
–55°C to 125°C  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
VCC  
UNIT  
MIN  
MAX  
5.1  
2.7 V  
tpd  
A or B  
Y
ns  
3.3 V ± 0.3 V  
1
4.3  
Switching Characteristics  
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)  
SN74LVC00A  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
VCC  
TA = 25°C  
–40°C to 85°C  
–40°C to 125°C  
UNIT  
MIN TYP MAX  
MIN  
1
MAX  
12.5  
6.4  
5.1  
4.3  
1
MIN  
1
MAX  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
2.7 V  
1
1
1
1
6
4.6  
4.3  
3.5  
12  
5.9  
4.9  
4.1  
14  
7.9  
6.5  
5.5  
1.5  
1
1
tpd  
A or B  
Y
ns  
ns  
1
1
3.3 V ± 0.3 V  
3.3 V ± 0.3 V  
1
1
tsk(o)  
Operating Characteristics  
TA = 25°C  
PARAMETER  
TEST CONDITIONS  
VCC  
TYP UNIT  
1.8 V  
2.5 V  
3.3 V  
18  
Cpd  
Power dissipation capacitance per gate  
f = 10 MHz  
18  
19  
pF  
6
SN54LVC00A, SN74LVC00A  
QUADRUPLE 2-INPUT POSITIVE-NAND GATES  
www.ti.com  
SCAS279PJANUARY 1993REVISED JULY 2005  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
S1  
Open  
R
L
From Output  
Under Test  
TEST  
/t  
S1  
GND  
t
t
Open  
PLH PHL  
C
L
t
/t  
V
R
L
PLZ PZL  
LOAD  
GND  
(see Note A)  
/t  
PHZ PZH  
LOAD CIRCUIT  
INPUTS  
V
CC  
V
M
V
LOAD  
C
L
R
L
V
V
I
t /t  
r f  
1.8 V ± 0.15 V  
2.5 V ± 0.2 V  
2.7 V  
V
V
2.7 V  
2.7 V  
2 ns  
2 ns  
2.5 ns  
2.5 ns  
V
/2  
/2  
2 × V  
2 × V  
6 V  
6 V  
30 pF  
30 pF  
50 pF  
50 pF  
1 k  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
CC  
CC  
CC  
V
CC  
CC  
CC  
1.5 V  
1.5 V  
3.3 V ± 0.3 V  
0.3 V  
V
I
Timing Input  
Data Input  
V
M
0 V  
t
w
t
t
h
su  
V
I
V
I
Input  
V
M
V
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
I
V
I
Output  
Control  
V
M
V
M
Input  
V
M
V
M
0 V  
0 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
PLH  
Output  
Waveform 1  
V
V
OH  
V
V
/2  
LOAD  
V
V
V
M
M
Output  
V
V
M
S1 at V  
LOAD  
V
OL  
+ V  
OL  
(see Note B)  
OL  
t
PHL  
PLH  
t
t
PHZ  
PZH  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
V
OH  
V
- V  
V
M
OH  
M
Output  
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. C includes probe and jig capacitance.  
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
are the same as t  
.
dis  
.
PLZ  
PZL  
PLH  
PHZ  
are the same as t  
PZH  
en  
are the same as t .  
PHL pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
7
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
PACKAGING INFORMATION  
Orderable Device  
Status (1)  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
LCCC  
CDIP  
CFP  
Drawing  
5962-9753301Q2A  
5962-9753301QCA  
5962-9753301QDA  
5962-9753301V2A  
5962-9753301VCA  
5962-9753301VDA  
SN74LVC00AD  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
FK  
J
20  
14  
14  
20  
14  
14  
14  
1
1
1
1
1
1
TBD  
TBD  
TBD  
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
FK  
J
LCCC  
CDIP  
CFP  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
D
SOIC  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00ADBLE  
SN74LVC00ADBR  
OBSOLETE  
ACTIVE  
SSOP  
SSOP  
DB  
DB  
14  
14  
TBD  
Call TI  
Call TI  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00ADBRE4  
SN74LVC00ADBRG4  
SN74LVC00ADE4  
SN74LVC00ADG4  
SN74LVC00ADR  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
SSOP  
SSOP  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SOIC  
SO  
DB  
DB  
D
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
14  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
50 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00ADRE4  
SN74LVC00ADRG4  
SN74LVC00ADT  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00ADTE4  
SN74LVC00ADTG4  
SN74LVC00ANSR  
SN74LVC00ANSRG4  
SN74LVC00APW  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
D
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
NS  
NS  
PW  
PW  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SO  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
TSSOP  
TSSOP  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00APWE4  
SN74LVC00APWG4  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
90 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00APWLE  
SN74LVC00APWR  
OBSOLETE TSSOP  
PW  
PW  
14  
14  
TBD  
Call TI  
Call TI  
ACTIVE  
ACTIVE  
ACTIVE  
TSSOP  
TSSOP  
TSSOP  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00APWRE4  
SN74LVC00APWRG4  
PW  
PW  
14  
14  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Oct-2007  
Orderable Device  
SN74LVC00APWT  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
TSSOP  
PW  
14  
14  
14  
14  
14  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
SN74LVC00APWTE4  
SN74LVC00APWTG4  
SN74LVC00ARGYR  
SN74LVC00ARGYRG4  
TSSOP  
TSSOP  
QFN  
PW  
PW  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
RGY  
RGY  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
QFN  
1000 Green (RoHS & CU NIPDAU Level-2-260C-1 YEAR  
no Sb/Br)  
SNJ54LVC00AFK  
SNJ54LVC00AJ  
SNJ54LVC00AW  
ACTIVE  
ACTIVE  
ACTIVE  
LCCC  
CDIP  
CFP  
FK  
J
20  
14  
14  
1
1
1
TBD  
TBD  
TBD  
POST-PLATE N / A for Pkg Type  
A42 SNPB  
A42  
N / A for Pkg Type  
N / A for Pkg Type  
W
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
TAPE AND REEL BOX INFORMATION  
Device  
Package Pins  
Site  
Reel  
Reel  
A0 (mm)  
B0 (mm)  
K0 (mm)  
P1  
W
Pin1  
Diameter Width  
(mm) (mm) Quadrant  
(mm)  
330  
330  
330  
330  
330  
180  
(mm)  
16  
SN74LVC00ADBR  
SN74LVC00ADR  
SN74LVC00ADR  
SN74LVC00ANSR  
SN74LVC00APWR  
SN74LVC00ARGYR  
DB  
D
14  
14  
14  
14  
14  
14  
SITE 41  
SITE 27  
SITE 41  
SITE 41  
SITE 41  
SITE 41  
8.2  
6.5  
6.5  
8.2  
7.0  
3.85  
6.6  
9.0  
2.5  
2.1  
2.1  
2.5  
1.6  
1.35  
12  
8
16  
16  
16  
16  
12  
12  
Q1  
Q1  
Q1  
Q1  
Q1  
Q1  
16  
D
16  
9.0  
8
NS  
PW  
RGY  
16  
10.5  
5.6  
12  
8
12  
12  
3.85  
8
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
4-Oct-2007  
Device  
Package  
Pins  
Site  
Length (mm) Width (mm) Height (mm)  
SN74LVC00ADBR  
SN74LVC00ADR  
SN74LVC00ADR  
SN74LVC00ANSR  
SN74LVC00APWR  
SN74LVC00ARGYR  
DB  
D
14  
14  
14  
14  
14  
14  
SITE 41  
SITE 27  
SITE 41  
SITE 41  
SITE 41  
SITE 41  
346.0  
342.9  
346.0  
346.0  
346.0  
190.0  
346.0  
336.6  
346.0  
346.0  
346.0  
212.7  
33.0  
28.58  
33.0  
D
NS  
PW  
RGY  
33.0  
29.0  
31.75  
Pack Materials-Page 2  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements,  
improvements, and other changes to its products and services at any time and to discontinue any product or service without notice.  
Customers should obtain the latest relevant information before placing orders and should verify that such information is current and  
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s  
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TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and  
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DSP  
Applications  
Audio  
amplifier.ti.com  
dataconverter.ti.com  
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www.ti.com/audio  
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Military  
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www.ti.com/military  
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logic.ti.com  
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Microcontrollers  
RFID  
power.ti.com  
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Security  
www.ti.com/opticalnetwork  
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