SN74LVC06AQDRQ1 [TI]
具有漏极开路输出的汽车类 6 通道、1.65V 至 3.6V 反相器 | D | 14 | -40 to 125;
| 型号： | SN74LVC06AQDRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有漏极开路输出的汽车类 6 通道、1.65V 至 3.6V 反相器 | D | 14 | -40 to 125 栅 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：210K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC06A-Q1
www.ti.com .................................................................................................................................................. SCAS761B–FEBRUARY 2004–REVISED APRIL 2008
HEX INVERTER BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
1
FEATURES
D OR PW PACKAGE
•
•
•
Qualified for Automotive Applications
(TOP VIEW)
Operate From 1.65 V to 3.6 V
1A
1Y
2A
2Y
3A
1
2
3
4
5
6
7
14
V
CC
Inputs and Open-Drain Outputs Accept
Voltages up to 5.5 V
13 6A
12 6Y
•
•
Max tpd of 3.7 ns at 3.3 V
5A
5Y
4A
4Y
11
10
9
Ioff Supports Partial-Power-Down Mode
Operation
3Y
GND
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
8
DESCRIPTION/ORDERING INFORMATION
This hex inverter buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
The outputs of the SN74LVC06A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator in
a mixed 3.3-V/5-V system environment.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
Reel of 2500
Reel of 2000
ORDERABLE PART NUMBER
SN74LVC06AQDRQ1
TOP-SIDE MARKING
LVC06AQ
SOIC – D
–40°C to 125°C
TSSOP – PW
SN74LVC06AQPWRQ1
LVC06AQ
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(EACH INVERTER)
INPUT
A
OUTPUT
Y
H
L
L
H
LOGIC DIAGRAM, EACH INVERTER (POSITIVE LOGIC)
A
Y
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2008, Texas Instruments Incorporated
SN74LVC06A-Q1
SCAS761B–FEBRUARY 2004–REVISED APRIL 2008.................................................................................................................................................. www.ti.com
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
6.5
6.5
V
V
VO
IIK
Output voltage range
6.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
86
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
D package
(3)
θJA
Package thermal impedance
°C/W
°C
PW package
113
150
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
5.5
4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
Low-level output current
mA
12
24
125
TA
Operating free-air temperature
–40
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
Submit Documentation Feedback
Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC06A-Q1
SN74LVC06A-Q1
www.ti.com .................................................................................................................................................. SCAS761B–FEBRUARY 2004–REVISED APRIL 2008
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
MIN TYP(1)
MAX UNIT
IOL = 100 µA
IOL = 4 mA
0.2
0.45
VOL
IOL = 8 mA
2.3 V
0.7
0.5
0.65
±5
V
IOL = 12 mA
IOL = 24 mA
VI = 5.5 V or GND
2.7 V
3 V
II
ICC
ΔICC
Ci
3.6 V
µA
µA
mA
pF
VI = VCC or GND, IO = 0
3.6 V
10
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
1
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1)
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
3.9
MIN MAX
3.7
tpd
A
Y
1
ns
Operating Characteristics, TA = 25°C
VCC = 3.3 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
Cpd
Power dissipation capacitance per buffer/driver
f = 10 MHz
2.5
pF
Copyright © 2004–2008, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74LVC06A-Q1
SN74LVC06A-Q1
SCAS761B–FEBRUARY 2004–REVISED APRIL 2008.................................................................................................................................................. www.ti.com
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
V
LOAD
S1
Open
R
L
TEST
S1
From Output
Under Test
GND
t
(see Notes E and F)
(see Notes E and G)
V
V
V
PZL
LOAD
LOAD
LOAD
R
L
C
L
t
PLZ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
M
V
LOAD
V
∆
C
L
R
L
V
CC
V
I
t /t
r f
2.7 V
2.7 V
2.7 V
1.5 V
1.5 V
6 V
6 V
500 Ω
500 Ω
0.3 V
0.3 V
≤ 2.5 ns
≤ 2.5 ns
50 pF
50 pF
3.3 V ± 0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
PLZ
t
t
PHL
PZL
PLH
Output
Waveform 1
V
V
/2
/2
LOAD
V
V
OH
V
V
V
V
V
M
M
M
Output
V
V
+ V
∆
OL
S1 at V
LOAD
OL
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
V
LOAD
V
V
OH
- V
∆
LOAD/2
M
V
M
M
Output
S1 at V
LOAD
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t
and t are the same as t .
PZL pd
PLZ
F.
G.
t
t
is measured at V .
M
is measured at V + V .
∆
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
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Copyright © 2004–2008, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC06A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
PACKAGING INFORMATION
Status (1)
Eco Plan (2)
MSL Peak Temp (3)
Samples
Orderable Device
Package Type Package
Drawing
Pins
Package Qty
Lead/
Ball Finish
(Requires Login)
SN74LVC06AQDRG4Q1
SN74LVC06AQDRQ1
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
D
D
14
14
14
14
2500
2500
2000
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
Green (RoHS
& no Sb/Br)
CU NIPDAU Level-1-260C-UNLIM
CU NIPDAU Level-1-260C-UNLIM
SN74LVC06AQPWRG4Q1
SN74LVC06AQPWRQ1
TSSOP
TSSOP
PW
PW
Green (RoHS
& no Sb/Br)
TBD
Call TI
Call TI
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC06A-Q1 :
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
17-Aug-2012
Catalog: SN74LVC06A
•
Enhanced Product: SN74LVC06A-EP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Addendum-Page 2
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