SN74LVC07AQPWRQ1 [TI]
具有漏极开路输出的汽车类 6 通道、1.65V 至 5.5V 缓冲器 | PW | 14 | -40 to 125;
| 型号： | SN74LVC07AQPWRQ1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有漏极开路输出的汽车类 6 通道、1.65V 至 5.5V 缓冲器 | PW | 14 | -40 to 125 |
| 文件： | 总9页 (文件大小：143K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC07A-Q1
HEX BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
www.ti.com
SCAS783C–OCTOBER 2004–REVISED DECEMBER 2007
1
FEATURES
D OR PW PACKAGE
(TOP VIEW)
•
Qualified for Automotive Applications
•
•
Operates From 1.65 V to 3.6 V
Inputs and Open-Drain Outputs Accept
Voltages up to 5.5 V
•
Latch-Up Performance Exceeds 250 mA Per
JESD 17
DESCRIPTION/ORDERING INFORMATION
This hex buffer/driver is designed for 1.65-V to 3.6-V VCC operation.
The outputs of the SN74LVC07A device are open drain and can be connected to other open-drain outputs to
implement active-low wired-OR or active-high wired-AND functions. The maximum sink current is 24 mA.
Inputs can be driven from 1.8-V, 2.5-V, 3.3-V (LVTTL), or 5-V (CMOS) devices. This feature allows the use of
this device as a translator in a mixed-system environment.
ORDERING INFORMATION(1)
TA
PACKAGE(2)
Reel of 2500
Reel of 2000
ORDERABLE PART NUMBER
SN74LVC07AQDRQ1
TOP-SIDE MARKING
LVC07AQ
LVC07AQ
SOIC – D
–40°C to 125°C
TSSOP – PW
SN74LVC07AQPWRQ1
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
FUNCTION TABLE
(EACH BUFFER/DRIVER)
INPUT
A
OUTPUT
Y
H
L
H
L
LOGIC DIAGRAM, EACH BUFFER/DRIVER (POSITIVE LOGIC)
A
Y
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2004–2007, Texas Instruments Incorporated
SN74LVC07A-Q1
HEX BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
www.ti.com
SCAS783C–OCTOBER 2004–REVISED DECEMBER 2007
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX UNIT
VCC
VI
Supply voltage range
Input voltage range(2)
6.5
6.5
V
V
VO
IIK
Output voltage range
6.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
86
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
D package
θJA
Package thermal impedance(3)
Storage temperature range
°C/W
°C
PW package
113
150
Tstg
–65
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
Recommended Operating Conditions(1)
MIN
MAX UNIT
VCC
Supply voltage
1.65
3.6
V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
VIL
Low-level input voltage
0.7
0.8
5.5
5.5
4
V
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
12
IOL
Low-level output current
mA
12
24
TA
Operating free-air temperature
–40
125
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. See the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
2
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A-Q1
SN74LVC07A-Q1
HEX BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
www.ti.com
SCAS783C–OCTOBER 2004–REVISED DECEMBER 2007
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
MIN TYP(1)
MAX UNIT
0.2
IOL = 100 µA
IOL = 4 mA
0.45
VOL
2.3 V
0.7
0.4
0.65
±5
V
IOL = 12 mA
2.7 V
IOL = 24 mA
3 V
II
VI = 5.5 V or GND
3.6 V
µA
µA
µA
pF
ICC
ΔICC
Ci
VI = VCC or GND, IO = 0
3.6 V
10
One input at VCC – 0.6 V, Other inputs at VCC or GND
VI = VCC or GND
2.7 V to 3.6 V
3.3 V
500
5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
MIN MAX
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
2.9
tpd
A
Y
1
3.5
1
2.8
3
1
ns
Operating Characteristics
TA = 25°C
VCC = 1.8 V
TYP
VCC = 2.5 V
VCC = 3.3 V
TYP
TEST
CONDITIONS
PARAMETER
UNIT
TYP
Cpd
Power dissipation capacitance per buffer/driver
f = 10 MHz
1.8
2
2.5
pF
Copyright © 2004–2007, Texas Instruments Incorporated
Submit Documentation Feedback
3
Product Folder Link(s): SN74LVC07A-Q1
SN74LVC07A-Q1
HEX BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
www.ti.com
SCAS783C–OCTOBER 2004–REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × V
CC
S1
Open
GND
1 kΩ
From Output
Under Test
TEST
S1
2 × V
2 × V
2 × V
t
(see Note F)
(see Note G)
PZL
CC
C = 30 pF
(see Note A)
L
1 kΩ
t
PLZ
CC
CC
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
V
CC
V
V
CC
V
CC
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
S1 at 2 × V
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at V /2.
CC
is measured at V + 0.15 V.
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
4
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A-Q1
SN74LVC07A-Q1
HEX BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
www.ti.com
SCAS783C–OCTOBER 2004–REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
2 × V
2 × V
2 × V
t
(see Note F)
(see Note G)
PZL
CC
CC
CC
C = 30 pF
(see Note A)
L
500 Ω
t
PLZ
t
/t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PZL
PLZ
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
V
CC
V
V
CC
V
CC
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
S1 at 2 × V
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at V /2.
CC
is measured at V + 0.15 V.
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
Copyright © 2004–2007, Texas Instruments Incorporated
Submit Documentation Feedback
5
Product Folder Link(s): SN74LVC07A-Q1
SN74LVC07A-Q1
HEX BUFFER/DRIVER
WITH OPEN-DRAIN OUTPUTS
www.ti.com
SCAS783C–OCTOBER 2004–REVISED DECEMBER 2007
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 and 3.3 V ± 0.3 V
6 V
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
6 V
6 V
6 V
t
(see Note F)
(see Note G)
PZL
C = 50 pF
(see Note A)
L
t
PLZ
500 Ω
t
/t
PHZ PZH
LOAD CIRCUIT
1.5 V
t
w
2.7 V
2.7 V
0 V
1.5 V
1.5 V
Input
Timing
Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
0 V
Output
Control
(low-level
enabling)
Data
Input
2.7 V
0 V
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
S1 at 6 V
3 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
OL
+ 0.3 V
V
OL
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at 6 V
3 V
0 V
3 V
2.7 V
1.5 V
Output
1.5 V
1.5 V
V
OL
(see Note B)
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t and t are the same as t
.
pd
PLZ
PZL
F.
G.
t
t
is measured at 1.5 V.
is measured at V + 0.3 V.
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 3. Load Circuit and Voltage Waveforms
6
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Copyright © 2004–2007, Texas Instruments Incorporated
Product Folder Link(s): SN74LVC07A-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
3-Dec-2007
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SN74LVC07AQPWRQ1
ACTIVE
TSSOP
PW
14
2000
Pb-Free
(RoHS)
CU NIPDAU Level-1-250C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
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