SN74LVC125APWRG3 [TI]

具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器 | PW | 14;
SN74LVC125APWRG3
型号: SN74LVC125APWRG3
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

具有三态输出的 4 通道、1.65V 至 3.6V 缓冲器 | PW | 14

PC 驱动 光电二极管 逻辑集成电路 总线驱动器 总线收发器
文件: 总12页 (文件大小:282K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊ  
ꢋ ꢌꢊꢍꢎ ꢌꢏꢄ ꢐ ꢑꢌꢀ ꢑꢌꢒ ꢒꢐ ꢎ ꢓ ꢊꢔꢐ  
ꢕ ꢖꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚ ꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
D, DB, NS, OR PW PACKAGE  
(TOP VIEW)  
D
D
D
D
D
D
D
D
Operates From 1.65 V to 3.6 V  
Specified From −40°C to 85°C and  
−40°C to 125°C  
Inputs Accept Voltages to 5.5 V  
1
2
3
4
5
6
7
14  
13  
12  
11  
10  
9
1OE  
1A  
1Y  
2OE  
2A  
2Y  
V
CC  
4OE  
Max t of 4.8 ns at 3.3 V  
pd  
4A  
4Y  
3OE  
3A  
3Y  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
8
GND  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
Latch-Up Performance Exceeds 250 mA Per  
JESD 17  
RGY PACKAGE  
(TOP VIEW)  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
1
14  
− 1000-V Charged-Device Model (C101)  
1A  
13 4OE  
12 4A  
2
3
4
5
6
1Y  
2OE  
2A  
description/ordering information  
11  
10  
9
4Y  
3OE  
3A  
This quadruple bus buffer gate is designed for  
2Y  
1.65-V to 3.6-V V  
operation.  
CC  
7
8
The SN74LVC125A features independent line  
drivers with 3-state outputs. Each output is  
disabled when the associated output-enable (OE)  
input is high.  
To ensure the high-impedance state during power up or power down, OE should be tied to V  
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.  
through a pullup  
CC  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator  
in a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
−40°C to 85°C QFN − RGY  
Reel of 1000  
Tube of 50  
SN74LVC125ARGYR  
SN74LVC125AD  
LC125A  
Reel of 2500  
Reel of 250  
Reel of 2000  
Reel of 2000  
Tube of 90  
SN74LVC125ADR  
SN74LVC125ADT  
SN74LVC125ANSR  
SN74LVC125ADBR  
SN74LVC125APW  
SN74LVC125APWR  
SOIC − D  
SOP − NS  
LVC125A  
LVC125A  
LC125A  
−40°C to 125°C  
SSOP − DB  
Reel of 2000  
TSSOP − PW  
LC125A  
Reel of 250  
SN74LVC125APWT  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design  
guidelines are available at www.ti.com/sc/package.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢔꢦ  
Copyright 2004, Texas Instruments Incorporated  
ꢢ ꢦ ꢣ ꢢꢛ ꢜꢰ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢫ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ  
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ꢕꢖ ꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
FUNCTION TABLE  
(each buffer)  
INPUTS  
OUTPUT  
Y
OE  
A
H
L
L
L
H
L
H
X
Z
logic diagram (positive logic)  
1
10  
1OE  
3OE  
3A  
2
3
9
8
1A  
1Y  
2Y  
3Y  
4Y  
4
13  
12  
2OE  
4OE  
4A  
5
6
11  
2A  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V  
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
IK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
OK  
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous current through V  
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
CC  
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86°C/W  
JA  
(see Note 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96°C/W  
(see Note 3): NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W  
(see Note 3): PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W  
(see Note 4): RGY package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47°C/W  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Power dissipation, P (T = −40°C to 125°C) (see Notes 5 and 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 mW  
tot  
A
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The value of V is provided in the recommended operating conditions table.  
CC  
3. The package thermal impedance is calculated in accordance with JESD 51-7.  
4. The package thermal impedance is calculated in accordance with JESD 51-5.  
5. For the D package: above 70°C, the value of P derates linearly with 8 mW/K.  
tot  
6. For the DB, NS, and PW packages: above 60°C, the value of P derates linearly with 5.5 mW/K.  
tot  
2
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ꢋ ꢌꢊꢍꢎ ꢌꢏꢄ ꢐ ꢑꢌꢀ ꢑꢌꢒ ꢒꢐ ꢎ ꢓ ꢊꢔꢐ  
ꢕ ꢖꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚ ꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
recommended operating conditions (see Note 7)  
T
= 25°C  
−40 TO 85°C  
−40 TO 125°C  
A
UNIT  
MIN  
MAX  
MIN  
MAX  
MIN  
MAX  
Operating  
1.65  
1.5  
3.6  
1.65  
1.5  
3.6  
1.65  
1.5  
3.6  
V
V
Supply voltage  
V
CC  
Data retention only  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 1.65 V to 1.95 V  
= 2.3 V to 2.7 V  
= 2.7 V to 3.6 V  
= 1.65 V to 1.95 V  
= 2.3 V to 2.7 V  
= 2.7 V to 3.6 V  
0.65×V  
1.7  
0.65×V  
1.7  
0.65×V  
1.7  
CC  
CC  
CC  
High-level input  
voltage  
V
V
IH  
2
2
2
0.35×V  
0.7  
0.35×V  
0.7  
0.35×V  
0.7  
CC  
CC  
CC  
Low-level input  
voltage  
V
IL  
0.8  
0.8  
0.8  
V
V
Input voltage  
0
0
5.5  
0
0
5.5  
0
0
5.5  
V
V
I
Output voltage  
V
V
V
O
CC  
−4  
CC  
−4  
CC  
−4  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
V
CC  
= 1.65 V  
= 2.3 V  
= 2.7 V  
= 3 V  
−8  
−8  
−8  
High-level output  
current  
I
mA  
mA  
OH  
OL  
−12  
−24  
4
−12  
−24  
4
−12  
−24  
4
= 1.65 V  
= 2.3 V  
= 2.7 V  
= 3 V  
8
8
8
Low-level output  
current  
I
12  
24  
12  
24  
12  
24  
mA  
t/v Input transition rise or fall rate  
NOTE 7: All unused inputs of the device must be held at V  
8
8
8
ns/V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ  
ꢋꢌ ꢊ ꢍꢎ ꢌ ꢏꢄ ꢐ ꢑꢌ ꢀ ꢑꢌ ꢒꢒ ꢐꢎ ꢓ ꢊꢔꢐ  
ꢕꢖ ꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
T
= 25°C  
−40 TO 85°C  
MIN MAX  
−0.2  
−40 TO 125°C  
MIN MAX  
V −0.3  
CC  
A
PARAMETER  
TEST CONDITIONS  
UNIT  
V
CC  
MIN  
−0.2  
TYP  
MAX  
I
I
I
= −100 µA  
= −4 mA  
= −8 mA  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
V
V
CC  
OH  
OH  
OH  
CC  
1.29  
1.9  
2.2  
2.4  
2.3  
1.2  
1.7  
2.2  
2.4  
2.2  
1.05  
1.55  
2.05  
2.25  
2
V
V
OH  
OL  
2.7 V  
I
= −12 mA  
OH  
3 V  
I
I
I
I
I
I
= −24 mA  
= 100 µA  
= 4 mA  
3 V  
OH  
OL  
OL  
OL  
OL  
OL  
1.65 V to 3.6 V  
1.65 V  
2.3 V  
0.1  
0.24  
0.3  
0.4  
0.55  
1
0.2  
0.45  
0.7  
0.4  
0.55  
5
0.3  
0.6  
0.75  
0.6  
0.8  
20  
= 8 mA  
V
V
= 12 mA  
= 24 mA  
2.7 V  
3 V  
I
I
I
V = 5.5 V or GND  
3.6 V  
µA  
µA  
µA  
I
I
V
= V  
or GND  
or GND,  
3.6 V  
1
10  
20  
OZ  
CC  
O CC  
V = V  
CC  
I
O
= 0  
3.6 V  
1
10  
40  
I
One input at V  
Other inputs at V  
GND  
− 0.6 V,  
CC  
I  
CC  
or  
2.7 V to 3.6 V  
3.3 V  
500  
500  
5000  
µA  
CC  
C
V = V  
I CC  
or GND  
5
pF  
i
switching characteristics over recommended operating free-air temperature range (unless  
otherwise noted) (see Figure 1)  
T
A
= 25°C  
TYP  
4.5  
2.7  
3
−40 TO 85°C −40 TO 125°C  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
V
UNIT  
CC  
MIN  
1
MAX  
11.8  
5.8  
MIN  
1
MAX  
12.3  
6.3  
5.5  
4.8  
14.3  
7.4  
6.6  
5.4  
11.1  
5.6  
5
MIN  
1
MAX  
13.8  
8.4  
7
1.8 V 0.15 V  
2.5 V 0.2 V  
2.7 V  
1
1
1
Y
Y
Y
t
A
ns  
pd  
en  
1
5.3  
1
1
1
2.5  
4.3  
2.7  
3.3  
2.4  
4.3  
2.2  
2.5  
2.4  
4.6  
1
1
6
3.3 V 0.3 V  
1.8 V 0.15 V  
2.5 V 0.2 V  
2.7 V  
1
13.8  
6.9  
1
1
15.8  
9.5  
8.5  
7
1
1
1
t
OE  
OE  
ns  
1
6.4  
1
1
1
5.2  
1
1
3.3 V 0.3 V  
1.8 V 0.15 V  
2.5 V 0.2 V  
2.7 V  
1
10.6  
5.1  
1
1
12.6  
7.7  
6.5  
6
1
1
1
t
t
ns  
ns  
dis  
1
4.8  
1
1
1
4.4  
1
4.6  
1
1
3.3 V 0.3 V  
3.3 V 0.3 V  
1.5  
sk(o)  
4
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ꢕ ꢖꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚ ꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
operating characteristics, T = 25°C  
A
TEST  
CONDITIONS  
PARAMETER  
V
CC  
TYP  
UNIT  
1.8 V  
2.5 V  
3.3 V  
7.4  
11.3  
15  
C
Power dissipation capacitance per gate  
f = 10 MHz  
pF  
pd  
5
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ꢕꢖ ꢔ ꢗ ꢘ ꢙꢀꢔꢊꢔ ꢐ ꢚꢌꢔ ꢏ ꢌꢔꢀ  
SCAS290N − JANUARY 1993 − REVISED FEBRUARY 2004  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
Open  
S1  
R
L
From Output  
Under Test  
TEST  
S1  
GND  
t
t
/t  
Open  
PLH PHL  
/t  
C
L
t
V
R
PLZ PZL  
LOAD  
GND  
L
(see Note A)  
/t  
PHZ PZH  
LOAD CIRCUIT  
INPUTS  
V
CC  
V
M
V
C
R
L
V
LOAD  
L
V
I
t /t  
r f  
1.8 V 0.15 V  
2.5 V 0.2 V  
2.7 V  
V
V
2 ns  
2 ns  
2.5 ns  
2.5 ns  
V
V
/2  
/2  
2 × V  
2 × V  
6 V  
30 pF  
30 pF  
50 pF  
50 pF  
1 kΩ  
500 Ω  
500 Ω  
500 Ω  
0.15 V  
0.15 V  
0.3 V  
CC  
CC  
CC  
CC  
CC  
CC  
2.7 V  
2.7 V  
1.5 V  
1.5 V  
3.3 V 0.3 V  
6 V  
0.3 V  
V
I
Timing Input  
Data Input  
V
M
0 V  
t
w
t
t
su  
h
V
I
V
I
Input  
V
M
V
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
I
V
I
Output  
Control  
V
M
V
M
Input  
V
M
V
M
0 V  
V
0 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
+ V  
PLH  
PHL  
Output  
Waveform 1  
V
/2  
OH  
LOAD  
V
V
V
M
Output  
M
V
V
M
S1 at V  
(see Note B)  
V
LOAD  
OL  
V
OL  
V
OL  
t
PLH  
t
t
PZH  
PHZ  
− V  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
V
OH  
V
V
M
OH  
M
Output  
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
PHL  
are the same as t  
.
dis  
PLZ  
PZL  
PLH  
PHZ  
PZH  
are the same as t  
.
en  
are the same as t .  
pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001  
D (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
8 PINS SHOWN  
0.020 (0,51)  
0.014 (0,35)  
0.050 (1,27)  
8
0.010 (0,25)  
5
0.244 (6,20)  
0.228 (5,80)  
0.008 (0,20) NOM  
0.157 (4,00)  
0.150 (3,81)  
Gage Plane  
1
4
0.010 (0,25)  
0°– 8°  
A
0.044 (1,12)  
0.016 (0,40)  
Seating Plane  
0.010 (0,25)  
0.069 (1,75) MAX  
0.004 (0,10)  
0.004 (0,10)  
PINS **  
8
14  
16  
DIM  
A MAX  
0.197  
(5,00)  
0.344  
(8,75)  
0.394  
(10,00)  
0.189  
(4,80)  
0.337  
(8,55)  
0.386  
(9,80)  
A MIN  
4040047/E 09/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).  
D. Falls within JEDEC MS-012  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001  
DB (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE  
28 PINS SHOWN  
0,38  
0,22  
0,65  
28  
M
0,15  
15  
0,25  
0,09  
5,60  
5,00  
8,20  
7,40  
Gage Plane  
1
14  
0,25  
A
0°ā8°  
0,95  
0,55  
Seating Plane  
0,10  
2,00 MAX  
0,05 MIN  
PINS **  
14  
16  
20  
24  
28  
30  
38  
DIM  
6,50  
5,90  
6,50  
5,90  
7,50  
8,50  
7,90  
10,50  
9,90  
10,50 12,90  
A MAX  
A MIN  
6,90  
9,90  
12,30  
4040065 /E 12/01  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-150  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
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any product or service without notice. Customers should obtain the latest relevant information before placing  
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and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
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www.ti.com/digitalcontrol  
www.ti.com/military  
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Logic  
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logic.ti.com  
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Microcontrollers  
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Security  
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www.ti.com/security  
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