SN74LVC137AD [TI]
LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, PLASTIC, SOIC-16;
| 型号： | SN74LVC137AD |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, PLASTIC, SOIC-16 驱动 光电二极管 输出元件 |
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SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
FEATURES
D, DB, OR PW PACKAGE
(TOP VIEW)
•
•
•
EPIC™ (Enhanced-Performance Implanted
CMOS) Submicron Process
V
CC
Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
A
B
1
2
3
4
5
6
7
8
16
15
14
13
12
11
Y0
Y1
Y2
Y3
Y4
C
Typical VOHV (Output VOH Undershoot)
G2A
G2B
G1
> 2 V at VCC = 3.3 V, TA = 25°C
•
•
Inputs Accept Voltages to 5.5 V
Package Options Include Plastic
10 Y5
Y7
Small-Outline (D), Shrink Small-Outline (DB),
and Thin Shrink Small-Outline (PW) Packages
9
Y6
GND
DESCRIPTION
This 3-line to 8-line decoder/demultiplexer, with latches on three address inputs, is designed for 1.65-V to 3.6-V
VCC operation.
The SN74LVC137A is designed for high-performance memory-decoding or data-routing applications requiring
very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize
the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the
delay times of this decoder and the enable time of the memory usually are less than the typical access time of
the memory. This means that the effective system delay introduced by the decoder is negligible.
When the latch-enable (G2A) input is low, the SN74LVC137A acts as a decoder/demultiplexer. When G2A
transitions from low to high, the address present at the inputs (A, B, and C) is stored in the latches. Further
address changes are ignored, provided G2A remains high. The output-enable (G1 and G2B) inputs control the
outputs independently of the select or latch-enable inputs. All of the outputs are forced high if G1 is low or G2B is
high.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators
in a mixed 3.3-V/5-V system environment.
The SN74LVC137A is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
INPUTS
OUTPUTS
Y3 Y4
LATCH
ENABLE
OUTPUT
ENABLE
SELECT
G2A
X
X
L
G1
G2B
H
X
L
C
X
X
L
B
X
X
L
A
X
X
L
Y0
H
H
L
Y1
H
H
H
L
Y2
H
H
H
H
L
Y5
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
L
X
L
H
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
H
L
L
L
L
H
L
H
H
H
H
H
H
H
L
L
L
H
H
L
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
L
L
H
H
H
H
X
H
H
H
H
L
L
L
H
L
H
H
H
L
L
H
H
X
H
H
L
L
H
X
H
H
L
Outputs corresponding to stored address = L; all other outputs = H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments.
PRODUCT PREVIEW information concerns products in the forma-
Copyright © 1994–2005, Texas Instruments Incorporated
tive or design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the
right to change or discontinue these products without notice.
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
LOGIC SYMBOLS (ALTERNATIVES)(1)
BIN/OCT
DMUX
15
14
13
12
11
10
9
15
Y0
1
2
3
1
2
3
0
1
2
3
4
5
6
7
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
0
1
2
3
4
5
6
7
A
B
C
1
2
4
A
B
C
0
2
14
0
G
Y1
13
Y2
7
12
Y3
&
&
6
4
6
4
11
G1
G1
Y4
EN
10
G2A
G2A
Y5
9
Y6
5
7
5
7
Y7
G2B
G2B
(1) These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM (POSITIVE LOGIC)
15
14
1
Y0
Y1
A
13
12
11
Y2
2
Select
Inputs
B
Y3
Y4
Data
Outputs
3
4
C
10
9
Y5
Y6
Latch
Enable
G2A
7
Y7
5
6
G2B
G1
Output
Enables
2
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
6.5
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Output voltage range(2)(3)
6.5
V
VO
IIK
VCC + 0.5
–50
V
Input clamp current
VI < 0
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
–50
Continuous output current
Continuous current through VCC or GND
±50
±100
113
D package
θJA
Package thermal impedance(4)
DB package
PW package
131
°C/W
°C
149
Tstg
Storage temperature range
–65
150
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The value of VCC is provided in the recommended operating conditions table.
(4) The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
MIN
MAX UNIT
Operating
1.65
3.6
V
VCC Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
1.5
0.65 × VCC
VIH
High-level input voltage
1.7
2
V
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
5.5
VCC
–4
VI
Input voltage
0
0
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
–8
IOH
High-level output current
Low-level output current
mA
mA
–12
–24
4
VCC = 1.65 V
VCC = 2.3 V
VCC = 2.7 V
VCC = 3 V
8
IOL
12
24
∆t/∆v Input transition rise or fall rate
TA Operating free-air temperature
0
10
ns/V
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 3.6 V
1.65 V
2.3 V
MIN TYP(1) MAX UNIT
IOH = –100 µA
IOH = –4 mA
IOH = –8 mA
VCC – 0.2
1.2
1.7
2.2
2.4
2.2
VOH
V
V
2.7 V
IOH = –12 mA
3 V
IOH = –24 mA
IOL = 100 µA
IOL = 4 mA
3 V
1.65 V to 3.6 V
1.65 V
2.3 V
0.2
0.45
0.7
VOL
IOL = 8 mA
IOL = 12 mA
2.7 V
0.4
IOL = 24 mA
3 V
0.55
±5
II
VI = 5.5 V or GND
VI = VCC or GND,
3.6 V
µA
µA
ICC
IO = 0
3.6 V
10
One input at VCC – 0.6 V,
Other inputs at VCC or GND
∆ICC
2.7 V to 3.6 V
500
µA
Ci
VI = VCC or GND
VO = VCC or GND
3.3 V
3.3 V
pF
pF
Co
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 1 through Figure 3)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 2.7 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
A or B or C
G2A or G2B
G1
tpd
Y
ns
ns
(1)
tsk(o)
(1) Skew between any two outputs of the same package switching in the same direction
Operating Characteristics
TA = 25°C
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
TEST
CONDITIONS
PARAMETER
UNIT
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
pF
4
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 1.8 V ± 0.15 V
2 × V
CC
S1
Open
GND
1k Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
Open
PLZ PZL
1k Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 1. Load Circuit and Voltage Waveforms
5
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.5 V ± 0.2 V
2 × V
CC
S1
Open
GND
500 Ω
From Output
Under Test
TEST
S1
t
pd
Open
C = 30 pF
(see Note A)
L
t
/t
/t
2 × V
CC
GND
PLZ PZL
500 Ω
t
PHZ PZH
LOAD CIRCUIT
t
w
V
CC
V
CC
V /2
CC
V /2
CC
Input
Timing
Input
V
/2
CC
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
V
CC
Output
Control
(low-level
enabling)
Data
Input
V
CC
V
/2
CC
V /2
CC
V /2
CC
V /2
CC
0 V
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
t
PLZ
PZL
Output
Waveform 1
V
CC
V
CC
V /2
CC
Input
V /2
CC
V /2
CC
S1 at 2 × V
V
OL
+ 0.15 V
CC
V
OL
(see Note B)
0 V
t
t
PHZ
PZH
t
t
PLH
PHL
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
− 0.15 V
V /2
CC
Output
V /2
CC
V /2
CC
0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2 ns, t ≤ 2 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 2. Load Circuit and Voltage Waveforms
6
SN74LVC137A
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
WITH ADDRESS LATCHES
www.ti.com
SCAS340E–MARCH 1994–REVISED FEBRUARY 2005
PARAMETER MEASUREMENT INFORMATION
VCC = 2.7 V AND 3.3 V ± 0.3 V
6 V
TEST
S1
S1
500 Ω
Open
t
Open
6 V
GND
pd
From Output
Under Test
t
t
/t
/t
PLZ PZL
GND
PHZ PZH
C = 50 pF
(see Note A)
L
500 Ω
t
w
LOAD CIRCUIT
1.5 V
2.7 V
0 V
1.5 V
1.5 V
Input
2.7 V
Timing
Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
t
su
t
h
2.7 V
Data
Input
2.7 V
0 V
1.5 V
1.5 V
Output
Control
(low-level
enabling)
0 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
t
PZL
t
PLZ
3 V
Output
Waveform 1
S1 at 6 V
2.7 V
0 V
1.5 V
Input
1.5 V
1.5 V
V
V
+ 0.3 V
− 0.3 V
OL
V
OL
OH
(see Note B)
t
t
PHZ
PZH
t
t
PHL
PLH
Output
Waveform 2
S1 at GND
V
V
OH
OH
1.5 V
Output
1.5 V
1.5 V
(see Note B)
0 V
V
OL
VOLTAGE WAVEFORMS
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
ENABLE AND DISABLE TIMES
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
.
dis
.
PLZ
PZL
PLH
PHZ
are the same as t
PZH
en
are the same as t .
PHL pd
Figure 3. Load Circuit and Voltage Waveforms
7
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相关型号：
SN74LVC137APWR
LVC/LCX/Z SERIES, OTHER DECODER/DRIVER, INVERTED OUTPUT, PDSO16, PLASTIC, TSSOP-16
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