SN74LVC138AQDRG4Q1 [TI]
汽车类 3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 125;
| 型号： | SN74LVC138AQDRG4Q1 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 汽车类 3 线至 8 线解码器/多路解复用器 | D | 16 | -40 to 125 驱动 输入元件 光电二极管 逻辑集成电路 复用器 解复用器 解码器 驱动器 |
| 文件： | 总8页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢉ ꢊꢋ ꢌ ꢇ
ꢈ ꢋꢄ ꢍꢁꢎ ꢏ ꢐ ꢉ ꢋꢄ ꢍꢁꢎ ꢑꢎꢆ ꢐꢑ ꢎꢒꢓ ꢑꢎꢔ ꢕꢄꢏꢍ ꢖ ꢄꢎ ꢗꢎ ꢒ
SCAS708A − SEPTEMBER 2003 − REVISED MAY 2004
D
Qualification in Accordance With
AEC-Q100
D
Typical V
(Output V
= 3.3 V, T = 25°C
Undershoot)
OHV
OH
†
>2 V at V
CC A
D
Qualified for Automotive Applications
D OR PW PACKAGE
(TOP VIEW)
D
Customer-Specific Configuration Control
Can Be Supported Along With
Major-Change Approval
1
2
3
4
5
6
7
8
16
15
14
V
Y0
Y1
A
B
C
CC
D
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
13 Y2
12
G2A
G2B
G1
Y7
GND
Y3
D
D
D
D
Operates From 2 V to 3.6 V
11 Y4
10 Y5
Inputs Accept Voltages to 5.5 V
Max t of 5.8 ns at 3.3 V
pd
9
Y6
Typical V
<0.8 V at V
(Output Ground Bounce)
OLP
CC
= 3.3 V, T = 25°C
A
†
Contact factory for details. Q100 qualification data available on
request.
description/ordering information
The SN74LVC138A 3-line to 8-line decoder/demultiplexer is designed for 2.7-V to 3.6-V V
operation.
CC
The device is designed for high-performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high-performance memory systems, this decoder minimizes the effects of
system decoding. When employed with high-speed memories utilizing a fast enable circuit, delay times of this
decoder and the enable time of the memory usually are less than the typical access time of the memory. This
means that the effective system delay introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two
active-low enable inputs and one active-high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires
only one inverter. An enable input can be used as a data input for demultiplexing applications.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator
in a mixed 3.3-V/5-V system environment.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
‡
PACKAGE
T
A
SOIC − D
Reel of 2500
Reel of 2000
SN74LVC138AQDRQ1
SN74LVC138AQPWRQ1
L138AQ1
L138AQ1
−40°C to 125°C
TSSOP − PW
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available
at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 2004, Texas Instruments Incorporated
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢋꢌꢇ
ꢈꢋ ꢄ ꢍ ꢁꢎ ꢏꢐ ꢉ ꢋꢄ ꢍ ꢁ ꢎ ꢑꢎ ꢆꢐ ꢑꢎ ꢒꢓ ꢑ ꢎꢔ ꢕꢄꢏꢍ ꢖ ꢄꢎ ꢗꢎꢒ
SCAS708A − SEPTEMBER 2003 − REVISED MAY 2004
FUNCTION TABLE
ENABLE INPUTS
SELECT INPUTS
OUTPUTS
G1
G2A
H
X
X
L
G2B
C
X
X
X
L
B
X
X
X
L
A
Y0
H
H
H
L
Y1
H
H
H
H
L
Y2
H
H
H
H
H
L
Y3
H
H
H
H
H
H
L
Y4
H
H
H
H
H
H
H
L
Y5
H
H
H
H
H
H
H
H
L
Y6
H
H
H
H
H
H
H
H
H
L
Y7
H
H
H
H
H
H
H
H
H
H
L
X
X
L
X
H
X
L
L
L
L
L
L
L
L
X
X
X
L
H
H
H
H
H
H
H
H
L
L
L
H
L
H
H
H
H
H
H
H
L
L
H
H
L
H
H
H
H
H
H
L
L
H
L
H
H
H
H
H
L
H
H
H
H
H
H
H
H
L
L
H
L
H
H
H
L
H
H
H
H
L
H
H
logic diagram (positive logic)
15
14
13
12
11
10
9
Y0
Y1
1
A
2
3
Select
Inputs
B
C
Y2
Y3
Y4
Y5
Y6
Data
Outputs
6
G1
4
5
Enable
Inputs
7
G2A
G2B
Y7
2
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SCAS708A − SEPTEMBER 2003 − REVISED MAY 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Continuous current through V
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
JA
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
recommended operating conditions (see Note 4)
MIN
2
MAX
UNIT
Operating
3.6
V
Supply voltage
V
CC
Data retention only
1.5
2
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
V
V
V
V
IH
IL
I
CC
0.8
5.5
CC
0
0
Output voltage
V
CC
O
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
−12
−24
12
I
High-level output current
Low-level output current
mA
mA
OH
= 2.7 V
= 3 V
I
OL
24
∆t/∆v Input transition rise or fall rate
Operating free-air temperature
NOTE 4: All unused inputs of the device must be held at V
10
ns/V
T
A
−40
125
°C
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢉ ꢊ ꢋꢌꢇ
ꢈꢋ ꢄ ꢍ ꢁꢎ ꢏꢐ ꢉ ꢋꢄ ꢍ ꢁ ꢎ ꢑꢎ ꢆꢐ ꢑꢎ ꢒꢓ ꢑ ꢎꢔ ꢕꢄꢏꢍ ꢖ ꢄꢎ ꢗꢎꢒ
SCAS708A − SEPTEMBER 2003 − REVISED MAY 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
MIN
V −0.2
CC
TYP
MAX
UNIT
V
CC
I
I
= −100 µA
2.7 V to 3.6 V
2.7 V
OH
2.2
2.4
2.2
V
= −12 mA
V
OH
OH
3 V
I
I
I
I
= −24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
2.7 V to 3.6 V
2.7 V
0.2
0.4
0.55
5
V
V
OL
3 V
I
I
V = 5.5 V or GND
3.6 V
µA
µA
µA
pF
I
I
V = V
CC
or GND,
I = 0
O
3.6 V
10
CC
I
∆I
CC
One input at V
CC
− 0.6 V, Other inputs at V
or GND
2.7 V to 3.6 V
3.3 V
500
CC
C
V = V
or GND
5
i
I
CC
CC
†
All typical values are at V
= 3.3 V, T = 25°C.
A
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figure 1)
V
= 3.3 V
CC
0.3 V
V
= 2.7 V
CC
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
7.9
MIN
MAX
6.7
A or B or C
G2A or G2B
G1
1
1
1
7.4
6.5
t
Y
ns
pd
6.4
5.8
operating characteristics, T = 25°C
A
V
CC
= 2.5 V
TYP
26
V = 3.3 V
CC
TEST
CONDITIONS
PARAMETER
UNIT
TYP
C
Power dissipation capacitance
f = 10 MHz
27
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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SCAS708A − SEPTEMBER 2003 − REVISED MAY 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
2.7 V
V
V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
2.7 V
2.7 V
1.5 V
1.5 V
3.3 V 0.3 V
6 V
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999
PW (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
14 PINS SHOWN
0,30
0,19
M
0,10
0,65
14
8
0,15 NOM
4,50
4,30
6,60
6,20
Gage Plane
0,25
1
7
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
8
14
16
20
24
28
DIM
3,10
2,90
5,10
4,90
5,10
4,90
6,60
6,40
7,90
9,80
9,60
A MAX
A MIN
7,70
4040064/F 01/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74LVC138PW
8-BIT DUAL-SUPPLY BUS TRANSCEIVER WITH CONFIGURABLE VOLTAGE TRANSLATION AND 3-STATE OUTPUTS
TI
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