SN74LVC157AQDREP [TI]

QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER;
SN74LVC157AQDREP
型号: SN74LVC157AQDREP
厂家: TEXAS INSTRUMENTS    TEXAS INSTRUMENTS
描述:

QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER

文件: 总8页 (文件大小:423K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢂ ꢉꢊ ꢋꢌ  
ꢍ ꢎꢉꢏ ꢐ ꢎꢌꢄ ꢋ ꢑ ꢊꢄ ꢒꢁꢋ ꢓ ꢔ ꢇ ꢊꢄ ꢒꢁꢋ ꢏꢉꢓꢉ ꢀꢋ ꢄꢋ ꢆꢓꢔ ꢐꢕꢖ ꢎꢄꢓꢒ ꢌ ꢄꢋ ꢗꢋ ꢐ  
SCAS735A − NOVEMBER 2003 − REVISED MAY 2004  
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
D
Operates From 2 V to 3.6 V  
Inputs Accept Voltages to 5.5 V  
Max t of 5.4 ns at 3.3 V  
pd  
D
D
D
D
D
Extended Temperature Performance of  
−40°C to 125°C  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
= 3.3 V, T = 25°C  
A
D
Typical V  
(Output V  
Undershoot)  
OHV  
OH  
>2 V at V  
= 3.3 V, T = 25°C  
CC  
A
Enhanced Product-Change Notification  
D OR PW PACKAGE  
(TOP VIEW)  
Qualification Pedigree  
ESD Protection Exceeds 2000 V Per  
MIL-STD-883, Method 3015; Exceeds 200 V  
Using Machine Model (C = 200 pF, R = 0)  
1
2
3
4
5
6
7
8
16  
15  
14  
13  
12  
11  
10  
9
V
G
A/B  
1A  
1B  
1Y  
2A  
2B  
2Y  
CC  
4A  
4B  
4Y  
3A  
3B  
3Y  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
GND  
description/ordering information  
The SN74LVC157A-EP quadruple 2-line to 1-line data selector/multiplexer is designed for 2.7-V to 3.6-V V  
operation.  
CC  
This device features a common strobe (G) input. When G is high, all outputs are low. When G is low, a 4-bit word  
is selected from one of two sources and is routed to the four outputs. The device provides true data.  
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of this device as a translator  
in a mixed 3.3-V/5-V system environment.  
ORDERING INFORMATION  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
PACKAGE  
T
A
SOIC − D  
Tape and reel  
Tape and reel  
SN74LVC157AQDREP  
SN74LVC157AQPWREP  
C157AEP  
C157AEP  
−40°C to 125°C  
TSSOP − PW  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are  
available at www.ti.com/sc/package.  
FUNCTION TABLE  
INPUTS  
OUTPUT  
Y
G
H
L
A/B  
X
A
X
L
B
X
X
X
L
L
L
L
L
L
H
X
X
H
L
L
H
L
H
H
H
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
ꢓꢣ  
Copyright 2004, Texas Instruments Incorporated  
ꢟ ꢣ ꢠ ꢟꢘ ꢙꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟ ꢣ ꢜ ꢠ ꢨ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢂ ꢉ ꢊꢋꢌ  
ꢍꢎ ꢉ ꢏꢐ ꢎ ꢌꢄ ꢋ ꢑ ꢊꢄ ꢒ ꢁꢋ ꢓ ꢔ ꢇ ꢊꢄꢒ ꢁ ꢋ ꢏꢉꢓꢉ ꢀꢋ ꢄꢋ ꢆꢓꢔ ꢐꢕꢖ ꢎꢄꢓ ꢒꢌ ꢄꢋ ꢗꢋꢐ  
SCAS735A − NOVEMBER 2003 − REVISED MAY 2004  
logic diagram (positive logic)  
2
1A  
4
1Y  
2Y  
3Y  
4Y  
3
1B  
5
2A  
7
9
6
2B  
11  
3A  
10  
3B  
14  
4A  
12  
13  
4B  
15  
G
1
A/B  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage range, V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V  
CC  
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V  
I
Output voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V  
+ 0.5 V  
O
CC  
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
IK  
I
Output clamp current, I  
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA  
OK  
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA  
Continuous current through V  
O
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA  
CC  
Package thermal impedance, θ (see Note 3): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W  
JA  
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108°C/W  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
Storage temperature range, T  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.  
2. The value of V is provided in the recommended operating conditions table.  
CC  
3. The package thermal impedance is calculated in accordance with JESD 51-7.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀꢁꢂ ꢃ ꢄꢅ ꢆꢇ ꢈꢂ ꢉꢊ ꢋꢌ  
ꢍ ꢎꢉꢏ ꢐ ꢎꢌꢄ ꢋ ꢑ ꢊꢄ ꢒꢁꢋ ꢓ ꢔ ꢇ ꢊꢄ ꢒꢁꢋ ꢏꢉꢓꢉ ꢀꢋ ꢄꢋ ꢆꢓꢔ ꢐꢕꢖ ꢎꢄꢓꢒ ꢌ ꢄꢋ ꢗꢋ ꢐ  
SCAS735A − NOVEMBER 2003 − REVISED MAY 2004  
recommended operating conditions (see Note 4)  
MIN  
2
MAX  
UNIT  
Operating  
3.6  
V
Supply voltage  
V
CC  
Data retention only  
1.5  
2
V
V
V
V
High-level input voltage  
Low-level input voltage  
Input voltage  
V
V
= 2.7 V to 3.6 V  
= 2.7 V to 3.6 V  
V
V
V
V
IH  
IL  
I
CC  
0.8  
5.5  
CC  
0
0
Output voltage  
V
CC  
O
V
CC  
V
CC  
V
CC  
V
CC  
= 2.7 V  
= 3 V  
−12  
−24  
12  
I
High-level output current  
Low-level output current  
mA  
mA  
OH  
= 2.7 V  
= 3 V  
I
OL  
24  
t/v  
Input transition rise or fall rate  
Operating free-air temperature  
10  
ns/V  
T
A
−40  
125  
°C  
NOTE 4: All unused inputs of the device must be held at V  
or GND to ensure proper device operation. Refer to the TI application report,  
CC  
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.  
electrical characteristics over recommended operating free-air temperature range (unless  
otherwise noted)  
PARAMETER  
TEST CONDITIONS  
MIN  
V −0.2  
CC  
MAX  
UNIT  
V
CC  
I
I
= −100 µA  
2.7 V to 3.6 V  
2.7 V  
OH  
2.2  
2.4  
2.2  
V
= −12 mA  
V
OH  
OL  
OH  
3 V  
I
I
I
I
= −24 mA  
= 100 µA  
= 12 mA  
= 24 mA  
3 V  
OH  
OL  
OL  
OL  
2.7 V to 3.6 V  
2.7 V  
0.2  
0.4  
0.55  
5
V
V
3 V  
I
I
All inputs  
V = 5.5 V or GND  
3.6 V  
µA  
µA  
µA  
I
I
V = V  
CC  
or GND,  
I = 0  
O
3.6 V  
10  
CC  
I
I  
CC  
One input at V  
CC  
− 0.6 V, Other inputs at V  
or GND  
2.7 V to 3.6 V  
500  
CC  
switching characteristics over recommended operating free-air temperature range (unless  
otherwise noted) (see Figure 1)  
V
= 3.3 V  
CC  
0.3 V  
V
= 2.7 V  
CC  
FROM  
(INPUT)  
TO  
(OUTPUT)  
PARAMETER  
UNIT  
MIN  
MAX  
6.2  
MIN  
MAX  
5.4  
7
A or B  
A/B  
G
0.8  
0.8  
0.8  
8.2  
t
pd  
Y
ns  
7.8  
6.5  
operating characteristics, T = 25°C  
A
V
CC  
= 2.5 V  
TYP  
15  
V
CC  
= 3.3 V  
TEST  
CONDITIONS  
PARAMETER  
UNIT  
TYP  
C
Power dissipation capacitance  
f = 10 MHz  
16  
pF  
pd  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃꢄꢅꢆ ꢇ ꢈꢂ ꢉ ꢊꢋꢌ  
ꢍꢎ ꢉ ꢏꢐ ꢎ ꢌꢄ ꢋ ꢑ ꢊꢄ ꢒ ꢁꢋ ꢓ ꢔ ꢇ ꢊꢄꢒ ꢁ ꢋ ꢏꢉꢓꢉ ꢀꢋ ꢄꢋ ꢆꢓꢔ ꢐꢕꢖ ꢎꢄꢓ ꢒꢌ ꢄꢋ ꢗꢋꢐ  
SCAS735A − NOVEMBER 2003 − REVISED MAY 2004  
PARAMETER MEASUREMENT INFORMATION  
V
LOAD  
Open  
S1  
R
L
From Output  
Under Test  
TEST  
S1  
GND  
t
t
/t  
Open  
PLH PHL  
/t  
C
L
t
V
R
PLZ PZL  
LOAD  
GND  
L
(see Note A)  
/t  
PHZ PZH  
LOAD CIRCUIT  
INPUTS  
V
CC  
V
M
V
C
R
L
V
LOAD  
L
V
I
t /t  
r f  
2.7 V  
2.7 V  
2.7 V  
2.5 ns  
2.5 ns  
1.5 V  
1.5 V  
6 V  
6 V  
50 pF  
50 pF  
500 Ω  
500 Ω  
0.3 V  
0.3 V  
3.3 V 0.3 V  
V
I
Timing Input  
Data Input  
V
M
0 V  
t
w
t
t
su  
h
V
I
V
I
Input  
V
M
V
M
V
M
V
M
0 V  
0 V  
VOLTAGE WAVEFORMS  
PULSE DURATION  
VOLTAGE WAVEFORMS  
SETUP AND HOLD TIMES  
V
I
V
I
Output  
Control  
V
M
V
M
Input  
V
M
V
M
0 V  
V
0 V  
t
t
t
t
t
PHL  
PZL  
PLZ  
+ V  
PLH  
PHL  
Output  
Waveform 1  
V
/2  
OH  
LOAD  
V
V
V
M
Output  
M
V
V
M
S1 at V  
(see Note B)  
V
LOAD  
OL  
V
OL  
V
OL  
t
PLH  
t
t
PZH  
PHZ  
− V  
Output  
Waveform 2  
S1 at GND  
V
V
OH  
V
OH  
V
V
M
OH  
M
Output  
M
0 V  
OL  
(see Note B)  
VOLTAGE WAVEFORMS  
PROPAGATION DELAY TIMES  
INVERTING AND NONINVERTING OUTPUTS  
VOLTAGE WAVEFORMS  
ENABLE AND DISABLE TIMES  
LOW- AND HIGH-LEVEL ENABLING  
NOTES: A. includes probe and jig capacitance.  
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.  
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.  
C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, Z = 50 .  
O
D. The outputs are measured one at a time, with one transition per measurement.  
E.  
F.  
G.  
t
t
t
and t  
and t  
and t  
PHL  
are the same as t  
.
dis  
PLZ  
PZL  
PLH  
PHZ  
PZH  
are the same as t  
.
en  
are the same as t .  
pd  
H. All parameters and waveforms are not applicable to all devices.  
Figure 1. Load Circuit and Voltage Waveforms  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
PACKAGE OPTION ADDENDUM  
www.ti.com  
18-Sep-2008  
PACKAGING INFORMATION  
Orderable Device  
SN74LVC157AQDREP  
SN74LVC157AQPWREP  
V62/04659-01XE  
Status (1)  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
Package Package  
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)  
Qty  
Type  
Drawing  
SOIC  
D
16  
16  
16  
16  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
TSSOP  
SOIC  
PW  
D
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
V62/04659-01YE  
TSSOP  
PW  
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM  
no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in  
a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2)  
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check  
http://www.ti.com/productcontent for the latest availability information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements  
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered  
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and  
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS  
compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame  
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)  
(3)  
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder  
temperature.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is  
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the  
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take  
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on  
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited  
information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI  
to Customer on an annual basis.  
OTHER QUALIFIED VERSIONS OF SN74LVC157A-EP :  
Catalog: SN74LVC157A  
Automotive: SN74LVC157A-Q1  
Military: SN54LVC157A  
NOTE: Qualified Version Definitions:  
Catalog - TI's standard catalog product  
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects  
Military - QML certified for Military and Defense Applications  
Addendum-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
SN74LVC157AQDREP  
SOIC  
D
16  
16  
2500  
2000  
330.0  
330.0  
16.4  
12.4  
6.5  
6.9  
10.3  
5.6  
2.1  
1.6  
8.0  
8.0  
16.0  
12.0  
Q1  
Q1  
SN74LVC157AQPWREP TSSOP  
PW  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
14-Jul-2012  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
SN74LVC157AQDREP  
SN74LVC157AQPWREP  
SOIC  
D
16  
16  
2500  
2000  
333.2  
367.0  
345.9  
367.0  
28.6  
35.0  
TSSOP  
PW  
Pack Materials-Page 2  
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