概述
规格参数
数据手册SN74LVC1G139YEPR 概述
2-TO -4 LINE DECODER 2 -TO -4线译码器 解码器/驱动器
SN74LVC1G139YEPR 规格参数
| 生命周期： | Obsolete | 零件包装代码： | BGA |
| 包装说明： | VFBGA, BGA8,2X4,20 | 针数： | 8 |
| Reach Compliance Code： | unknown | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.65 |
| 其他特性： | TXIIK01155 | 系列： | LVC/LCX/Z |
| 输入调节： | STANDARD | JESD-30 代码： | R-XBGA-B8 |
| 长度： | 1.9 mm | 负载电容（CL）： | 50 pF |
| 逻辑集成电路类型： | OTHER DECODER/DRIVER | 最大I（ol）： | 0.024 A |
| 功能数量： | 1 | 端子数量： | 8 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出特性： | 3-STATE | 输出极性： | INVERTED |
| 封装主体材料： | UNSPECIFIED | 封装代码： | VFBGA |
| 封装等效代码： | BGA8,2X4,20 | 封装形状： | RECTANGULAR |
| 封装形式： | GRID ARRAY, VERY THIN PROFILE, FINE PITCH | 包装方法： | TAPE AND REEL |
| 电源： | 3.3 V | Prop。Delay @ Nom-Sup： | 5.9 ns |
| 传播延迟（tpd）： | 16.7 ns | 认证状态： | Not Qualified |
| 座面最大高度： | 0.5 mm | 子类别： | Decoder/Drivers |
| 最大供电电压 (Vsup)： | 5.5 V | 最小供电电压 (Vsup)： | 1.65 V |
| 标称供电电压 (Vsup)： | 1.8 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子形式： | BALL | 端子节距： | 0.5 mm |
| 端子位置： | BOTTOM | 宽度： | 0.9 mm |
SN74LVC1G139YEPR 数据手册
通过下载SN74LVC1G139YEPR数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢉ ꢊ
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SCES602 − AUGUST 2004
DCT OR DCU PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
D
D
Supports 5-V V
Operation
CC
V
1
2
3
4
8
7
6
5
A
B
CC
Inputs Accept Voltages to 5.5 V
Y0
Y1
Y2
Y3
GND
Max t of 4.9 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
24-mA Output Drive at 3.3 V
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
I
Supports Partial-Power-Down Mode
off
Operation
4 5
3 6
2 7
1 8
GND
Y3
B
Y2
Y1
Y0
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
A
V
CC
description/ordering information
This 2-to-4 line decoder is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding
or data-routing applications requiring very short propagation delay times. In high-performance memory
systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed
memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory
usually are less than the typical access time of the memory. This means that the effective system delay
introduced by the decoder is negligible.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1G139YEPR
SN74LVC1G139YZPR
Reel of 3000
_ _ _C9_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
−40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1G139DCTR
SN74LVC1G139DCTT
SN74LVC1G139DCUR
SSOP − DCT
C39_ _ _
C39_
VSSOP − DCU
Reel of 250
SN74LVC1G139DCUT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DCT: The actual top-side marking has three additional characters that designate the year, month, and assembly/test site.
DCU: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
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Copyright 2004 Texas Instruments Incorporated
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1
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SCES602 − AUGUST 2004
description/ordering information (continued)
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
SELECT
B
L
A
L
Y0
L
Y1
H
L
Y2
H
H
L
Y3
H
H
H
L
L
H
L
H
H
H
H
H
H
H
H
H
logic diagram (positive logic)
1
A
3
5
6
7
Y3
Y2
Y1
Y0
Select
Inputs
2
B
Data
Outputs
2
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SCES602 − AUGUST 2004
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DCT package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220°C/W
JA
DCU package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . 102°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
3
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SCES602 − AUGUST 2004
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
Operating
5.5
V
Supply voltage
V
CC
IH
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.7 × V
CC
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
= 4.5 V to 5.5 V
0.3 × V
5.5
CC
V
V
Input voltage
0
0
V
V
I
Output voltage
V
CC
−4
O
V
V
= 1.65 V
= 2.3 V
CC
−8
CC
−16
−24
−32
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
20
15
10
85
I
V
CC
= 3 V
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.8 V 0.15 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
= 5 V 0.5 V
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implicationsof Slow or Floating CMOS Inputs, literature number SCBA004.
4
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SCES602 − AUGUST 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V
MIN
− 0.1
MAX
UNIT
CC
I
I
I
I
= −100 mA
= −4 mA
= −8 mA
= −16 mA
1.65 V to 5.5 V
1.65 V
V
OH
OH
OH
OH
CC
1.2
2.3 V
1.9
2.4
2.3
V
OH
V
3 V
I
= −24 mA
OH
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
I
I
I
I
I
= −32 mA
= 100 mA
= 4 mA
OH
OL
OL
OL
OL
0.1
0.45
0.3
= 8 mA
2.3 V
V
OL
V
= 16 mA
0.4
3 V
0.55
I
I
= 24 mA
= 32 mA
OL
OL
4.5 V
0.55
1
I
I
V = 5.5 V or GND
0 to 5.5 V
mA
A or B inputs
I
I
V or V = 5.5 V
0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
5
10
mA
mA
mA
pF
off
CC
I
O
I
V = 5.5 V or GND,
I
I
= 0
O
∆I
CC
One input at V
CC
− 0.6 V,
Other inputs at V
CC
or GND
500
C
V = V
or GND
= 3.3 V, T = 25°C.
4
i
I
CC
†
All typical values are at V
CC
A
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
1.5 7.5
MIN MAX
0.9 4.9
MIN MAX
0.8 3.6
t
pd
A or B
2.7 15.3
ns
Y
switching characteristics over recommended operating free-air temperature range, C = 30 pF or
L
50 pF (unless otherwise noted) (see Figure 2)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
1.1 4.2
t
pd
A or B
3
16.7
1.6
8.2
1.2
5.9
ns
Y
operating characteristics, T = 25°C
A
V
CC
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
TEST
CONDITIONS
CC
TYP
39
PARAMETER
UNIT
TYP
TYP
34
TYP
36
‡
C
pd
Power dissipation capacitance
f = 10 MHz
31
pF
‡
Two outputs switching
5
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SCES602 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
L
R
L
V
LOAD
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
(see Note B)
V
+ V
LOAD
OL
∆
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SCES602 − AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
Open
GND
t
t
/t
PLH PHL
/t
C
L
t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
L
R
L
V
LOAD
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
(see Note B)
V
+ V
LOAD
OL
∆
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS049B – MAY 1999 – REVISED OCTOBER 2002
DCT (R-PDSO-G8)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,13
0,65
8
5
0,15 NOM
2,90
2,70
4,25
3,75
Gage Plane
PIN 1
INDEX AREA
0,25
1
4
0° – 8°
0,60
0,20
3,15
2,75
1,30 MAX
Seating Plane
0,10
0,10
0,00
4188781/C 09/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion
D. Falls within JEDEC MO-187 variation DA.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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