SN74LVC1G175_15 [TI]
Single D-Type Flip-Flop With Asynchronous Clear;
| 型号： | SN74LVC1G175_15 |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | Single D-Type Flip-Flop With Asynchronous Clear |
| 文件： | 总12页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁ ꢂꢃ ꢄꢅ ꢆꢇ ꢈ ꢇꢂ ꢉ
ꢀꢊ ꢁꢈ ꢄ ꢋ ꢌꢍꢎ ꢏꢐ ꢋ ꢑꢄ ꢊꢐ ꢍꢑ ꢄꢒ ꢐ
ꢓ ꢊꢎ ꢔ ꢕꢀꢏ ꢁꢆꢔꢖ ꢒꢁ ꢒꢗꢀ ꢆ ꢄꢋ ꢕꢖ
SCES560A − MARCH 2004 − REVISED AUGUST 2004
DBV OR DCK PACKAGE
(TOP VIEW)
D
Available in the Texas Instruments
NanoStar and NanoFree Packages
D
D
D
D
D
D
D
D
Supports 5-V V
Operation
CC
1
2
3
6
5
4
CLK
GND
D
CLR
Inputs Accept Voltages to 5.5 V
V
CC
Max t of 4.3 ns at 3.3 V
pd
Low Power Consumption, 10-µA Max I
24-mA Output Drive at 3.3 V
Q
CC
YEP OR YZP PACKAGE
(BOTTOM VIEW)
I
Supports Partial-Power-Down Mode
off
Operation
3 4
2 5
1 6
D
GND
CLK
Q
Latch-Up Performance Exceeds 100 mA
Per JESD 78, Class II
V
CC
CLR
ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
description/ordering information
This single D-type flip-flop is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G175 has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D)
is transferred to the output pin (Q) on the clock’s (CLK) rising edge. When CLR is low, Q is forced into the low
state, regardless of the clock edge or data on D.
NanoStar and NanoFree package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,
off
off
preventing damaging current backflow through the device when it is powered down.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar − WCSP (DSBGA)
0.23-mm Large Bump − YEP
SN74LVC1G175YEPR
Reel of 3000
_ _ _D6_
NanoFree − WCSP (DSBGA)
0.23-mm Large Bump − YZP (Pb-free)
SN74LVC1G175YZPR
−40°C to 85°C
Reel of 3000
Reel of 250
Reel of 3000
SN74LVC1G175DBVR
SN74LVC1G175DBVT
SN74LVC1G175DCKR
SOT (SOT-23) − DBV
C75_
D6_
SOT (SC-70) − DCK
Reel of 250
SN74LVC1G175DCKT
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar and NanoFree are trademarks of Texas Instruments.
ꢐꢖ ꢒ ꢌꢗ ꢆ ꢎꢊ ꢒꢁ ꢌ ꢕꢎꢕ ꢘꢙ ꢚꢛ ꢜ ꢝꢞ ꢟꢘꢛꢙ ꢘꢠ ꢡꢢ ꢜ ꢜ ꢣꢙꢟ ꢞꢠ ꢛꢚ ꢤꢢꢥ ꢦꢘꢡ ꢞꢟꢘ ꢛꢙ ꢧꢞ ꢟꢣꢨ
ꢐꢜ ꢛ ꢧꢢꢡ ꢟ ꢠ ꢡ ꢛꢙ ꢚꢛꢜ ꢝ ꢟꢛ ꢠ ꢤꢣ ꢡ ꢘꢚ ꢘꢡꢞ ꢟꢘꢛꢙ ꢠ ꢤꢣ ꢜ ꢟꢩꢣ ꢟꢣ ꢜ ꢝꢠ ꢛꢚ ꢎꢣꢪ ꢞ ꢠ ꢊꢙꢠ ꢟꢜ ꢢꢝ ꢣꢙꢟ ꢠ
ꢠ ꢟꢞ ꢙ ꢧꢞ ꢜ ꢧ ꢫ ꢞ ꢜꢜ ꢞ ꢙ ꢟꢬꢨ ꢐꢜ ꢛ ꢧꢢꢡ ꢟꢘꢛꢙ ꢤꢜ ꢛꢡ ꢣꢠ ꢠꢘ ꢙꢭ ꢧꢛꢣ ꢠ ꢙꢛꢟ ꢙꢣ ꢡꢣ ꢠꢠ ꢞꢜ ꢘꢦ ꢬ ꢘꢙꢡ ꢦꢢꢧ ꢣ
ꢟꢣ ꢠ ꢟ ꢘꢙ ꢭ ꢛꢚ ꢞ ꢦꢦ ꢤꢞ ꢜ ꢞ ꢝ ꢣ ꢟꢣ ꢜꢠ ꢨ
Copyright 2004, Texas Instruments Incorporated
1
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ꢓꢊ ꢎ ꢔ ꢕ ꢀꢏꢁ ꢆ ꢔ ꢖꢒ ꢁꢒ ꢗꢀ ꢆꢄ ꢋꢕ ꢖ
SCES560A − MARCH 2004 − REVISED AUGUST 2004
FUNCTION TABLE
INPUTS OUTPUTS
CLK
CLR
H
D
L
Q
L
↑
↑
H
H
X
X
H
H
H or L
X
Q
O
L
L
logic diagram (positive logic)
6
CLR
1
CLK
3
D
R
D
4
Q
C1
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
I
Voltage range applied to any output in the high-impedance or power-off state, V
O
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 6.5 V
Voltage range applied to any output in the high or low state, V
O
(see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to V
+ 0.5 V
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
IK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −50 mA
OK
O
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
O
Continuous current through V
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 3): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied.
Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The value of V is provided in the recommended operating conditions table.
CC
3. The package thermal impedance is calculated in accordance with JESD 51-7.
2
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SCES560A − MARCH 2004 − REVISED AUGUST 2004
recommended operating conditions (see Note 4)
MIN
1.65
MAX
UNIT
Operating
5.5
V
Supply voltage
V
CC
IH
Data retention only
1.5
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.65 × V
1.7
CC
V
High-level input voltage
V
V
2
= 4.5 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
0.7 × V
CC
0.35 × V
0.7
CC
V
IL
Low-level input voltage
0.8
= 4.5 V to 5.5 V
0.3 × V
5.5
CC
V
V
Input voltage
0
0
V
V
I
Output voltage
V
CC
−4
O
V
V
= 1.65 V
= 2.3 V
CC
−8
CC
−16
−24
−32
4
I
High-level output current
Low-level output current
mA
mA
OH
OL
V
= 3 V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.65 V
= 2.3 V
8
16
24
32
20
10
10
85
I
V
CC
= 3 V
V
CC
V
CC
V
CC
V
CC
= 4.5 V
= 1.8 V 0.15 V, 2.5 V 0.2 V
= 3.3 V 0.3 V
= 5 V 0.5 V
∆t/∆v Input transition rise or fall rate
ns/V
T
Operating free-air temperature
−40
°C
A
NOTE 4: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implicationsof Slow or Floating CMOS Inputs, literature number SCBA004.
3
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ꢓꢊ ꢎ ꢔ ꢕ ꢀꢏꢁ ꢆ ꢔ ꢖꢒ ꢁꢒ ꢗꢀ ꢆꢄ ꢋꢕ ꢖ
SCES560A − MARCH 2004 − REVISED AUGUST 2004
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V
MIN
V − 0.1
CC
MAX
UNIT
CC
I
I
I
I
= −100 mA
= −4 mA
= −8 mA
= −16 mA
1.65 V to 5.5 V
1.65 V
OH
OH
OH
OH
1.2
1.9
2.4
2.3
2.3 V
V
OH
V
3 V
I
= −24 mA
OH
4.5 V
1.65 V to 5.5 V
1.65 V
3.8
I
I
I
I
I
= −32 mA
= 100 mA
= 4 mA
OH
OL
OL
OL
OL
0.1
0.45
0.3
= 8 mA
2.3 V
V
OL
V
= 16 mA
0.4
3 V
0.55
I
I
= 24 mA
= 32 mA
OL
OL
4.5 V
0 to 5.5 V
0
0.55
1
I
I
I
V = 5.5 V or GND
mA
mA
mA
mA
pF
I
I
V or V = 5.5 V
10
off
I
O
V = 5.5 V or GND,
I = 0
O
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
10
CC
I
∆I
CC
One input at V
CC
− 0.6 V,
Other inputs at V
CC
or GND
500
C
V = V
or GND
= 3.3 V, T = 25°C.
3
i
I
CC
†
All typical values are at V
CC
A
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 1.8 V
CC
0.15 V
V = 2.5 V
CC
0.2 V
V = 3.3 V
CC
0.3 V
V = 5 V
CC
0.5 V
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN
MAX
175
f
t
Clock frequency
Pulse duration
100
125
150
MHz
ns
clock
CLR
CLK
Data
Low
5.6
3.5
3
3
3
2.8
2.8
2
2.5
2.5
1.5
0.5
0.5
w
High or Low
2.5
0
t
t
Setup time, before CLK↑
Hold time, data after CLK↑
ns
ns
su
CLR inactive
0
0.5
0.5
0
0
h
switching characteristics over recommended operating free-air temperature range, C = 15 pF
L
(unless otherwise noted) (see Figure 1)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
100
MIN MAX
MIN MAX
MIN MAX
f
t
125
150
175
MHz
ns
max
CLK
CLR
2.5 12.9
2.5 12.4
2
2
6.5
6
1.4
1.2
4.6
4.3
1
1
3
Q
pd
3.2
4
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ꢓ ꢊꢎ ꢔ ꢕꢀ ꢏꢁꢆꢔꢖ ꢒꢁ ꢒꢗ ꢀ ꢆ ꢄꢋ ꢕꢖ
SCES560A − MARCH 2004 − REVISED AUGUST 2004
switching characteristics over recommended operating free-air temperature range, C = 30 pF or
L
50 pF (unless otherwise noted) (see Figure 2)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN MAX
f
t
100
125
150
175
MHz
ns
max
CLK
CLR
2.7 13.4
2.7 12.9
2.2
2.2
7.1
7
1.6
1.5
5.7
5.8
1.5
1.3
4
Q
pd
4.1
operating characteristics, T = 25°C
A
V
= 1.8 V
V
CC
= 2.5 V
V
CC
= 3.3 V
V
= 5 V
TEST
CONDITIONS
CC
TYP
18
CC
TYP
21
PARAMETER
UNIT
TYP
19
TYP
19
C
pd
Power dissipation capacitance
f = 10 MHz
pF
5
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SCES560A − MARCH 2004 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
L
R
L
V
LOAD
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
15 pF
15 pF
15 pF
15 pF
1 MΩ
1 MΩ
1 MΩ
1 MΩ
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
(see Note B)
V
+ V
LOAD
OL
∆
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
6
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SCES560A − MARCH 2004 − REVISED AUGUST 2004
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
L
PLZ PZL
LOAD
GND
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
L
R
L
V
LOAD
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
V
3 V
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
V
/2
/2
2 × V
2 × V
6 V
2 × V
CC
30 pF
30 pF
50 pF
50 pF
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
CC
CC
CC
CC
CC
CC
1.5 V
/2
V
CC
V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
OH
V
V
/2
LOAD
V
V
V
M
M
Output
V
V
M
S1 at V
(see Note B)
V
+ V
LOAD
OL
∆
OL
OL
t
PHL
PLH
t
t
PZH
PHZ
− V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
PHL
are the same as t
.
dis
PLZ
PZL
PLH
PHZ
PZH
are the same as t
.
en
are the same as t .
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
6
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-3/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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