SN74LVC1G3157DBVR [TI]
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH; 单刀双掷模拟开关
| 型号： | SN74LVC1G3157DBVR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH |
| 文件： | 总16页 (文件大小：312K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
DBV OR DCK PACKAGE
(TOP VIEW)
1.65-V to 5.5-V V
Operation
CC
Useful for Both Analog and Digital
Applications
1
2
3
6
5
4
B2
GND
B1
S
V
A
Specified Break-Before-Make Switching
Rail-to-Rail Signal Handling
High Degree of Linearity
CC
High Speed, Typically 0.5 ns
YEP OR YZP PACKAGE
(BOTTOM VIEW)
(V
= 3 V, C = 50 pF)
CC
L
Low On-State Resistance, Typically ≈6 Ω
(V = 4.5 V)
3 4
2 5
1 6
B1
GND
B2
A
V
S
CC
CC
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V V
operation.
CC
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes
of up to V (peak) to be transmitted in either direction.
CC
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
T
A
PACKAGE
‡
NanoStar – WCSP (DSBGA)
0.23-mm Large Bump – YEP
SN74LVC1G3157YEPR
SN74LVC1G3157YZPR
Tape and reel
_ _ _C5_
NanoFree – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
–40°C to 85°C
SOT (SOT-23) – DBV
Tape and reel
Tape and reel
SN74LVC1G3157DBVR
SN74LVC1G3157DCKR
CC5_
C5_
SOT (SC-70) – DCK
†
‡
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one
following character to designate the assembly/test site. Pin
1 identifier indicates solder-bump composition
(1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
FUNCTION TABLE
CONTROL
ON
INPUT
S
CHANNEL
L
B1
B2
H
logic diagram (positive logic)
1
B2
6
4
A
S
3
B1
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
CC
Control input voltage range, V (see Notes 1 and 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6.5 V
Switch I/O voltage range, V (see Notes 1, 2, 3, and 4) . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
Control input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IN
I/O
+ 0.5 V
CC
IK IN
I/O port diode current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
IOK I/O
I/O CC
On-state switch current, I (V = 0 to V ) (see Note 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Continuous current through V
I/O I/O
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 mA
CC
Package thermal impedance, θ (see Note 6): DBV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165°C/W
JA
DCK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259°C/W
YEP/YZP package . . . . . . . . . . . . . . . . . . . . . . . . . . . 123°C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
Storage temperature range, T
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to ground unless otherwise specified.
2. The input and output voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 5.5 V maximum.
4. V , V , V , and V are used to denote specific conditions for V
Bn I/O
.
I
O
A
5. I , I , I , and I are used to denote specific conditions for I .
I
O
A
Bn
I/O
6. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
recommended operating conditions (see Note 7)
MIN
1.65
0
MAX
UNIT
V
CC
V
I/O
V
IN
5.5
V
V
V
V
CC
5.5
0
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 1.65 V to 1.95 V
= 2.3 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 5.5 V
= 1.65 V to 1.95 V
= 2.3 V to 2.7 V
= 3 V to 3.6 V
V
× 0.75
CC
V
High-level input voltage, control input
Low-level input voltage, control input
V
V
IH
IL
V
× 0.7
CC
V
× 0.25
CC
V
V
× 0.3
20
CC
20
∆t/∆v
Input transition rise/fall time
ns/V
10
= 4.5 V to 5.5 V
10
T
A
–40
85
°C
NOTE 7: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
TYP
PARAMETER
TEST CONDITIONS
V = 0 V
MIN
MAX
20
50
12
30
9
UNIT
V
CC
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
O
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
= 4 mA
11
15
8
I
1.65 V
2.3 V
3 V
V = 1.65 V
I
= –4 mA
= 8 mA
V = 0 V
I
V = 2.3 V
I
= –8 mA
= 24 mA
= –24 mA
= 30 mA
= –30 mA
= –30 mA
= –4 mA
= –8 mA
= –24 mA
= –30 mA
= –4 mA
= –8 mA
= –24 mA
= –30 mA
= –4 mA
= –8 mA
= –24 mA
= –30 mA
11
7
See
‡
r
On-state switch resistance
V = 0 V
Ω
on
I
Figures 1 and 2
V = 3 V
I
9
20
7
V = 0 V
I
6
V = 2.4 V
I
4.5 V
7
12
15
140
45
18
10
V = 4.5 V
I
7
1.65 V
2.3 V
3 V
On-state switch resistance
0 ≤ V ≤ V
Bn CC
(see Figures 1 and 2)
r
Ω
Ω
Ω
range
‡§
over signal range
4.5 V
1.65 V
2.3 V
3 V
V
Bn
V
Bn
V
Bn
V
Bn
= 1.15 V
= 1.6V
0.5
0.1
0.1
0.1
110
26
9
Difference of on-state
resistance between switches
∆r
See Figure 1
on
‡¶#
= 2.1 V
= 3.15 V
4.5 V
1.65 V
2.3 V
3 V
‡¶||
r
I
ON resistance flatness
0 ≤ V ≤ V
Bn CC
on(flat)
4.5 V
4
1
1.65 V
to 5.5 V
Off-state switch leakage current 0 ≤ V , V ≤ V , (see Figure 3)
CC
µA
µA
µA
I
O
off
†
1
0.05
1
V = V
or GND,
I
CC
= Open (see Figure 4)
I
On-state switch leakage current
Control input current
5.5 V
S(on)
†
0.1
V
O
1
0 V to
5.5 V
I
I
0 ≤ V ≤ V
IN
IN
CC
†
1
0.05
1
Supply current
V
V
= V
= V
or GND
– 0.6 V
5.5 V
5.5 V
10
µA
µA
CC
IN
CC
CC
∆I
Supply-current change
500
CC
IN
Control input
S
C
C
C
5 V
5 V
2.7
5.2
pF
pF
in
capacitance
Switch input/output
Bn
io(off)
io(on)
capacitance
Bn
A
17.3
17.3
Switch input/output
capacitance
5 V
pF
†
‡
T
= 25°C
A
Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of the
voltages on the two (A or B) ports.
Specified by design
§
¶
#
||
∆r = r measured at identical V , temperature, and voltage levels.
– r
on on(max) on(min) CC
This parameter is characterized, but not tested in production.
Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of conditions.
I
off
is the same as I
(off-state switch leakage current).
S(off)
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
analog switch characteristics, T = 25°C
A
FROM
TO
(OUTPUT)
PARAMETER
(INPUT)
TEST CONDITIONS
V
TYP
300
UNIT
CC
1.65 V
2.3 V
3 V
R
= 50 Ω,
= sine wave
(see Figure 6)
L
300
300
300
–54
–54
–54
–54
–57
–57
–57
–57
3
Frequency response
A or Bn
Bn or A
MHz
f
in
†
(switch on)
4.5 V
1.65 V
2.3 V
3 V
R
= 50 Ω,
= 10 MHz (sine wave)
(see Figure 7)
L
Crosstalk
(between switches)
B1 or B2
B2 or B1
dB
f
in
‡
4.5 V
1.65 V
2.3 V
3 V
C
= 5 pF, R = 50 Ω,
L
L
Feed-through attenuation
A or Bn
Bn or A
dB
pC
%
f
in
= 10 MHz (sine wave)
‡
(switch off)
(see Figure 8)
4.5 V
3.3 V
5 V
C
= 0.1 nF, R = 1 MΩ,
L
(see Figure 9)
L
§
S
A
Charge injection
7
1.65 V
2.3 V
3 V
0.1
V = 0.5 V p-p, R = 600 Ω,
I
in
L
0.025
0.015
0.01
f
= 600 Hz to 20 kHz
Total harmonic distortion
A or Bn
Bn or A
(sine wave)
(see Figure 10)
4.5 V
†
‡
§
Adjust f voltage to obtain 0 dBm at output. Increase f frequency until dB meter reads –3 dB.
in
in
Adjust f voltage to obtain 0 dBm at input.
in
Specified by design
switching characteristics over recommended operating free-air temperature range (unless
otherwise noted) (see Figures 5 and 11)
V
= 1.8 V
V
= 2.5 V
V
= 3.3 V
V
= 5 V
CC
0.15 V
CC
0.2 V
CC
0.3 V
CC
0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX
MIN MAX
MIN MAX
MIN
MAX
¶
#
t
t
t
A or Bn
S
Bn or A
Bn
2
24
13
1.2
14
0.8
7.6
5.3
0.3
5.7
3.8
ns
ns
ns
pd
en
7
3
3.5
2
2.5
1.5
1.7
0.8
||
7.5
dis
t
0.5
0.5
0.5
0.5
B-M
¶
t
is the slower of t
or t
PLH
. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and the
PHL
pd
specified load capacitance when driven by an ideal voltage source (zero output impedance).
#
||
t
t
is the slower of t
PZL
is the slower of t
or t
.
en
dis
PZH
or t .
PHZ
PLZ
Specified by design
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
V
O
V = V
I
or GND
CC
GND
I
O
VI VO
IO
r
on
V
V – V
I
O
Figure 1. On-State Resistance Test Circuit
120
100
80
60
40
20
0
V
CC
= 1.65 V
V
CC
= 2.3 V
V
CC
= 3 V
V
CC
= 4.5 V
0
1
2
3
4
5
V – V
I
Figure 2. Typical r as a Function of Input Voltage (V ) for V = 0 to V
CC
on
I
I
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
V
IL
or V
IH
1
2
B1
B2
SW
V
O
A
V
I
A
GND
Condition 1: V = GND, V = V
I
O
CC
Condition 2: V = V , V = GND
I
CC
O
Figure 3. Off-State Switch Leakage-Current Test Circuit
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
or V
IL
IH
A
1
2
B1
B2
SW
V
O
O
V
= Open
V
I
GND
V = V
I
or GND
CC
Figure 4. On-State Switch Leakage-Current Test Circuit
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
LOAD
Open
S1
R
L
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
PLH PHL
/t
C
L
t
V
R
PLZ PZL
LOAD
GND
L
(see Note A)
/t
PHZ PZH
LOAD CIRCUIT
INPUTS
V
CC
V
M
V
C
R
L
V
LOAD
L
∆
V
I
t /t
r f
1.8 V 0.15 V
2.5 V 0.2 V
3.3 V 0.3 V
5 V 0.5 V
V
CC
V
CC
V
CC
V
CC
≤2 ns
≤2 ns
≤2.5 ns
≤2.5 ns
V
CC
V
CC
V
CC
V
CC
/2
/2
/2
/2
2 × V
2 × V
2 × V
2 × V
50 pF
50 pF
50 pF
50 pF
500 Ω
500 Ω
500 Ω
500 Ω
0.3 V
0.3 V
0.3 V
0.3 V
CC
CC
CC
CC
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
su
h
V
I
V
I
Input
V
M
V
M
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
I
V
I
Output
Control
V
M
V
M
Input
V
M
V
M
0 V
V
0 V
t
t
t
t
t
PHL
PZL
PLZ
+ V
PLH
PHL
Output
Waveform 1
V
/2
OH
LOAD
V
V
V
M
Output
M
V
V
M
S1 at V
(see Note B)
V
LOAD
OL
∆
V
OL
V
OL
t
PLH
t
t
PZH
PHZ
– V
Output
Waveform 2
S1 at GND
V
V
OH
V
OH
V
V
M
OH
∆
M
Output
M
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time with one transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
.
.
PLZ
PZL
PLH
PHZ
PZH
PHL
dis
en
pd
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
V
O
R
L
GND
f
50 Ω
in
R
= 50 Ω
L
Figure 6. Frequency Response (Switch On)
S
V
V
TEST CONDITION
20log (V /V )
V
CC
IL
10 O2 I
20log (V /V )
10 O1
I
IH
V
CC
S
V
IL
or V
IH
V
B1
B1
f
in
V
B2
A
Analyzer
B2
GND
R
L
50 Ω
R
= 50 Ω
L
Figure 7. Crosstalk (Between Switches)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
V
SW
1
S
CC
V
IL
2
V
IH
CC
S
A
V
IL
or V
IH
1
2
B1
B2
SW
Analyzer
R
L
GND
f
50 Ω
in
R
= 50 Ω
L
Figure 8. Feed Through
V
CC
CC
V
S
1
B1
B2
LOGIC
INPUT
R
GEN
SW
2
V
GE
A
V
OUT
GND
R /C = 1 MΩ/100 pF
R
L
C
L
L
L
LOGIC
INPUT
OFF
ON
OFF
∆V
OUT
V
OUT
Q = (∆V
) (C )
OUT
L
Figure 9. Charge-Injection Test
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
SCES424C – JANUARY 2003 - REVISED SEPTEMBER 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
A
V
IL
or V
IH
1
2
B1
B2
10 µF
SW
R
V
O
C
50 pF
L
L
10 kΩ
GND
V
CC
/2
f
600 Ω
in
V
CC
V
CC
V
CC
V
CC
= 1.65 V, V = 1.4 V
I
P-P
P-P
P-P
P-P
= 2.30 V, V = 2.0 V
I
= 3.00 V, V = 2.5 V
I
= 4.50 V, V = 4.0 V
I
Figure 10. Total Harmonic Distortion
V
CC
V
CC
S
B1
B2
V = V /2
I
CC
V
O
A
GND
V
V
S
R
C
L
L
R /C = 50 Ω/35 pF
L
L
O
0.9 x V
O
t
D
Figure 11. Break-Before-Make Internal Timing
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MPDS114 – FEBRUARY 2002
DCK (R-PDSO-G6)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
6
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-3/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
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TI warrants performance of its hardware products to the specifications applicable at the time of sale in
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