SN74LVC1G3157DSFR [TI]
5V、2:1 (SPDT)、单通道通用模拟开关 | DSF | 6 | -40 to 125;
| 型号： | SN74LVC1G3157DSFR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 5V、2:1 (SPDT)、单通道通用模拟开关 | DSF | 6 | -40 to 125 开关 光电二极管 输出元件 |
| 文件： | 总23页 (文件大小：932K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
FEATURES
•
•
•
Low On-State Resistance, Typically ≈6 Ω
(VCC = 4.5 V)
•
1.65-V to 5.5-V VCC Operation
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
•
Useful for Both Analog and Digital
Applications
ESD Protection Exceeds JESD 22
•
•
•
•
Specified Break-Before-Make Switching
Rail-to-Rail Signal Handling
–
–
–
2000-V Human-Body Model (A114-A)
200-V Machine Model (A115-A)
High Degree of Linearity
1000-V Charged-Device Model (C101)
High Speed, Typically 0.5 ns
(VCC = 3 V, CL = 50 pF)
DBV PACKAGE
(TOP VIEW)
DCK PACKAGE
(TOP VIEW)
DRL PACKAGE
(TOP VIEW)
1
2
3
6
5
4
B2
GND
B1
S
1
2
3
6
5
4
B2
GND
B1
S
1
2
3
6
5
4
B2
GND
B1
S
VCC
VCC
A
VCC
A
A
DRY PACKAGE
(TOP VIEW)
YZP PACKAGE
(BOTTOM VIEW)
3
2
1
4
5
6
B1
GND
B2
A
1
2
3
6
5
4
B2
GND
B1
S
VCC
VCC
S
A
See mechanical drawings for dimensions.
DESCRIPTION/ORDERING INFORMATION
This single-pole, double-throw (SPDT) analog switch is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G3157 can handle both analog and digital signals. The device permits signals with amplitudes of
up to VCC (peak) to be transmitted in either direction.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for
analog-to-digital and digital-to-analog conversion systems.
ORDERING INFORMATION
TA
PACKAGE(1)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SON – DRY
Reel of 3000
SN74LVC1G3157YZPR
_ _ _ C5_
Reel of 5000
Reel of 3000
Reel of 3000
Reel of 4000
SN74LVC1G3157DRYR
SN74LVC1G3157DBVR
SN74LVC1G3157DCKR
SN74LVC1G3157DRLR
C5_
CC5_
C5_
C5_
–40°C to 85°C
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
SOT (SOT-553) – DRL
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK/DRL/DRY: The actual top-side marking has one additional character that designates the assembly/test site.
YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, • = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoFree is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2003–2007, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
FUNCTION TABLE
CONTROL
INPUT
ON
CHANNEL
S
L
B1
B2
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
6
3
B2
S
4
A
B1
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
MAX UNIT
VCC
VIN
VI/O
IIK
Supply voltage range(2)
6.5
6.5
V
Control input voltage range(2)(3)
Switch I/O voltage range(2)(3)(4)(5)
Control input clamp current
I/O port diode current
V
–0.5 VCC + 0.5
V
VIN < 0
–50
±50
mA
mA
mA
mA
IIOK
II/O
VI/O < 0 or VI/O > VCC
VI/O = 0 to VCC
On-state switch current(6)
±128
±100
165
Continuous current through VCC or GND
DBV package
DCK package
DRL package
DRY package
YZP package
259
θJA
Package thermal impedance(7)
142 °C/W
234
123
Tstg
Storage temperature range
–65
150
°C
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are with respect to ground unless otherwise specified.
(3) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
(4) This value is limited to 5.5 V maximum.
(5) VI, VO, VA, and VBn are used to denote specific conditions for VI/O
(6) II, IO, IA, and IBn are used to denote specific conditions for II/O
(7) The package thermal impedance is calculated in accordance with JESD 51-7.
.
.
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
Recommended Operating Conditions(1)
MIN
MAX UNIT
VCC
VI/O
VIN
1.65
5.5
VCC
5.5
V
V
V
0
0
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
V
CC × 0.75
VIH
VIL
High-level input voltage, control input
Low-level input voltage, control input
V
V
V
CC × 0.7
V
CC × 0.25
V
CC × 0.3
20
20
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
10
VCC = 4.5 V to 5.5 V
10
TA
–40
85
°C
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1)
MAX UNIT
VI = 0 V
IO = 4 mA
11
15
8
20
50
12
30
1.65 V
VI = 1.65 V IO = –4 mA
VI = 0 V
IO = 8 mA
2.3 V
3 V
VI = 2.3 V
VI = 0 V
IO = –8 mA
IO = 24 mA
IO = –24 mA
IO = 30 mA
IO = –30 mA
IO = –30 mA
IA = –4 mA
IA = –8 mA
IA = –24 mA
IA = –30 mA
11
7
See Figure 1 and
Figure 2
ron
On-state switch resistance(2)
9
20
7
Ω
VI = 3 V
9
VI = 0 V
6
VI = 2.4 V
VI = 4.5 V
4.5 V
7
12
15
140
45
18
10
7
1.65 V
2.3 V
3 V
On-state switch resistance
over signal range(2)(3)
0 ≤ VBn ≤ VCC
rrange
Ω
Ω
Ω
(see Figure 1 and Figure 2)
4.5 V
VBn = 1.15
V
IA = –4 mA
1.65 V
0.5
Difference of on-state
resistance between
switches(2)(4)(5)
VBn = 1.6 V IA = –8 mA
VBn = 2.1 V IA = –24 mA
2.3 V
3 V
0.1
0.1
∆ron
See Figure 1
VBn = 3.15
IA = –30 mA
V
4.5 V
0.1
IA = –4 mA
IA = –8 mA
IA = –24 mA
IA = –30 mA
1.65 V
2.3 V
3 V
110
26
9
ron(flat)
ON resistance flatness(2)(4)(6) 0 ≤ VBn ≤ VCC
4.5 V
4
(1) TA = 25°C
(2) Measured by the voltage drop between I/O pins at the indicated current through the switch. ON resistance is determined by the lower of
the voltages on the two (A or B) ports.
(3) Specified by design
(4) ∆ron = ron(max) – ron(min) measured at identical VCC, temperature, and voltage levels
(5) This parameter is characterized, but not tested in production.
(6) Flatness is defined as the difference between the maximum and minimum values of ON resistance over the specified range of
conditions.
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
Electrical Characteristics (continued)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN TYP(1)
MAX UNIT
±1
µA
Off-state switch leakage
current
0 ≤ VI, VO ≤ VCC
(see Figure 3 )
1.65 V to
5.5 V
(7)
Ioff
±0.05
±1(1)
±1
µA
On-state switch leakage
current
VI = VCC or GND, VO = Open
(see Figure 4)
IS(on)
5.5 V
±0.1(1)
±1
µA
0 V to
5.5 V
IIN
Control input current
0 ≤ VIN≤ VCC
±0.05
±1(1)
ICC
Supply current
VIN = VCC or GND
VIN = VCC – 0.6 V
5.5 V
5.5 V
1
10
µA
µA
∆ICC
Supply-current change
500
Control input
capacitance
Cin
S
5 V
5 V
2.7
5.2
pF
pF
Switch input/ouput
capacitance
Cio(off)
Bn
Bn
A
17.3
17.3
Switch input/ouput
capacitance
Cio(on)
5 V
pF
(7) Ioff is the same as IS(off) (off-state switch leakage current).
4
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
Analog Switch Characteristics
TA = 25°C
FROM
PARAMETER
TO
(OUTPUT)
TEST CONDITIONS
VCC
TYP
UNIT
(INPUT)
1.65 V
2.3 V
3 V
300
300
300
300
–54
–54
–54
–54
–57
–57
–57
–57
3
Frequency
RL = 50 Ω,
fin = sine wave
(see Figure 6 )
response(1)
(switch on)
A or Bn
Bn or A
MHz
4.5 V
1.65 V
2.3 V
3 V
Crosstalk(2)
(between
switches)
RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 7 )
B1 or B2
B2 or B1
dB
4.5 V
1.65 V
2.3 V
3 V
Feed-through
attenuation(2)
(switch off)
CL = 5 pF, RL = 50 Ω,
fin = 10 MHz (sine wave)
(see Figure 8 )
A or Bn
Bn or A
dB
pC
%
4.5 V
3.3 V
5 V
CL = 0.1 nF, RL = 1 MΩ
(see Figure 9 )
Charge injection(3)
S
A
7
1.65 V
2.3 V
3 V
0.1
VI = 0.5 Vp-p, RL = 600 Ω,
fin = 600 Hz to 20 kHz (sine wave)
(see Figure 10 )
0.025
0.015
0.01
Total harmonic
distortion
A or Bn
Bn or A
4.5 V
(1) Adjust fin voltage to obtain 0 dBm at output. Increase fin frequency until dB meter reads –3 dB.
(2) Adjust fin voltage to obtain 0 dBm at input.
(3) Specified by design
Switching Characteristics
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5 and Figure 11)
VCC = 1.8 V
± 0.15 V
VCC = 2.5 V
± 0.2 V
VCC = 3.3 V
± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
MAX
MIN
MAX
MIN MAX
MIN
MAX
(1)
tpd
A or Bn
S
Bn or A
Bn
2
24
13
1.2
14
0.8
0.3
5.7
3.8
ns
ns
ns
(2)
ten
7
3
3.5
2
2.5
1.5
0.5
7.6
5.3
1.7
0.8
0.5
(3)
tdis
7.5
(4)
tB-M
0.5
0.5
(1) tpd is the slower of tPLH or tPHL. The propagation delay is calculated RC time constant of the typical on-state resistance of the switch and
the specified load capacitance when driven by an ideal voltage source (zero output impedance).
(2) ten is the slower of tPZL or tPZH
.
(3) tdis is the slower of tPLZ or tPHZ
(4) Specified by design
.
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION
V – V
I
O
r
=
Ω
on
IO
Figure 1. On-State Resistance Test Circuit
120
100
80
60
40
20
0
V
CC
= 1.65 V
V
CC
= 2.3 V
V
= 3 V
CC
V
CC
= 4.5 V
0
1
2
3
4
5
V - V
I
Figure 2. Typical ron as a Function of Input Voltage (VI) for VI = 0 to VCC
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 3. Off-State Switch Leakage-Current Test Circuit
V
CC
SW
1
S
V
IL
2
V
IH
V
CC
S
V
or V
IH
IL
1
2
B1
B2
SW
V
O
V
= Open
O
A
V
A
or GND
I
GND
V = V
CC
I
Figure 4. On-State Switch Leakage-Current Test Circuit
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
VLOAD
Open
S1
RL
From Output
Under Test
TEST
tPLH/tPHL
tPLZ/tPZL
tPHZ/tPZH
S1
GND
Open
VLOAD
GND
CL
(see Note A)
RL
LOAD CIRCUIT
INPUTS
VCC
VM
VLOAD
CL
RL
V
D
VI
tr/tf
VCC
VCC
VCC
VCC
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
£2 ns
£2 ns
VCC/2
VCC/2
VCC/2
VCC/2
2 × VCC
2 × VCC
2 × VCC
2 × VCC
50 pF
50 pF
50 pF
50 pF
500 W
0.3 V
0.3 V
0.3 V
0.3 V
500 W
500 W
500 W
£2.5 ns
£2.5 ns
VI
Timing Input
Data Input
VM
0 V
tW
tsu
th
VI
VI
Input
VM
VM
VM
VM
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VI
VI
Output
Control
VM
VM
Input
VM
VM
0 V
0 V
tPZL
tPLZ
tPLH
tPHL
VM
Output
Waveform 1
S1 at VLOAD
VOH
VOL
VLOAD/2
VM
VM
Output
Output
VOL + V
D
VOL
(see Note B)
tPHL
tPLH
tPZH
tPHZ
VOH
VOL
Output
Waveform 2
S1 at GND
VOH
VOH – V
D
VM
VM
VM
»0 V
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. CL includes probe and jig capacitance.
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR £ 10 MHz, ZO = 50 W.
D. The outputs are measured one at a time, with one transition per measurement.
E. tPLZ and tPHZ are the same as tdis.
F. tPZL and tPZH are the same as ten.
G. tPLH and tPHL are the same as tpd.
H. All parameters and waveforms are not applicable to all devices.
Figure 5. Load Circuit and Voltage Waveforms
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
50 Ω
R
= 50 Ω
L
Figure 6. Frequency Response (Switch On)
S
TEST CONDITION
20log (V /V )
V
V
V
IL
10 O2 I
CC
20log (V /V )
10 O1
V
IH
I
CC
S
V
or V
IH
V
B1
IL
B1
f
in
V
B2
A
Analyzer
B2
GND
R
L
50 Ω
R
= 50 Ω
L
Figure 7. Crosstalk (Between Switches)
9
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
50 Ω
R
= 50 Ω
L
Figure 8. Feedthrough
V
CC
CC
V
S
1
2
B1
B2
LOGIC
INPUT
R
GEN
SW
V
GE
A
V
OUT
GND
R /C = 1 MΩ/100 pF
L L
R
L
C
L
LOGIC
INPUT
OFF
ON
OFF
∆V
OUT
V
OUT
Q = (∆V
) (C )
L
OUT
Figure 9. Charge-Injection Test
10
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SN74LVC1G3157
SINGLE-POLE, DOUBLE-THROW ANALOG SWITCH
www.ti.com
SCES424F–JANUARY 2003–REVISED FEBRUARY 2007
PARAMETER MEASUREMENT INFORMATION (continued)
10 kΩ
600 Ω
Figure 10. Total Harmonic Distortion
V
CC
CC
V
S
B1
B2
V = V /2
I CC
V
O
A
GND
V
V
S
R
L
C
L
R /C = 50 Ω/35 pF
L
L
O
0.9 x V
O
t
D
Figure 11. Break-Before-Make Internal Timing
11
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PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2009
PACKAGING INFORMATION
Orderable Device
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
74LVC1G3157DBVRE4
74LVC1G3157DBVRG4
74LVC1G3157DCKRE4
74LVC1G3157DCKRG4
74LVC1G3157DRLRG4
74LVC1G3157DRYRG4
SN74LVC1G3157DBVR
SN74LVC1G3157DCKR
SOT-23
DBV
6
6
6
6
6
6
6
6
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SC70
SC70
SOT
DBV
DCK
DCK
DRL
DRY
DBV
DCK
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SON
5000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SOT-23
SC70
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G3157DGVR
SN74LVC1G3157DRLR
PREVIEW
ACTIVE
SOT-23
SOT
DBV
DRL
6
6
TBD
Call TI
Call TI
4000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G3157DRYR
SN74LVC1G3157YZPR
ACTIVE
ACTIVE
SON
DRY
YZP
6
6
5000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DSBGA
3000 Green (RoHS &
no Sb/Br)
SNAGCU
Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
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information may not be available for release.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
23-Jan-2009
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN74LVC1G3157 :
Automotive: SN74LVC1G3157-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2009
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74LVC1G3157DBVR SOT-23
DBV
DCK
DCK
DRL
DRY
YZP
6
6
6
6
6
6
3000
3000
3000
4000
5000
3000
180.0
180.0
180.0
180.0
179.0
180.0
9.2
8.4
9.2
9.2
8.4
8.4
3.23
2.24
2.24
1.78
1.2
3.17
2.34
2.34
1.78
1.65
1.52
1.37
1.22
1.22
0.69
0.7
4.0
4.0
4.0
4.0
4.0
4.0
8.0
8.0
8.0
8.0
8.0
8.0
Q3
Q3
Q3
Q3
Q1
Q1
SN74LVC1G3157DCKR
SN74LVC1G3157DCKR
SN74LVC1G3157DRLR
SN74LVC1G3157DRYR
SC70
SC70
SOT
SON
SN74LVC1G3157YZPR DSBGA
1.02
0.63
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Sep-2009
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74LVC1G3157DBVR
SN74LVC1G3157DCKR
SN74LVC1G3157DCKR
SN74LVC1G3157DRLR
SN74LVC1G3157DRYR
SN74LVC1G3157YZPR
SOT-23
SC70
SC70
SOT
DBV
DCK
DCK
DRL
DRY
YZP
6
6
6
6
6
6
3000
3000
3000
4000
5000
3000
202.0
202.0
205.0
202.0
220.0
220.0
201.0
201.0
200.0
201.0
205.0
220.0
28.0
28.0
33.0
28.0
50.0
34.0
SON
DSBGA
Pack Materials-Page 2
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