SN74LVC1G38DPWR [TI]
具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DPW | 5 | -40 to 85;
| 型号： | SN74LVC1G38DPWR |
| 厂家： | 
TEXAS INSTRUMENTS |
| 描述： | 具有漏极开路输出的单路 2 输入、1.65V 至 5.5V 与非门 | DPW | 5 | -40 to 85 栅 逻辑集成电路 栅极 |
| 文件： | 总12页 (文件大小：261K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC1G38
SINGLE 2-INPUT NAND GATE
WITH OPEN-DRAIN OUTPUT
www.ti.com
SCES538A–JANUARY 2004–REVISED APRIL 2005
FEATURES
DBV OR DCK PACKAGE
(TOP VIEW)
•
Available in the Texas Instruments
NanoStar™ and NanoFree™ Packages
1
2
3
5
4
A
B
V
Y
•
•
•
•
•
•
Supports 5-V VCC Operation
CC
Inputs Accept Voltages to 5.5 V
Max tpd of 4.5 ns at 3.3 V
GND
Low Power Consumption, 10-µA Max ICC
±24-mA Output Drive at 3.3 V
YEP OR YZP PACKAGE
(BOTTOM VIEW)
Ioff Supports Partial-Power-Down Mode
Operation
3
2
1
4
5
GND
B
Y
V
•
•
Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
A
CC
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ORDERING INFORMATION
The SN74LVC1G38 is designed for 1.65-V to 5.5-V VCC operation.
This device is a single two-input NAND buffer gate with open-drain output. It performs the Boolean function
Y = A B or Y = A + B in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs,
preventing damaging current backflow through the device when it is powered down.
NanoStar™ and NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the
die as the package.
ORDERING INFORMATION
TA
PACKAGE(1)
NanoStar™ – WCSP (DSBGA)
ORDERABLE PART NUMBER
TOP-SIDE MARKING(2)
SN74LVC1G38YEPR
0.23-mm Large Bump – YEP
Reel of 3000
_ _ _D7_
NanoFree™ – WCSP (DSBGA)
0.23-mm Large Bump – YZP (Pb-free)
SN74LVC1G38YZPR
–40°C to 85°C
Reel of 3000 SN74LVC1G38DBVR
Reel of 250 SN74LVC1G38DBVT
Reel of 3000 SN74LVC1G38DCKR
Reel of 250 SN74LVC1G38DCKT
SOT (SOT-23) – DBV
SOT (SC-70) – DCK
C38_
D7_
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/sc/package.
(2) DBV/DCK: The actual top-side marking has one additional character that designates the assembly/test site.
YEP/YZP: The actual top-side marking has three preceding characters to denote year, month, and sequence code, and one following
character to designate the assembly/test site. Pin 1 identifier indicates solder-bump composition (1 = SnPb, = Pb-free).
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
NanoStar, NanoFree are trademarks of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2004–2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
SN74LVC1G38
SINGLE 2-INPUT NAND GATE
WITH OPEN-DRAIN OUTPUT
www.ti.com
SCES538A–JANUARY 2004–REVISED APRIL 2005
FUNCTION TABLE
INPUTS
OUTPUT
Y
A
L
B
L
H
H
H
L
L
H
L
H
H
H
LOGIC DIAGRAM (POSITIVE LOGIC)
1
A
4
Y
2
B
Absolute Maximum Ratings(1)
over operating free-air temperature range (unless otherwise noted)
MIN
–0.5
–0.5
–0.5
MAX
UNIT
V
VCC
VI
Supply voltage range
Input voltage range(2)
Voltage range applied to any output in the high-impedance or power-off state(2)
6.5
6.5
V
VO
IIK
6.5
V
Input clamp current
VI < 0
–50
–50
±50
±100
206
252
132
150
mA
mA
mA
mA
IOK
IO
Output clamp current
VO < 0
Continuous output current
Continuous current through VCC or GND
DBV package
θJA
Package thermal impedance(3)
DCK package
°C/W
°C
YEP/YZP package
Tstg
Storage temperature range
–65
(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed.
(3) The package thermal impedance is calculated in accordance with JESD 51-7.
2
SN74LVC1G38
SINGLE 2-INPUT NAND GATE
WITH OPEN-DRAIN OUTPUT
www.ti.com
SCES538A–JANUARY 2004–REVISED APRIL 2005
Recommended Operating Conditions(1)
MIN
1.65
MAX UNIT
Operating
5.5
V
VCC
Supply voltage
Data retention only
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
VCC = 1.65 V to 1.95 V
VCC = 2.3 V to 2.7 V
VCC = 3 V to 3.6 V
VCC = 4.5 V to 5.5 V
1.5
0.65 × VCC
1.7
VIH
High-level input voltage
V
2
0.7 × VCC
0.35 × VCC
0.7
VIL
Low-level input voltage
V
0.8
0.3 × VCC
VI
Input voltage
0
0
5.5
5.5
4
V
V
VO
Output voltage
VCC = 1.65 V
VCC = 2.3 V
8
IOL
Low-level output current
16
24
32
20
10
5
mA
VCC = 3 V
VCC = 4.5 V
VCC = 1.8 V ± 0.15 V, 2.5 V ± 0.2 V
VCC = 3.3 V ± 0.3 V
VCC = 5 V ± 0.5 V
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
ns/V
°C
TA
–40
85
(1) All unused inputs of the device must be held at VCC or GND to ensure proper device operation. Refer to the TI application report,
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
Electrical Characteristics
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
1.65 V to 5.5 V
1.65 V
MIN TYP(1) MAX
UNIT
IOL = 100 µA
IOL = 4 mA
IOL = 8 mA
IOL = 16 mA
IOL = 24 mA
IOL = 32 mA
0.1
0.45
0.3
2.3 V
VOL
V
0.4
3 V
0.55
0.55
±1
4.5 V
1.65 V to 5.5 V
0
II
A or B inputs VI = 5.5 V or GND
VI or VO = 5.5 V
µA
µA
µA
µA
pF
pF
Ioff
ICC
∆ICC
Ci
±10
10
VI = 5.5 V or GND,
IO = 0
1.65 V to 5.5 V
3 V to 5.5 V
3.3 V
One input at VCC – 0.6 V,
Other inputs at VCC or GND
500
3.5
VI = VCC or GND
VO = VCC or GND
Co
3.3 V
4.5
(1) All typical values are at VCC = 3.3 V, TA = 25°C.
Switching Characteristics
over recommended operating free-air temperature range, CL = 15 pF (unless otherwise noted) (see Figure 1)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
± 0.15 V ± 0.2 V ± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
2.9 7.4 1.7 3.8 1.5 4.9 0.9 2.4
tpd
A or B
Y
ns
3
SN74LVC1G38
SINGLE 2-INPUT NAND GATE
WITH OPEN-DRAIN OUTPUT
www.ti.com
SCES538A–JANUARY 2004–REVISED APRIL 2005
Switching Characteristics
over recommended operating free-air temperature range, CL = 30 pF or 50 pF (unless otherwise noted) (see Figure 2)
VCC = 1.8 V VCC = 2.5 V VCC = 3.3 V
± 0.15 V ± 0.2 V ± 0.3 V
VCC = 5 V
± 0.5 V
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN MAX MIN MAX MIN MAX MIN MAX
2.8 10 1.6 1.4 4.5 3.9
tpd
A or B
Y
6
1
ns
Operating Characteristics
TA = 25°C
VCC = 1.8 V VCC = 2.5 V
VCC = 3.3 V
VCC = 5 V
PARAMETER
TEST CONDITIONS
UNIT
TYP
TYP
TYP
TYP
Cpd
Power dissipation capacitance
f = 10 MHz
3
3
4
6
pF
4
SN74LVC1G38
SINGLE 2-INPUT NAND GATE
WITH OPEN-DRAIN OUTPUT
www.ti.com
SCES538A–JANUARY 2004–REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
V
LOAD
S1
Open
R
L
TEST
S1
From Output
Under Test
GND
t
(see Notes E and F)
(see Notes E and G)
V
V
V
PZL
LOAD
LOAD
LOAD
R
L
C
L
t
PLZ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
M
V
LOAD
C
L
V
∆
R
L
V
CC
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
V
/2
/2
2 × V
2 × V
6 V
1 MΩ
1 MΩ
1 MΩ
1MΩ
0.15 V
0.15 V
0.3 V
15 pF
15 pF
15 pF
15 pF
CC
CC
CC
V
CC
V
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
2 × V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
/2
/2
LOAD
V
V
OH
V
V
V
V
V
M
M
M
Output
V
V
+ V
∆
OL
S1 at V
LOAD
OL
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
V
LOAD
V
V
OH
- V
∆
LOAD/2
M
V
M
M
Output
S1 at V
LOAD
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t
and t are the same as t .
PZL pd
PLZ
F.
G.
t
t
is measured at V .
M
is measured at V + V .
∆
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 1. Load Circuit and Voltage Waveforms
5
SN74LVC1G38
SINGLE 2-INPUT NAND GATE
WITH OPEN-DRAIN OUTPUT
www.ti.com
SCES538A–JANUARY 2004–REVISED APRIL 2005
PARAMETER MEASUREMENT INFORMATION
(OPEN DRAIN)
V
LOAD
S1
Open
R
L
TEST
S1
From Output
Under Test
GND
t
(see Notes E and F)
(see Notes E and G)
V
V
V
PZL
LOAD
LOAD
LOAD
R
L
C
L
t
PLZ
(see Note A)
t
/t
PHZ PZH
LOAD CIRCUIT
INPUT
V
M
V
LOAD
C
L
V
∆
R
L
V
CC
V
I
t /t
r f
1.8 V ± 0.15 V
2.5 V ± 0.2 V
3.3 V ± 0.3 V
5 V ± 0.5 V
V
≤ 2 ns
≤ 2 ns
≤ 2.5 ns
≤ 2.5 ns
V
/2
/2
2 × V
2 × V
6 V
1 kΩ
500 Ω
500 Ω
500 Ω
0.15 V
0.15 V
0.3 V
30 pF
30 pF
50 pF
50 pF
CC
CC
CC
V
CC
V
CC
CC
3 V
1.5 V
/2
V
CC
V
CC
2 × V
CC
0.3 V
V
I
Timing Input
Data Input
V
M
0 V
t
w
t
t
h
su
V
I
V
I
V
M
V
M
Input
V
M
V
M
0 V
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
V
V
I
I
Output
Control
V
M
V
M
V
M
V
M
Input
0 V
0 V
t
t
t
t
t
PHL
PZL
PLZ
PLH
Output
Waveform 1
V
V
/2
/2
LOAD
V
V
OH
V
V
V
V
V
M
M
M
Output
V
V
+ V
∆
OL
S1 at V
LOAD
OL
OL
(see Note B)
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
V
LOAD
V
V
OH
- V
∆
LOAD/2
M
V
M
M
Output
S1 at V
LOAD
≈0 V
OL
(see Note B)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. C includes probe and jig capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω.
O
D. The outputs are measured one at a time, with one transition per measurement.
E. Since this device has open-drain outputs, t
and t are the same as t .
PZL pd
PLZ
F.
G.
t
t
is measured at V .
M
is measured at V + V .
∆
OL
PZL
PLZ
H. All parameters and waveforms are not applicable to all devices.
Figure 2. Load Circuit and Voltage Waveforms
6
PACKAGE OPTION ADDENDUM
www.ti.com
26-Apr-2005
PACKAGING INFORMATION
Orderable Device
SN74LVC1G38DBVR
SN74LVC1G38DBVT
SN74LVC1G38DCKR
SN74LVC1G38DCKT
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOT-23
DBV
5
5
5
5
3000
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
SOT-23
SC70
DBV
DCK
DCK
250
Pb-Free
(RoHS)
CU NIPDAU Level-1-260C-UNLIM
3000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SC70
250 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74LVC1G38YEPR
SN74LVC1G38YZPR
ACTIVE
ACTIVE
WCSP
WCSP
YEP
YZP
5
5
3000
3000
TBD
SNPB
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Pb-Free
(RoHS)
SNAGCU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MPDS025C – FEBRUARY 1997 – REVISED FEBRUARY 2002
DCK (R-PDSO-G5)
PLASTIC SMALL-OUTLINE PACKAGE
0,30
0,15
M
0,10
0,65
5
4
0,13 NOM
1,40 2,40
1,10 1,80
1
3
Gage Plane
2,15
1,85
0,15
0°–8°
0,46
0,26
Seating Plane
0,10
1,10
0,80
0,10
0,00
4093553-2/D 01/02
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion.
D. Falls within JEDEC MO-203
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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